NXP Semiconductors FXTH870 D Series User manual

Freescale Semiconductor Document Number: FXTH870xD
Data Sheet: Advance Information Rev. 1.4, 02/2015
Thisdocumentcontainsinformation on a new product. Specifications andinformation herein
are subject to change without notice.
An Energy-Efficient Solution by Freescale
© 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
FXTH870xD Tire Pressure Monitor
Sensor
The FXTH870xD family is comprised of the following functions all within the
same package.
Features
• Pressure sensor with one of two calibrated pressure ranges
— 100 - 450 kPa
— 100 - 900 kPa
• Temperature sensor
• Optional XZ- or Z-axis accelerometer with adjustable offset option
• Voltage reference measured by ADC10
• Six-channel, 10-bit analog-to-digital converter (ADC10) with two external
I/O inputs
• 8-bit MCU
— S08 Core with SIM and interrupt
— 512 RAM
— 8K FLASH (in addition to 8K providing factory firmware and trim
data)
— 64-byte, low-power, parameter registers
• Dedicated state machines to sequence routine measurement and
transmission processes for reduced power consumption
• Internal 315-/434-MHz RF transmitter
— External crystal oscillator
— PLL-based output with fractional-n divider
— OOK and FSK modulation capability
— Programmable data rate generator
— Manchester, Bi-Phase or NRZ data encoding
— 256-bit RF data buffer variable length interrupt
— Direct access to RF transmitter from MCU for unique formats
— Low power consumption (less than 8 mA at 434 MHz, 5 dBM at
3.0 V, 25 °C)
• Differential input LF detector/decoder on independent signal pins
• Seven multipurpose GPIO pins
— Four pins can be connected to optional internal pullups/pulldowns and STOP4 wakeup interrupt
— Two of seven pins can be connected to a channel on the ADC10
— Two of seven pins can be connected to a channel on the TPM1
• Real-Time Interrupt driven by LFO with interrupt intervals of
8, 16, 32, 64, 128, 256, 512 or 1024 ms
• Low-power, wakeup timer and periodic reset driven by LFO
• Watchdog timeout with selectable times and clock sources
• Two-channel general purpose timer/PWM module (TPM1)
FXTH870xD
Top view
Pin connections
20 21 22 23 24
18 PTA3
LFA
LFB
BKGD/PTA4
X0
X1
17
19
2
3
4
5
6
7
PTB1
PTA2
PTA1
8
1
RESET
10 11 12
13
14
15
VDD
VDDA
VSSA
VREG
RF
16
9
PTB0 N/C N/C N/C N/C N/C
ID Feature
on top lid
PTA0
VSS
RFVSS
Top and bottom view
24-Pin, 1-hole lid
7 x 7 QFN

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 2
• Internal oscillators
— MCU bus clock of 0.5, 1, 2 and 4 MHz (1, 2, 4 and 8 MHz HFO)
— Low frequency, low power time clock (LFO) with 1 ms period
— Medium frequency, controller clock (MFO) of 8 sec period
• Low-voltage detection
• Normal temperature restart in hardware (over- or under-temperature detected by software)
ORDERING INFORMATION
Part number Accelerometer axis Package Range Code1
FXTH870502DT1 Z 2264 (7 x 7, 1-hole lid) 100-450 kPa $08
FXTH870511DT1 XZ 2264 (7 x 7, 1-hole lid) 100-450 kPa $0C
FXTH870902DT1 Z 2264 (7 x 7, 1-hole lid) 100-900 kPa $18
FXTH870911DT1 XZ 2264 (7 x 7, 1-hole lid) 100-900 kPa $1C
FXTH870912DT1 XZ Ext. Range 2264 (7 x 7, 1-hole lid) 100-900 kPa $1E
Related Documentation
The FXTH870xD device features and operations are described in a variety of reference manuals, user guides, and application
notes. To find the most-current versions of these documents:
1. Go to the Freescale homepage at: http://www.freescale.com/
2. In the Keyword search box at the top of the page, enter the device number FXTH870xD.

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 1
Contents
1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Overall Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Multi-Chip Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Recommended Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 RUN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 ACTIVE BACKGROUND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Reset and Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 MCU Register Addresses and Bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 High Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 MCU Parameter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 MCU RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9 FLASH Registers and Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Reset, Interrupts and System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 MCU Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 SIM Test Register (SIMTST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6 Low-Voltage Detect (LVD) System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7 System Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.8 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.9 Real Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.10 Temperature Sensor and Restart System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.11 Reset, Interrupt and System Control Registers And Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.12 System STOP Exit Status Register (SIMSES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 General Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Unused Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 Pin Behavior in STOP Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3 General Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7 Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.5 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3 Programmer’s Model and CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.5 Special Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.6 HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FXTH870xD
Sensors
2Freescale Semiconductor, Inc.
9 Timer Pulse-Width Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2 TPM1 Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.6 TPM1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10 Other MCU Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.2 Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3 Voltage Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.4 Optional Acceleration Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.5 Optional Battery Condition Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.6 Measurement Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.7 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11 Periodic Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2 Wakeup Divider Register - PWUDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3 PWU Control/Status Register 0 - PWUCS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.4 PWU Control/Status Register 1 - PWUCS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.5 PWU Wakeup Status Register - PWUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.6 Functional Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12 LF Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4 Input Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.5 LFR Data Mode States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.6 Carrier Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.7 Auto-Zero Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.8 Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.9 Data Clock Recovery and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.10 Manchester Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.11 Duty-Cycle For Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.12 Input Signal Envelope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.13 Telegram Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.14 Error Detection and Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.15 Continuous ON Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.16 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.17 LFR Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.1 RF Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.2 RF Output Buffer Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.3 Transmission Randomization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.4 RFM in STOP1 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.5 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.6 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 119
13.7 RF Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.8 Datagram Transmission Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.9 RFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.10 RFM Control Register 1 - RFCR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.11 RFM Control Register 2 - RFCR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.12 RFM Control Register 3 - RFCR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.13 RFM Control Register 4 - RFCR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.14 RFM Control Register 5 - RFCR5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.15 RFM Control Register 6 - RFCR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.16 RFM Control Register 7 - RFCR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.19 EPR Register - EPR (RPAGE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.20 RF DATA Registers - RFD[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.21 VCO Calibration Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 3
14 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.1 Software Jump Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.2 Function Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.3 Memory Resource Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.2 Background Debug Controller (BDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16 Battery Charge Consumption Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.1 Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.2 Measurement Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.3 Transmission Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.4 Total Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
17.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.4 Power Consumption (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
17.6 Voltage Measurement Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
17.7 Temperature Measurement Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
17.8 Pressure Measurement Characteristic (100 to 450 kPa ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
17.9 Pressure Measurement Characteristic (100 to 900 kPa Ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
17.10 Optional Acceleration Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
17.11 LFR Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17.12 LFR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
17.13 LFR Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
17.14 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17.15 Power Consumption RF Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
18 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.2 Media Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18.3 Mounting Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
20 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

FXTH870xD
Sensors
4Freescale Semiconductor, Inc.
1 General Information
1.1 Overall Block Diagram
The block diagram of the FXTH870xD is shown in Figure 1. This diagram covers all the main blocks mentioned above and their
main signal interactions. Power management controls and bus control signals are not shown in this block diagram for clarity.
1.2 Multi-Chip Interface
The FXTH870xD contains two to three devices using the best process technology for each.
• Microcontroller with accelerometer and pressure sensor interfaces, and RF transmitter (MCU)
• Optional ranges on pressure transducers
• Optional XZ- or Z-axis acceleration transducer
As shown in Figure 1 the MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers
connect to the MCU using custom analog interfaces and inter-chip bonding wires.
1.3 System Clock Distribution
The various clock sources and their distribution are shown in Figure 2. All clock sources except the low frequency oscillator, LFO,
can be turned off by software control in order to conserve power.

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 5
Figure 1. FXTH870xD Overall Block Diagram
8K USER
FLASH
MEMORY
RAM
MEMORY
512
TPM1
TIMER/PWM
2-CHAN
LVD
RTI
TIMER
MCU CORE
S08
AVDD
TEMP AVDD
AVSS
TEMP
SENSOR
PRESS
SENSOR
BANDGAP
REF
LFA
PTA1
ADC10
10-BIT
6-CHAN
TEMP
BKGD /
LFB
64 Byte
PARAMETER
REGISTER
DATA
ENCODE
BIT
RATE
256-BIT
DATA
BUFFER
RF
AMP
VCO/PLL
FRACTL
DIVIDER
XTAL
OSC
XI
XO
RF
MCU
TRANSDUCERS
VOLT
REG
RESTART
OSC
GEN
PWU
TIMER
MFO
8 Sec
RESET
LF
RECVR
DX
V
SENS
V
TP
V
0
LFO
1 ms
LFI
SMI
Z
HFO
1, 2, 4 or 8
MHz
GP
I/O
KEY
KBI
BOARD
WAKEUP
MFO
8K
FIRMWARE
MEMORY
PTA0
P
SENSOR MEASUREMENT
(SMI)
RF CONTROLLER
INTERFACE
LFO
(LFR)
RFM
VREG
PTA2
VDD
VDD
VSS
RVSS
PTA3
V
1
V
2
RF LVD
AVDD
RFVDD
VREG
PTB0
PTB1
PTA4
XZ
XZ
ACCEL
(OPTION)
Z
ACCEL
(OPTION)

FXTH870xD
Sensors
6Freescale Semiconductor, Inc.
Figure 2. FXTH870xD Clock Distribution
1.4 Reference Documents
The FXTH870xD utilizes the standard product MC9S08 CPU core. The user can obtain further detail on the full capabilities of
this core by referring to the HCS08 Family Reference Manual (HCS08RMV1).
RTI
SYSTEM
CONTROL
LOGIC
2
HFO OSC
1, 2, 4, fOSC fBUS
CPU
BDC
TPM1
RAM FLASH
LFR
ADC10
MFO
OSC
8 Sec
PWU
CLSA, CLKSB
fLFO (1 kHz)
XTL
OSC
26 MHz
XI XO PLL VCO
BIT
RATE
DATA
BUFFER
PRESSURE
SENSOR
TRANSDUCERS
MCU
RTICLKS
PAR
REG
fMFO
fXCO
GEN
DX(500 kHz)
LFO
OSC
1 mS
PERIOD
SENSOR MEASUREMENT
INTERFACE
ADC10
CLOCK
ADCCLK ADC10
BUSCLKS[1:0]
WATCH
DOG
COPCLKS
Z-AXIS
SENSOR
LF
4 kbps
(125 kHz)
RF STATE
MACHINE
LFRO
OSCILL
8
TCLKDIV
LFOSEL
fMFO
PTA3
PTA2
fLFO (1 kHz)
CH0 CH1
RANDOM
(0 - 1 MHz)
RANDOM
(0 - 1 MHz)
RF
OUT 41.67 kHz
Sampling 41.67 kHz
Sampling
and 8 MHz
X-AXIS
SENSOR
41.67 kHz
Sampling

FXTH870xD
Sensors
Freescale Semiconductor, Inc. 7
2 Pins and Connections
This section describes the pin layout and general function of each pin.
2.1 Package Pinout
The pinout for the FXTH870xD device QFN package is shown in Figure 3 for the orientation of the pressure port up. The
orientation of the internal Z-axis accelerometer is shown in Figure 4.
Figure 3. FXTH870xD QFN Package Pinout
Figure 4. FXTH870xD QFN Optional Z-axis Accelerometer Orientation
2.2 Recommended Application
Example of a simple OOK/FSK tire pressure monitors using the internal PLL-based RF output stage is shown in Figure 5. Any of
the PTA[3:0] pins can also be used as general purpose I/O pins. Any of the PTA[3:0] pins that are not used in the application
should be handled as described in Section 6.1.
20 21 22 23 24
18 PTA3
LFA
LFB
BKGD/PTA4
X0
X1
17
19
2
3
4
5
6
7
PTB1
PTA2
PTA1
8
1
RESET
10 11 12
13
14
15
VDD
VDDA
VSSA
VREG
RF
16
9
PTB0 N/C N/C N/C N/C N/C
ID Feature
on top lid
PTA0
VSS
RFVSS
N/C = No Connect: Do not connect PCB pads to signal traces, power/ground or multi-layer via.
Top View
BKGD/PTA4
X-AXIS
ORIENTATION
+X
-X
Y-AXIS
ORIENTATION
+Y
-Y
Side View
Pressure
Port
POSITIVE ACCELERATION MOVES MASS
IN +Z DIRECTION (VALUE INCREASES)
Z-AXIS
ORIENTATION
+Z
-Z

FXTH870xD
Sensors
8Freescale Semiconductor, Inc.
2.3 Signal Properties
The following sections describe the general function of each pin.
g
Figure 5. FXTH870xD Example Application
2.3.1 VDD and VSS Pins
The digital circuits operate from a single power supply connected to the FXTH870xD through the VDD and VSS pins. VDD is the
positive supply and VSS is the ground. The conductors to the power supply should be connected to the VDD and VSS pins and
locally decoupled as shown in Figure 6.
Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a “star”
connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.
2.3.2 AVDD and AVSS Pins
The analog circuits operate from a single power supply connected to the FXTH870xD through the AVDD and AVSS pins. AVDD is
the positive supply and AVSS is the ground. The conductors to the power supply should be connected to the AVDD and AVSS pins
and locally decoupled as shown in Figure 6.
FXTH870xxx
0.1 µF
VDD
VSS
3.0 V
BATTERY
LF
COIL
XTAL
RF
RVSS
XI
XO
C1
ANT
L1
BKGD/PTA4
LFA
LFB
PTA1
RESET
GENERAL
PURPOSE I/O
PTA0
PTA2
AVDD
AVSS
VREG
470 nF
0.1 µF
PTA3
MATCHING
NETWORK
C2 C3
C2, C3, C4
optimized
for crystal
C5
C4*
R2 R3
R2 and R3, <10 k
recommended for
highest EMC resistance
R1
PTB0
PTB1
L1 and matching network
optimized for specific PWB and
antenna layout. Recommend
0603 minimum size for L1 and
other matching network inductors
for maximum efficiency.
C1 and R1 optimized
for coil used, but
recommended
RC < 15.3 sec.
The device C4, although drawn here as a capacitor, may be any type of passive component(s) sufficient to block
or reduce unwanted external radiated signals from corrupting the crystal oscillator circuit: PCB traces for the LFA
/ LFB, AVDD / VDD, and VSS / AVSS pins and bypass capacitors should be minimized to reduce unwanted external
radiated signals from corrupting the power input circuits.

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Freescale Semiconductor, Inc. 9
Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a “star”
connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.
Figure 6. Recommended Power Supply Connections
2.3.3 VREG Pin
The internal regulator for the analog circuits requires an external stabilization capacitor to AVSS.
2.3.4 RVSS Pin
Power in the RF output amplifier is returned to the supply through the RVSS pin. This conductor should be connected to the power
supply as shown in Figure 6 using a “star” connection such that each metal trace does not share any load currents with other
supply pins.
2.3.5 RF Pin
The RF pin is the RF energy data supplied by the FXTH870xD to an external antenna.
2.3.6 XO, XI Pins
The XO and XI pins are for an external crystal to be used by the internal PLL for creating the carrier frequencies and data rates
for the RF pin.
2.3.7 LF[A:B] Pins
The LF[A:B] pins can be used by the LF receiver (LFR) as one differential input channel for sensing low level signals from an
external low frequency (LF) coil. The external LF coil should be connected between the LFA and the LFB pins.
Signaling into the LFR pins can place the FXTH870xD into various diagnostic or operational modes. The LFR is comprised of
the detector and the decoder.
Each LF[A:B] pin will always have an impedance of approximately 500 kto VSS due to the LFR input circuitry. The LFA/LFB
pins are used by the LFR when the LFEN control bit is set and are not functional when the LFEN control bit is clear.
2.3.8 PTA[1:0] Pins
The PTA[1:0] pins are general purpose I/O pins. These two pins can be configured as normal bidirectional I/O pins with
programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input
channels of the A/D converter module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled.
User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described in
Section 6.1. PTA[1:0] map to Keyboard Interrupt function bits [1:0].
0.1 µF
FXTH870xxx
VDD
VSS
to other
Battery
IDD ILOAD
Bypass capacitors
closely coupled to
the package pins
FXTH870xxx and Other Load Currents
star connected to battery terminals
loads
0.1 µF
AVDD
AVSS
RVSS
The decoupling devices, although
drawn here as 0.1 F capacitors,
may be any type of passive component(s)
sufficient to block or reduce unwanted
external radiated signals from corrupting
the power input protection circuits;
application tuning may be required.

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10 Freescale Semiconductor, Inc.
2.3.9 PTA[3:2] Pins
The PTA[3:2] pins are general purpose I/O pin. These two pins can be configured as normal bidirectional I/O pin with
programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input
channels of the Timer Pulse Width (TPM1) module. The pulldown devices can only be activated if the wakeup interrupt capability
is enabled. User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described
in Section 6.1. PTA[3:2] map to Keyboard Interrupt function bits [3:2].
2.3.10 BKGD/PTA4 Pin
The BKGD/PTA4 pin is used to place the FXTH870xD in the BACKGROUND DEBUG mode (BDM) to evaluate MCU code and
to also transfer data to/from the internal memories. If the BKGD/PTA4 pin is held low when the FXTH870xD comes out of a power-
on reset the device will go into the ACTIVE BACKGROUND DEBUG mode (BDM).
The BKGD/PTA4 pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter
BDM operation after the device as been soldered into the PWB. If in-circuit BDM is desired the BKGD/PTA4 pin can be left
unconnected, but should be connected to VDD through a low impedance resistor (<10 k) which can be over-driven by an
external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an
EMC event.
2.3.11 RESET Pin
The RESET pin is used for test and establishing the BDM condition and providing the programming voltage source to the internal
FLASH memory. This pin can also be used to direct to the MCU to the reset vector as described in Section 5.2.
The RESET pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter BDM
operation after the device as been soldered to the PWB. If in-circuit BDM is desired the RESET pin can be left unconnected; but
should be connected to VDD through a low impedance resistor (<10 k) which can be over-driven by an external signal. This low
impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event.
Activation of the external reset function occurs when the voltage on the RESET pin goes below 0.3 x VDD for at least 100 nsec
before rising above 0.7 x VDD as shown in Figure 7.
Figure 7. RESET Pin Timing
2.3.12 PTB[1:0] Pins
The PTB[1:0] pins are general purpose I/O pins. These two pins can be configured as nominal bidirectional I/O pins with
programmable pullup devices. User software must configure the general purpose I/O pins so that they do not result in “floating”
inputs as described in Section 6.1
RESET 0.7 VDD
0.3 VDD
> 100 nsec
Reset
Initiated

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3 Modes of Operation
The operating modes of the FXTH870xD are described in this section. Entry into each mode, exit from each mode, and
functionality while in each of the modes are described.
3.1 Features
• ACTIVE BACKGROUND DEBUG mode for code development
• STOP modes:
— System clocks stopped
— STOP1: Power down of most internal circuits, including RAM, for maximum power savings; voltage regulator in
standby
— STOP4: All internal circuits powered and full voltage regulation maintained for fastest recovery
3.2 RUN Mode
This is the normal operating mode for the FXTH870xD. This mode is selected when the BKGD/PTA4 pin is high at the rising edge
of reset. In this mode, the CPU executes code from internal memory following a reset with execution beginning at address
specified by the reset pseudo-vector ($DFFE and $DFFF).
3.3 WAIT Mode
The WAIT mode is also present like other members of the Freescale S08 family members; but is not normally used by the
FXTH870xD firmware or typical TPMS applications.
3.4 ACTIVE BACKGROUND Mode
The ACTIVE BACKGROUND mode functions are managed through the BACKGROUND DEBUG controller (BDC) in the HCS08
core. The BDC provides the means for analyzing MCU operation during software development.
ACTIVE BACKGROUND mode is entered in any of four ways:
• When the BKGD/PTA4 pin is low at the rising edge of a power up reset
• When a BACKGROUND command is received through the BKGD/PTA4 pin
• When a BGND instruction is executed by the CPU
• When encountering a BDC breakpoint
Once in ACTIVE BACKGROUND mode, the CPU is held in a suspended state waiting for serial BACKGROUND commands
rather than executing instructions from the user’s application program. Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive
commands can be issued through the BKGD/PTA4 pin while the MCU is in RUN mode; non-intrusive commands can also
be executed when the MCU is in the ACTIVE BACKGROUND mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• ACTIVE BACKGROUND commands, which can only be executed while the MCU is in ACTIVE BACKGROUND mode.
ACTIVE BACKGROUND commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave ACTIVE BACKGROUND mode to return to the user’s application program (GO)
The ACTIVE BACKGROUND mode is used to program a bootloader or user application program into the FLASH program
memory before the MCU is operated in RUN mode for the first time. When the FXTH870xD is shipped from the Freescale factory,
the FLASH program memory is erased by default (unless specifically requested otherwise) so there is no program that could be
executed in RUN mode until the FLASH memory is initially programmed.
The ACTIVE BACKGROUND mode can also be used to erase and reprogram the FLASH memory after it has been previously
programmed.

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12 Freescale Semiconductor, Inc.
3.5 STOP Modes
One of two stop modes are entered upon execution of a STOP instruction when the STOPE bit in the system option register is
set. In all STOP modes, all internal clocks are halted except for the low frequency 1 kHz oscillator (LFO) which runs continuously
whenever power is applied to the VDD and VSS pins. If the STOPE bit is not set when the CPU executes a STOP instruction, the
MCU will not enter any of the STOP modes and an illegal opcode reset is forced. The STOP modes are selected by setting the
appropriate bitsin SPMSC2. Table 1 summarizes the behavior of the MCU in each of the STOP1 and STOP4 modes. The STOP2
mode found in other Freescale S08 family members is not available; but the STOP3 mode is present like other members of the
Freescale S08 family members.
3.5.1 STOP1 Mode
The STOP1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be
powered down.
When the MCU is in STOP1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage
regulator is in a low-power standby state. STOP1 is exited by asserting either a reset or an interrupt function to the MCU.
Entering STOP1 mode automatically asserts LVD. STOP1 cannot be exited until the VDD is greater than VLVDH or VLV/DL rising
(VDD must rise above the LVI re-arm voltage).
Upon wakeup from STOP1 mode, the MCU will start up as from a power-on reset (POR) by taking the reset vector.
NOTE
If there are any pending interrupts that have yet to be serviced then the device will not go
into the STOP1 mode. Be certain that all interrupt flags have been cleared before entry to
STOP1 mode.
3.5.2 STOP4 LVD Enabled in STOP Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If
the LVD is enabled by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the
voltage regulator remains active during STOP mode. If the user attempts to enter the STOP1 with the LVD enabled in STOP
(LVDSE = 1), the MCU will enter STOP4 instead.
Table 1. STOP Mode Behavior
Mode STOP1 STOP4
LFO Oscillator, PWU Always On & Clocking
Real-Time Interrupt (RTI)(1) Always On if using LFO as Clock
MFO Oscillator(2) Optionally On Optionally On
HFO Oscillator Off Off
CPU Off Standby
RAM Off Standby
Parameter Registers On On
FLASH Off Standby
TPM1 2-Chan Timer/PWM Off Off
Digital I/O Disabled Standby
Sensor Measurement Interface (SMI) Off Optionally On
Pressure P-cell Off Optionally On
Optional Acceleration g-cell Off Optionally On
Temperature Sensor (in ADC10) Off Optionally On(3)
Normal Temperature Restart Optionally On Optionally On
Voltage Reference (in ADC10) Off Optionally On(3)
LFR Detector(4) Periodically On Periodically On
LFR Decoder Optionally On Optionally On
RF Controller, Data Buffer, Encoder Optionally On Optionally On
RF Transmitter(5) Optionally On Optionally On
ADC10 Off Optionally On(3)

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Specific to the tire pressure monitoring application the parameter registers and the LFO with wakeup timer are powered up at all
times whenever voltage is applied to the supply pins. The LFR detector and MFO may be periodically powered up by the LFR
decoder.
3.5.3 Active BDM Enabled in STOP Mode
Entry into the ACTIVE BACKGROUND DEBUG mode from RUN mode is enabled if the ENBDM bit in BDCSCR is set. The
BDCSCR register is not memory mapped so it can only be accessed through the BDM interface by use of the BDM commands
READ_STATUS and WRITE_CONTROL. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the
BACKGROUND DEBUG logic remain active when the MCU enters STOP mode so BACKGROUND DEBUG communication is
still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter the STOP1 with ENDBM set, the MCU will instead enter this mode which is STOP4 with system clocks
running.
Most BACKGROUND commands are not available in STOP mode. The memory-access-with-status commands do not allow
memory access, but they report an error indicating that the MCU is in STOP mode. The BACKGROUND command can be used
to wake the MCU from stop and enter ACTIVE BACKGROUND mode if the ENDBM bit is set. Once in BACKGROUND DEBUG
mode, all BACKGROUND commands are available.
3.5.4 MCU On-Chip Peripheral Modules in STOP Modes
When the MCU enters any STOP mode, system clocks to the internal peripheral modules except the wakeup timer and LFR
detectors/decoder are stopped. Even in the exception case (ENDBM = 1), where clocks are kept alive to the BACKGROUND
debug logic, clocks to the peripheral systems are halted to reduce power consumption.
I/O Pins
If the MCU is configured to go into STOP1 mode, the I/O pins are forced to their default reset state (Hi-Z) upon entry into stop.
This means that the I/O input and output buffers are turned off and the pullup is disconnected.
Memory
All module interface registers will be reset upon wakeup from STOP1 and the contents of RAM are not preserved. The MCU must
be initialized as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the STOP modes.
Parameter Registers
The 64 bytes of parameter registers are kept active in all modes of operation as long as power is applied to the supply pins. The
contents of the parameter registers behave like RAM and are unaffected by any reset.
LFO
The LFO remains active regardless of any mode of operation.
MFO
The medium frequency oscillator (MFO) will remain powered up when the MCU enters the STOP mode only when the SMI has
been initiated to make a pressure or acceleration measurement; or when the RF transmitter’s state machine is processing data.
HFO
The HFO is halted in all STOP modes.
PWU
The PWU remains active regardless of any mode of operation.
Regulator Off On
I/O Pins Hi-Z States Held
Wakeup Methods Interrupts, resets Interrupts, resets
1. RTI can be used in STOP1 or STOP4 if the clock selected is the LFO. To use the HFO as the clock the MCU must be in the RUN mode.
2. MFO oscillator started if the LFR detectors are periodically sampled, the LFR detectors detect an input signal; a pressure or acceleration
reading is in progress or the RF state machine is sending data.
3. Requires internal ADC10 clock to be enabled.
4. Period of sampling set by MCU.
5. RF data buffer may be set up to run while the CPU is in the STOP modes.
Table 1. STOP Mode Behavior (continued)
Mode STOP1 STOP4

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ADC10
The internal asynchronous ADC10 clock is always used as the conversion clock. The ADC10 can continue operation during
STOP4 mode. Conversions can be initiated while the MCU is the STOP4 mode. All ADC10 module registers contain their reset
values following exit from STOP1 mode.
LFR
When the MCU enters STOP mode the detectors in the LFR will remain powered up depending on the states of the bits selecting
the periodic sampling. Refer to Section 12 for more details.
Bandgap Reference
The bandgap reference is enabled whenever the sensor measurement interface requires sensor or voltage measurements.
TPM1
When the MCU enters STOP mode, the clock to the TPM1 module stops and the module halts operation. If the MCU is configured
to go into STOP1 mode, the TPM1 module will be reset upon wakeup from STOP and must be re-initialized.
Voltage Regulator
The voltage regulator enters a low-power standby state when the MCU enters any of the STOP modes except STOP4 (LVDSE
= 1 or ENBDM =1).
Temperature Sensor
The temperature sensor is powered up on command from the MCU.
Temperature Restart
WhentheMCUentersaSTOPmodethetemperaturerestartwillremainpoweredupiftheTREbitisset.Ifthetemperaturerestart
level is reached the MCU will restart from the reset vector.
3.5.5 RFM Module in STOP Modes
The RFM’s external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer, data encoder, and RF output stage will
remain powered up in STOP modes during a transmission, or if the SEND bit has been set and DIRECT mode has been enabled.
RF Output
When the RFM finishes a transmission sequence the external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data
buffer, data encoder, and RF output stage will remain powered up if the SEND bit is set.
3.5.6 P-cell in STOP Modes
The P-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered
down.
3.5.7 Optional g-Cell in STOP Modes
The g-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered
down.

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4Memory
The overall memory map of the FXTH870xD resides on the MCU.
4.1 MCU Memory Map
As shown in Figure 8, MCU on-chip memory in the FXTH870xD consists of parameter registers, RAM, FLASH program memory
for nonvolatile data storage, and I/O and control/status registers. The registers are divided into four groups:
• Direct-page registers ($0000 through $004F)
• Parameter registers ($0050 through $008F)
• RAM ($0090 through $028F)
• High-page registers ($1800 through $182B)
Figure 8. FXTH870xD MCU Memory Map
The total programmable FLASH memory map is 16K, but the upper 8K is used for firmware and test software. Upon power up
thefirmwarewillinitializethedeviceandredirectall vectors totheuser areafrom $DFC0 through $DFFF.Anycallstothefirmware
subroutines are accessed through a jump table starting at location $E000 (see Section 14).
4.2 Reset and Interrupt Vectors
Table 2 shows address assignments for jump table to the reset and interrupt vectors. The vector names shown in this table are
the labels used in the equate file provided by Freescale in the CodeWarrior project file.
Table 2. Vector Summary
User Vector Addr Vector Name Module Source
$DFE0:DFE1 Vkbi KBI
$DFE2:DFE3 Reserved
$DFE4:DFE5 Reserved
$DFE6:DFE7 Vrti Sys Ctrl - RTI
$DFE8:DFE9 Vlfrcvr LFR
$DFEA:DFEB Vadc1 ADC10
$DFEC:DFED Vrf RFM
$0000
$004F
$0050
$008F
$1800
$17FF
$182B
$182C
$FFFF
$0090
$C000
$BFFF
DIRECT PAGE REGISTERS
RAM 512 BYTES
UNIMPLEMENTED
HIGH PAGE REGISTERS
5488 BYTES
41964 BYTES
$028F
$0290
PARAMETER REGISTERS
$DFC0
$DFBF
USER FLASH
8128 BYTES
USER VECTORS
FIRMWARE FLASH
8128 BYTES
$E000
$DFFF
$E040
$E03F
FIRMWARE JUMP TABLE

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4.3 MCU Register Addresses and Bit Assignments
The registers in the FXTH870xD are divided into these four groups:
• Direct-page registers are located in the first 80 locations in the memory map; these are accessible with efficient direct
addressing mode instructions.
• The parameter registers begin at address $0050; these are also accessible with efficient direct addressing mode
instructions.
• High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room in the
direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register
locations include:
— Three values that are loaded into working registers at reset
— An 8-byte back door comparison key that optionally allows the user to gain controlled access to secure memory.
Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory
locations.
Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct
addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to
access any bit in any direct-page register. Table 3 is a summary of all user-accessible direct-page registers and control bits.
Those related to the TPMS application and modules are described in detail in this specification.
The register names in column two of the following tables are shown in bold to set them apart from the bit names to the right. Cells
that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded
cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
$DFEE:DFEF Vsm SMI
$DFF0:DFF1 Vtpm1ovf TPM1
$DFF2:DFF3 Vtpm1ch1 TPM1
$DFF4:DFF5 Vtpm1ch0 TPM1
$DFF6:DFF7 Vwuktmr PWU
$DFF8:DFF9 Vlvd Sys Ctrl - LVD
$DFFA:DFFB Reserved
$DFFC:DFFD Vswi SWI opcode
$DFFE:DFFF Vreset Sys Ctrl - POR, PRF, COP, LVD
Temp Restart, Illegal opcode or address
Table 3. MCU Direct Page Register Summary
AddressRegisterNameBit7654321Bit0
$0000 PTAD PTAD[4:0]
$0001 PTAPE PTAPE[3:0]
$0002 Reserved
$0003 PTADD PTADD[3:0]
$0004 PTBD PTBD[1:0]
$0005 PTBPE PTBPE[1:0]
$0006 Reserved
$0007 PTBDD PTBDD[1:0]
$0008 Reserved
$0009 Reserved
$000A Reserved
$000B Reserved
$000C KBISC 0000 KBF KBACK KBIE KBIMOD
Table 2. Vector Summary (continued)
User Vector Addr Vector Name Module Source

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$000D KBIPE KBIPE[3:0]
$000E KBIES KBEDG[3:0]
$000F Reserved
$0010 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
$0011 TPM1CNTH Bit [15:8]
$0012 TPM1CNTL Bit [7:0]
$0013 TPM1MODH Bit [15:8]
$0014 TPM1MODL Bit [7:0]
$0015 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
$0016 TPM1C0VH Bit [15:8]
$0017 TPM1C0VL Bit [7:0]
$0018 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
$0019 TPM1C1VH Bit [15:8]
$001A TPM1C1VL Bit [7:0]
$001B Reserved
$001C PWUDIV WDIV[5:0]
$001D PWUCS0 WUF WUFAK WUT[5:0]
$001E PWUCS1 PRF PRFAK PRST[5:0]
$001F PWUS PSEL 0 CSTAT[5:0]
$0020-27 LFR Registers LFR Registers, see Table 4 and Table 5
$0028 ADSC1 COCO AIEN ADCO ADCH[4:0]
$0029 ADSC2 ADACT ADTRG ACFE ADCFGT 0 0 0 0
$002A ADRH 0000 ADR[11:8]
$002B ADRL ADR[7:0]
$002C ADCVH 0000 ADCV[11:8]
$002D ADCVL ADCV[7:0]
$002E ADCFG ADLPC ADIV[1:0] ADLSMP MODE[1:0] ADICLK[1:0]
$002F ADPCTL1 ADPC[7:0]
$0030-4F RFM Registers RFM Registers, see Table 6 and Table 7
$0050-8F Parameter Reg PARAM[63:0]
Note: Shaded bits are recommended to only be controlled by firmware or factory test.
Table 4. LFR Register Summary - LPAGE = 0
AddressRegisterNameBit7654321Bit0
$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0]
$0021 LFCTL2 LFSTM[3:0] LFONTM[3:0]
$0022 LFCTL3 LFDO TOGMOD SYNC[1:0] LFCDTM[3:0]
$0023 LFCTL4 LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT[1:0]
$0024 LFS LFDRF LFERF LFCDF LFIDF LFOVF LFEOMF LPSM LFIAK
$0025 LFDATA RXDATA[7:0]
$0026 LFIDL ID[7:0]
$0027 LFIDH ID[15:8]
Table 3. MCU Direct Page Register Summary (continued)
AddressRegisterNameBit7654321Bit0

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Table 5. LFR Register Summary - LPAGE = 1
AddressRegisterNameBit7654321Bit0
$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0]
$0021 LFCTRLE TRIMEE AZSC[2:0]
$0022 LFCTRLD AVFOF[1:0} DEQS AZDC[1:0] ONMODE CHK125[1:0]
$0023 LFCTRLC AMPGAIN[1:0] FINSEL[1:0] AZEN LOWQ[1:0] DEQEN
$0024 LFCTRLB HYST[1:0] LFFAF LFCAF LFPOL LFCPTAZ[2:0]
$0025 LFCTRLA TESTSEL[3:0] LFCC[3:0]
$0026 Reserved
$0027 Reserved
Note: Shaded bits are recommended to only be controlled by firmware or factory test.
Table 6. RFM Register Summary - RPAGE = 0
AddressRegisterNameBit7654321Bit0
$0030 RFCR0 BPS[7:0]
$0031 RFCR1 FRM[7:0]
$0032 RFCR2 SEND RPAGE EOM PWR[4:0]
$0033 RFCR3 DATA IFPD ISPC IFID FNUM[3:0]
$0034 RFCR4 RFBT[7:0]
$0035 RFCR5 BOOST LFSR[6:0]
$0036 RFCR6 VCO_GAIN[1:0] RFFT[5:0]
$0037 RFCR7 RFIF RFEF RFVF RFIAK RFIEN RFLVDEN RCTS RFMRST
$0038 PLLCR0 AFREQ[12:5]
$0039 PLLCR1 AFREQ[4:0] POL CODE[1:0]
$003A PLLCR2 BFREQ[12:5]
$003B PLLCR3 BFREQ[4:0] CF MOD CKREF
$003C RFD0 RFD[7:0]
$003D RFD1 RFD[15:8]
$003E RFD2 RFD[23:16]
$003F RFD3 RFD[31:24]
$0040 RFD4 RFD[39:32]
$0041 RFD5 RFD[47:40]
$0042 RFD6 RFD[55:48]
$0043 RFD7 RFD[63:56]
$0044 RFD8 RFD[71:64]]
$0045 RFD9 RFD[79:72]
$0046 RFD10 RFD[87:80]
$0047 RFD11 RFD[95:88]
$0048 RFD12 RFD[103:96]
$0049 RFD13 RFD[111:104]
$004A RFD14 RFD[119:112]
$004B RFD15 RFD[127:120]
$004C Reserved
$004D Reserved
$004E Reserved
$004F Reserved
Note: Shaded bits are recommended to only be controlled by firmware or factory test.