NXP Semiconductors MMPF0100 Installation manual

© Freescale Semiconductor, Inc., 2014. All rights reserved.
Freescale Semiconductor
Application Note AN4536
Rev. 3.0, 1/2014
1 Introduction
This document provides a detailed description of the
One-TimeProgrammable(OTP)functionofthe MMPF0100.It
providesthesystemrequirementsandinstructionstoprogram
the fuses for a selected power-up configuration. All examples
assume the customer is using silicon revision P1.1 or higher.
Freescale analog ICs are manufactured using the
SMARTMOS process, a combinational BiCMOS
manufacturing flow that integrates precision analog, power
functions and dense CMOS logic together on a single
cost-effective die.
MMPF0100 OTP Programming Instructions
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 OTP Overview. . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Power-up Configuration. . . . . . . . . . . . . . . . 2
2.2 OTP Programming Example . . . . . . . . . . . . 3
2.3 Try-Before-Buy Mode Example. . . . . . . . . . 8
2.4 OTP Registers Description . . . . . . . . . . . . 10
2.5 Fuse Programming and Error Correction Code
(ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Hardware Considerations . . . . . . . . . . . . . . . . 28
3.1 Programming the MMPF0100 on an Application
Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Isolating SCL/SDA. . . . . . . . . . . . . . . . . . . 29
3.3 Programming using the PF-Programmer . 30
3.4 Programming using a Generic Programmer33
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . 35

AN4536 Application Note Rev. 2.0 1/2014
2Freescale Semiconductor
OTP Overview
2 OTP Overview
The regulators in the MMPF0100 have been designed with flexibility and configurability to allow them to be adapted
for a wide variety of applications. One-Time-Programmable (OTP) fuses in the MMPF0100 are used to exercise this
flexibility. Key startup parameters and regulator configuration information can be programmed into the MMPF0100
to enable it to power the system. These parameters are:
•General: I2C slave address, PWRON pin configuration, regulator start-up sequence and timing,
RESETBMCU configuration
•Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching
frequency, and soft start ramp rate
•Boost regulator and LDOs: Output voltage
MMPF0100 starts up based on the contents of the TBBOTP registers. The TBBOTP registers can be loaded from
different sources as shown in Table 1. The default setting is hard-coded in the MMPF0100 and is available in all
non-programmed and programmed MMPF0100 devices. Once OTP programming is complete, TBBOTP can be
either loaded from the default values or from the OTP fuses.
The OTP block in the MMPF0100 also features a ‘Try-Before-Buy’ (TBB) mode which allows experimentation with
different voltages and sequences of the regulators. In the TBB mode, TBBOTP registers are directly written to and
used for startup of the MMPF0100. Contents of the TBBOTP registers can be maintained in the absence of the main
input supply, VIN, by using a coin cell at the LICELL pin.
2.1 Power-up Configuration
The PF0100 powers up based on the contents of the TBBOTP registers. Depending on certain pin and bit settings,
the TBBOTP registers are loaded from different sources as shown in Table 1.
The TBBOTP registers serve as temporary storage for any of the following:
1. The values to be written to the fuses, or
2. The values read from the fuses, or
3. The values to start from during TBB development, or
4. The values read from the default configuration.
The TBBOTP registers are located within the Extended Page 1 of the MMPF0100 register map.
Table 1. Power-up Configuration Source and Conditions
Source Condition Power-Up Configuration
ROM VDDOTP = VCOREDIG(1) MMPF0100 starts up using the factory default settings
TBBOTP Registers VDDOTP = 0 V and TBB_POR = 1 MMPF0100 starts up from current values of TBBOTP registers. This is referred to as the 'Try-Before-Buy'
mode
OTP Fuses VDDOTP = 0 V and
TBB_POR = 0 and FUSE_POR_XOR = 1(2) The MMPF0100 starts up from the OTP fuse values
Notes:
1. Pull-up VDDOTP to VCOREDIG with a 100 k resistor.
2. In MMPF0100, FUSE_POR1, FUSE_POR2 and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be
1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In MMPF0100A, the XOR function is
removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses.

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 3
OTP Overview
During a power-up, the TBBOTP registers behave as follows:
• The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied.
• The values that are then loaded into the TBBOTP registers depend on the setting of the VDDOTP pin, and
on the value of the TBB_POR, and the FUSE_POR_XOR bits. Refer to Table 1.
• If VDDOTP = VCOREDIG (1.5 V), the TBBOTP values are loaded from ROM.
• If VDDOTP = 0 V, TBB_POR = 0 and FUSE_POR_XOR = 1; the TBBOTP values are loadedfrom the fuses.
• If VDDOTP = 0, TBB_POR = 0 and FUSE_POR_XOR=0; the TBBOTP registers remain initialized at zero.
• The initial value of TBB_POR is always “0”, only when VDDOTP = 0 V and TBB_POR is set to “1”, are the
values from the TBBOTP registers maintained and not loaded from a different source.
The contents of the TBBOTP registers may be modified by I2C. To communicate with I2C, VIN must be valid and
VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN or the coin cell
voltage must be valid to maintain the contents of the TBBOTP registers. To power on with the contents of the
TBBOTP registers, a valid turn-on event must occur with the following conditions: a valid VIN, optional LICELL,
VDDOTP = 0 V, TBB_POR = 1.
2.2 OTP Programming Example
The One-Time-Programmable memory is realized using fuses. The startup configuration can be programmed into
the MMPF0100 by changing the state of these fuses as required during the OTP programming process.
There are 10 banks of fuses with each bank consisting of 26 fuses. Of the 26 fuses in a bank, 20 are programmable
by the user. The remaining 6 are redundant fuses that allow implementation of Error Correction. An Error Correction
Code within the MMPF0100 corrects single bit errors if they occur in the bank.
The following is an example of programming the MMPF0100 and MMPF0100A. MMPF0100A refers to the newer
silicon version of MMPF0100. Refer to the product Data Sheet for complete details.
Note that the programming voltage and time-delay during fuse programming is different between the two silicon
revisions. The programming voltage should have a tolerance of +/-3% and OTP programming should be done at
room temperature. For reliability reasons, do not OTP program a given part more than once.
Note: All code examples in this document represent a script using the KITPFPGMEVME and the associated GUI.
Command syntax may vary if the user utilizes a different tool for communication.
//---------------------------------------------------------------------------
// F0 - Sample Configuration
// Set VDDOTP = 0 V, PWRON = HIGH, LICELL = 3.0 V (Optional), VIN = VDDIO = 3.3 V
//---------------------------------------------------------------------------
WRITE_I2C:7F:01 // Access PF0100 EXT Page1
//[Extended Page 1 Registers: 0xA0 - 0xAF] ----------------------------------
WRITE_I2C:A0:2B // Sw1AB Voltage = 1.375 V
WRITE_I2C:A1:01 // Sw1AB Sequence = 1
WRITE_I2C:A2:05 // Sw1AB Freq = 2MHZ, Mode = Single phase
WRITE_I2C:A8:2B // Sw1c Voltage = 1.375 V
WRITE_I2C:A9:02 // Sw1c Sequence = 2
WRITE_I2C:AA:01 // Sw1c Freq = 2 MHZ
WRITE_I2C:AC:72 // Sw2 Voltage = 3.30 V
WRITE_I2C:AD:05 // Sw2 Sequence = 5
WRITE_I2C:AE:01 // Sw2 Freq = 2 MHZ
//[Extended Page 1 Registers: 0xB0 - 0xBF] ----------------------------------
WRITE_I2C:B0:2C // Sw3A Voltage = 1.500 V

AN4536 Application Note Rev. 2.0 1/2014
4Freescale Semiconductor
OTP Overview
WRITE_I2C:B1:03 // Sw3A Sequence = 3
WRITE_I2C:B2:05 // Sw3A Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:B4:2C // Sw3B Voltage = 1.500 V
WRITE_I2C:B5:03 // Sw3B Sequence = 3
WRITE_I2C:B6:01 // Sw3B Freq = 2 MHZ
WRITE_I2C:B8:6F // Sw4 Voltage = 3.150 V
WRITE_I2C:B9:06 // Sw4 Sequence = 6
WRITE_I2C:BA:01 // Sw4 Freq = 2 MHZ
WRITE_I2C:BC:00 // Swbst Voltage = 5 V
WRITE_I2C:BD:0D // Swbst Sequence = 13
//[Extended Page 1 Registers: 0xC0 - 0xCF] ----------------------------------
WRITE_I2C:C0:06 // Vsnvs Voltage = 3 V
WRITE_I2C:C4:03 // Vsnvs Sequence = 3
WRITE_I2C:C8:0E // Vgen1 Voltage = 1.50 V
WRITE_I2C:C9:09 // Vgen1 Sequence = 9
WRITE_I2C:CC:0E // Vgen2 Voltage = 1.5 V
WRITE_I2C:CD:0A // Vgen2 Sequence = 10
//[Extended Page 1 Registers: 0xD0 - 0xDF] ----------------------------------
WRITE_I2C:D0:07 // Vgen3 Voltage = 2.5 V
WRITE_I2C:D1:0B // Vgen3 Sequence = 11
WRITE_I2C:D4:00 // Vgen4 Voltage = 1.8 V
WRITE_I2C:D5:07 // Vgen4 Sequence = 7
WRITE_I2C:D8:0A // Vgen5 Voltage = 2.8 V
WRITE_I2C:D9:0C // Vgen5 Sequence = 12
WRITE_I2C:DC:0F // Vgen6 Voltage = 3.3 V
WRITE_I2C:DD:08 // Vgen6 Sequence = 8
//[Extended Page 1 Registers: 0xE0 - 0xEF] ----------------------------------
WRITE_I2C:E0:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E1:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E2:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E8:00 // Power Good = Disabled
//[Extended Page 1 Registers: 0xF0 - 0xFF] ----------------------------------
WRITE_I2C:FF:08 // I2C Device Address = 0x08
//===========================================================================
// PROGRAMMING COMMANDS FOLLOW
//===========================================================================
WRITE_I2C:E4:02 // FUSE POR=1 (This Enables OTP Programming)
WRITE_I2C:E5:02 // FUSE POR=1 (This Enables OTP Programming)
WRITE_I2C:E6:02 // FUSE POR=1 (This Enables OTP Programming)
//---------------------------------------------------------------------------
WRITE_I2C:F0:1F // Enable ECC for fuse banks 1 to 5
WRITE_I2C:F1:1F // Enable ECC for fuse banks 6 to 10
WRITE_I2C:7F:02 // Access PF0100 EXT Page2

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 5
OTP Overview
WRITE_I2C:D0:1F // Set Auto ECC for fuse banks 1 to 5
WRITE_I2C:D1:1F // Set Auto ECC for fuse banks 6 to 10
//---------------------------------------------------------------------------
WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
VPGM:ON // Turn ON 9.5 V supply for PF0100A. Turn ON 9.0 V supply for PF0100.
// VPGM:ON turns on supply to the VDDOTP pin
DELAY:500 // Adds 500 msec delay to allow VPGM time to ramp up
//---------------------------------------------------------------------------
// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
//---------------------------------------------------------------------------
// BANK 1
//---------------------------------------------------------------------------
WRITE_I2C:F1:03 // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F1:0B // Set Bank 1 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F1:03 // Reset Bank 1 ANTIFUSE_EN
WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 2
//---------------------------------------------------------------------------
WRITE_I2C:F2:03 // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F2:0B // Set Bank 2 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F2:03 // Reset Bank 2 ANTIFUSE_EN
WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 3
//---------------------------------------------------------------------------
WRITE_I2C:F3:03 // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F3:0B // Set Bank 3 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F3:03 // Reset Bank 3 ANTIFUSE_EN
WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

AN4536 Application Note Rev. 2.0 1/2014
6Freescale Semiconductor
OTP Overview
//---------------------------------------------------------------------------
// BANK 4
//---------------------------------------------------------------------------
WRITE_I2C:F4:03 // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F4:0B // Set Bank 4 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F4:03 // Reset Bank 4 ANTIFUSE_EN
WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 5
//---------------------------------------------------------------------------
WRITE_I2C:F5:03 // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F5:0B // Set Bank 5 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F5:03 // Reset Bank 5 ANTIFUSE_EN
WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 6
//---------------------------------------------------------------------------
WRITE_I2C:F6:03 // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F6:0B // Set Bank 6 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F6:03 // Reset Bank 6 ANTIFUSE_EN
WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 7
//---------------------------------------------------------------------------
WRITE_I2C:F7:03 // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F7:0B // Set Bank 7 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F7:03 // Reset Bank 7 ANTIFUSE_EN
WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 8
//---------------------------------------------------------------------------
WRITE_I2C:F8:03 // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F8:0B // Set Bank 8 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F8:03 // Reset Bank 8 ANTIFUSE_EN
WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 9
//---------------------------------------------------------------------------

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 7
OTP Overview
WRITE_I2C:F9:03 // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F9:0B // Set Bank 9 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F9:03 // Reset Bank 9 ANTIFUSE_EN
WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
// BANK 10
//---------------------------------------------------------------------------
WRITE_I2C:FA:03 // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:FA:0B // Set Bank 10 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:FA:03 // Reset Bank 10 ANTIFUSE_EN
WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
//---------------------------------------------------------------------------
WRITE_I2C:D0:00 // Clear
WRITE_I2C:D1:00 // Clear
//---------------------------------------------------------------------------
VPGM:OFF // Turn off 8.5 V Boost Supply
DELAY:500 // Adds delay to allow VPGM to bleed off
PWRON:LOW // PWRON LOW to reload new OTP data
DELAY:500
PWRON:HIGH
After OTP programming is complete by following the above steps, read the registers 0xA0 to 0xE8 in Extended Page
1 and compare to the required register values as in the script. Additionally, read the ECC Interrupt bit, OTP_ECCI
in register 0x0E. If there is an error in the programmed values or if the OTP_ECCI bit is set to 1, reject the part as
the programming process resulted in errors.

AN4536 Application Note Rev. 2.0 1/2014
8Freescale Semiconductor
OTP Overview
2.3 Try-Before-Buy Mode Example
As shown in Table 1, it is possible to start the MMPF0100 directly from the TBBOTP registers without actually
programming the part. Shown below is an example of the Try-Before-Buy mode.
Note: All code examples in this document represent a script using the KITPFPGMEVME and the associated GUI.
Command syntax may vary if the user utilizes a different tool for communication.
///---------------------------------------------------------------------------
// F0 – Sample Try-Before-Buy Configuration
// Set VDDOTP = 0 V, PWRON = HIGH, LICELL = 3.0 V (Optional), VIN = VDDIO = 3.3 V
//---------------------------------------------------------------------------
WRITE_I2C:7F:01 // Access PF0100 EXT Page1
//[Extended Page 1 Registers: 0xA0 - 0xAF] ----------------------------------
WRITE_I2C:A0:2B // Sw1AB Voltage = 1.375 V
WRITE_I2C:A1:01 // Sw1AB Sequence = 1
WRITE_I2C:A2:05 // Sw1AB Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:A8:2B // Sw1c Voltage = 1.375 V
WRITE_I2C:A9:02 // Sw1c Sequence = 2
WRITE_I2C:AA:01 // Sw1c Freq = 2.0 MHZ
WRITE_I2C:AC:72 // Sw2 Voltage = 3.30 V
WRITE_I2C:AD:05 // Sw2 Sequence = 5
WRITE_I2C:AE:01 // Sw2 Freq = 2 MHZ
//[Extended Page 1 Registers: 0xB0 - 0xBF] ----------------------------------
WRITE_I2C:B0:2C // Sw3A Voltage = 1.500 V
WRITE_I2C:B1:03 // Sw3A Sequence = 3
WRITE_I2C:B2:05 // Sw3A Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:B4:2C // Sw3B Voltage = 1.500 V
WRITE_I2C:B5:03 // Sw3B Sequence = 3
WRITE_I2C:B6:01 // Sw3B Freq = 2 MHZ
WRITE_I2C:B8:6F // Sw4 Voltage = 3.150 V
WRITE_I2C:B9:06 // Sw4 Sequence = 6
WRITE_I2C:BA:01 // Sw4 Freq = 2 MHZ
WRITE_I2C:BC:00 // Swbst Voltage = 5.0 V
WRITE_I2C:BD:0D // Swbst Sequence = 13
//[Extended Page 1 Registers: 0xC0 - 0xCF] ----------------------------------
WRITE_I2C:C0:06 // Vsnvs Voltage = 3.0 V
WRITE_I2C:C4:03 // Vsnvs Sequence = 3
WRITE_I2C:C8:0E // Vgen1 Voltage = 1.50 V
WRITE_I2C:C9:09 // Vgen1 Sequence = 9
WRITE_I2C:CC:0E // Vgen2 Voltage = 1.5 V
WRITE_I2C:CD:0A // Vgen2 Sequence = 10
//[Extended Page 1 Registers: 0xD0 - 0xDF] ----------------------------------
WRITE_I2C:D0:07 // Vgen3 Voltage = 2.5 V
WRITE_I2C:D1:0B // Vgen3 Sequence = 11

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 9
OTP Overview
WRITE_I2C:D4:00 // Vgen4 Voltage = 1.8 V
WRITE_I2C:D5:07 // Vgen4 Sequence = 7
WRITE_I2C:D8:0A // Vgen5 Voltage = 2.8 V
WRITE_I2C:D9:0C // Vgen5 Sequence = 12
WRITE_I2C:DC:0F // Vgen6 Voltage = 3.3 V
WRITE_I2C:DD:08 // Vgen6 Sequence = 8
//[Extended Page 1 Registers: 0xE0 - 0xEF] ----------------------------------
WRITE_I2C:E0:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E1:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E2:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E8:00 // Power Good = Disabled
//[Extended Page 1 Registers: 0xF0 - 0xFF] ----------------------------------
WRITE_I2C:FF:08 // I2C Device Address = 0x08
//===========================================================================
// TRY-BEFORE-BUY COMMANDS FOLLOW
//===========================================================================
WRITE_I2C:E4:80 // TBB POR=1 (This Enables TBB Mode)
//---------------------------------------------------------------------------
// BANK 9
//---------------------------------------------------------------------------
PWRON:LOW // PWRON LOW
DELAY:500
PWRON:HIGH // PWRON HIGH to Start PMIC from desired TBB Configuration
Optionally, PWRON on can be kept HIGH and VIN can be toggled when a valid LICELL is present.

AN4536 Application Note Rev. 2.0 1/2014
10 Freescale Semiconductor
OTP Overview
2.4 OTP Registers Description
There are ten banks with a total of 260 fuses, where each bank contains 26 fuses. Each fuse represents one bit of
the TBBOTP register map. Table 2 toTable 11show thebanks, theirfuses andthe correspondingbitsinthe register
map.
Table 2. Bank 1
Fuses Register Name Register bits Description
5:0 OTP SW1AB VOLT SW1AB_VOLT[5:0] SW1AB power-up voltage
6– –RSVD
11:7 OTP SW1AB SEQ SW1AB_SEQ[4:0] SW1AB power-up sequence
13:12 OTP SW1AB CONFIG SW1AB_FREQ[1:0] SW1AB power-up frequency
15:14 OTP SW1AB CONFIG SW1AB_CONFIG[1:0] SW1A/B/C power-up configuration
18:16 OTP I2C ADDR I2C_SLV_ADDR[3:0] 3 LSBs of the slave address
19 OTP EN ECC0 EN_ECC_BANK1 Enable ECC for OTP fuse bank 1
25:20 – – ECC check bits for fuse bank 1
Table 3. Bank 2
Fuses Register Name Register bits Description
5:0 OTP SW1C VOLT SW1C_VOLT[5:0] SW1C power-up voltage
6– –RSVD
11:7 OTP SW1C SEQ SW1C_SEQ[4:0] SW1C power-up sequence
13:12 OTP SW1C CONFIG SW1C_FREQ[1:0] SW1C power-up frequency
15:14 OTP SWBST VOLT SWBST[1:0] SWBST power-up voltage
18:16 – – RSVD
19 OTP EN ECC0 EN_ECC_BANK2 Enable ECC for OTP fuse bank 2
25:20 – – ECC check bits for fuse bank 2
Table 4. Bank 3
Fuses Register Name Register bits Description
6:0 OTP SW2 VOLT SW2_VOLT6:0] SW2 power-up voltage
11:7 OTP SW2 SEQ SW2_SEQ[4:0] SW2 power-up sequence
13:12 OTP SW2 CONFIG SW2_FREQ[1:0] SW2 power-up frequency
18:14 OTP SWBST SEQ SWBST_SEQ[4:0] SWBST power-up sequence
19 OTP EN ECC0 EN_ECC_BANK3 Enable ECC for OTP fuse bank 3
25:20 – – ECC check bits for fuse bank 3

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 11
OTP Overview
Table 5. Bank 4
Fuses Register Name Register bits Description
6:0 OTP SW3A VOLT SW3A_VOLT[6:0] SW3A power-up voltage
11:7 OTP SW3A SEQ SW3A_SEQ[4:0] SW3A power-up sequence
13:12 OTP SW3A CONFIG SW3A_FREQ[1:0] SW3A power-up frequency
15:14 OTP SW3A CONFIG SW3_CONFIG SW3A/B power-up configuration
18:16 – – RSVD
19 OTP EN ECC0 EN_ECC_BANK4 Enable ECC for OTP fuse bank 4
25:20 – – ECC check bits for fuse bank 4
Table 6. Bank 5
Fuses Register Name Register bits Description
6:0 OTP SW3B VOLT SW3B_VOLT[6:0] SW3B power-up voltage
11:7 OTP SW3B SEQ SW3B_SEQ[4:0] SW3B power-up sequence
13:12 OTP SW3B CONFIG SW3B_FREQ[1:0] SW3B power-up frequency
18:14 OTP VREFDDR SEQ VREFDDR_SEQ[4:0] VREFDDR power-up sequence
19 OTP EN ECC0 EN_ECC_BANK5 Enable ECC for OTP fuse bank 5
25:20 – – ECC check bits for fuse bank 5
Table 7. Bank 6
Fuses Register Name Register bits Description
6:0 OTP SW 4 VOLT SW4_VOLT[6:0] SW4 power-up voltage
11:7 OTP SW 4 SEQ SW4_SEQ[4:0] SW4 power-up sequence
13:12 OTP SW 4 CONFIG SW4_FREQ[1:0] SW4 power-up frequency
14 OTP SW 4 CONFIG VTT SW4 tracking mode select
17:15 OTP VSNVS VOLT VSNVS_VOLT[2:0] VSNVS power-up voltage
18 – – RSVD
19 OTP EN ECC1 EN_ECC_BANK6 Enable ECC for OTP fuse bank 6
25:20 – – ECC check bits for fuse bank 6
Table 8. Bank 7
Fuses Register Name Register bits Description
3:0 OTP VGEN1 VOLT VGEN1_VOLT[3:0] VGEN1 power-up voltage
8:4 OTP VGEN1 SEQ VGEN1_SEQ[4:0] VGEN1 power-up sequence
12:9 OTP VGEN2 VOLT VGEN2_VOLT[3:0] VGEN2 power-up voltage
17:13 OTP VGEN2 SEQ VGEN2_SEQ[4:0] VGEN2 power-up sequence
18 – – RSVD
19 OTP EN ECC1 EN_ECC_BANK 7 Enable ECC for OTP fuse bank 7
25:20 – – ECC check bits for fuse bank 7

AN4536 Application Note Rev. 2.0 1/2014
12 Freescale Semiconductor
OTP Overview
Table 9. Bank 8
Fuses Register Name Register bits Description
3:0 OTP VGEN3 VOLT VGEN3_VOLT[3:0] VGEN3 power-up voltage
8:4 OTP VGEN3 SEQ VGEN3_SEQ[4:0] VGEN3 power-up sequence
12:9 OTP VGEN4 VOLT VGEN4_VOLT[3:0] VGEN4 power-up voltage
17:13 OTP VGEN4 SEQ VGEN4_SEQ[4:0] VGEN4 power-up sequence
18 – – RSVD
19 OTP EN ECC1 EN_ECC_BANK 8 Enable ECC for OTP fuse bank 8
25:20 – – ECC check bits for fuse bank 8
Table 10. Bank 9
Fuses Register Name Register bits Description
3:0 OTP VGEN5 VOLT VGEN5_VOLT[3:0] VGEN5 power-up voltage
8:4 OTP VGEN5 SEQ VGEN5_SEQ[4:0] VGEN5 power-up sequence
12:9 OTP VGEN6 VOLT VGEN6_VOLT[3:0] VGEN6 power-up voltage
17:13 OTP VGEN6 SEQ VGEN6_SEQ[4:0] VGEN6 power-up sequence
18 OTP PWRGD_EN PWRGD_EN Enable different functionality for
RESETBMCU
19 OTP EN ECC1 EN_ECC_BANK9 Enable ECC for OTP fuse bank 9
25:20 – – ECC check bits for fuse bank 9

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 13
OTP Overview
The TBBOTP registers store data for programming the fuses.These registers are written toand read from using the
I2C interface.
Once the TBBOTP registers are loaded with the correct values, the fuses can then be programmed. Before
discussing the programming process, some salient features of the OTP function are described.
Table 11. Bank 10
Fuses Register Name Register bits Description
1:0 OTP PU CONFIG1 SEQ_CLK_SPEED1[1:0] Power-up sequence delay, bits are XORed
3:2 OTP PU CONFIG1 SWDVS_CLK1[1:0] Power-up slew rate for all switching
regulators, bits are XORed
4 OTP PU CONFIG1 PWRON_CFG1 Power button configuration, bits is XORed
5 OTP FUSE POR1 FUSE_POR1 Loads fuse values to TBBOTP registers, bit
is XORed
7:6 OTP PU CONFIG2 SEQ_CLK_SPEED2[1:0] Power-up sequence delay, bits are XORed
9:8 OTP PU CONFIG2 SWDVS_CLK2[1:0] Power-up slew rate for all switching
regulators, bits are XORed
10 OTP PU CONFIG2 PWRON_CFG2 Power button configuration, bits is XORed
11 OTP FUSE POR2 FUSE_POR2 Loads fuse values to TBBOTP registers, bit
is XORed
13:12 OTP PU CONFIG3 SEQ_CLK_SPEED3[1:0] Power-up sequence delay, bits are XORed
15:14 OTP PU CONFIG3 SWDVS_CLK3[1:0] Power-up slew rate for all switching
regulators, bits are XORed
16 OTP PU CONFIG3 PWRON_CFG3 Power button configuration, bits is XORed
17 OTP FUSE POR3 FUSE_POR3 Loads fuse values to TBBOTP registers, bit
is XORed
18 OTP DONE OTP_DONE Prevents any further programming to fuses
and further writes to TBBOTP registers
19 OTP EN ECC1 EN ECC BANK10 Enable ECC for OTP fuse bank 10
25:20 – – ECC check bits for fuse bank 10

AN4536 Application Note Rev. 2.0 1/2014
14 Freescale Semiconductor
OTP Overview
2.4.1 TBBOTP Registers Description
The TBBOTP registers for configuring the switching regulators are listed in Table 12 and Table 13 to Table 18
provide a general description of the TBBOTP registers for all the switching regulators.
Table 12. OTP Switching Regulators Register Summary
Register Address Output
OTP SW1AB VOLT 0xA0 SW1AB OTP Output voltage set point
OTP SW1AB SEQ 0xA1 SW1AB OTP power-up sequence selection
OTP SW1AB CONFIG 0xA2 SW1AB OTP operation mode and frequency selection
OTP SW1C VOLT 0xA8 SW1C OTP Output voltage set point
OTP SW1C SEQ 0xA9 SW1C OTP power-up sequence selection
OTP SW1C CONFIG 0xAA SW1C OTP frequency selection
OTP SW2 VOLT 0xAC SW2 OTP Output voltage set point
OTP SW2 SEQ 0xAD SW2 OTP power-up sequence selection
OTP SW2 CONFIG 0xAE SW2 OTP frequency selection
OTP SW3AVOLT 0xB0 SW3A OTP Output voltage set point
OTP SW3A SEQ 0xB1 SW3A OTP power-up sequence selection
OTP SW3A CONFIG 0xB2 SW3A OTP operation mode and frequency selection
OTP SW3B VOLT 0xB4 SW3B OTP Output voltage set point
OTP SW3B SEQ 0xB5 SW3B OTP power-up sequence selection
OTP SW3B CONFIG 0xB6 SW3B OTP frequency selection
OTP SW4 VOLT 0xB8 SW4 OTP output voltage set point
OTP SW4 SEQ 0xB9 SW4 OTP power-up sequence selection
OTP SW4 CONFIG 0xBA SW4 OTP frequency and VTT mode selection
OTP SWBST VOLT 0xBC SWBST OTP output voltage set point
OTP SWBST SEQ 0xBD SWBST OTP power-up sequence selection
Table 13. OTP SW1x VOLT Register Description (SW1A/B and SW1C)
Name Bit # Description
SW1x_VOLT 5:0 Sets the SW1x output voltage to be programmed on the OTP
fusesand loaded during power-up.Refer toSW1A/B/Coutput
voltage configuration table on Data Sheet for all possible
configurations.
UNUSED 7:6 UNUSED
Table 14. OTP SWx VOLT Register Description (SW2 - SW4)
Name Bit # Description
SWx_VOLT 6:0 Sets the SWx output voltage to be programmed on the OTP
fuses and loaded during power-up. Refer to the respective
SWx output voltage configuration table on datasheet for all
possible configurations.
UNUSED 7 UNUSED
Table 15. OTP SWx SEQ Register Description
Name Bit # Description
SWx_SEQ 4:0 Assign the power-up sequence slot 0-31 for SWx
UNUSED 7:5 UNUSED

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 15
OTP Overview
Table 16. OTP SWx CONFIG Register Description
Name Bit # Description
SWx_FREQ 1:0 SWx OTP Frequency configuration
00 = 1.0 MHz
01 = 2.0 MHz
10 = 4.0 MHz
11 = Reserved
SWx_CONFIG 3:2 SWx configuration(3)
SW1A/B
00 = A/B/C Single Phase
01 = A/B Single Phase - C
Independent
10 = A/B Dual Phase - C
Independent
11 = Reserved
SW3A
00 = A/B Single Phase
01 = A/B Single Phase
10 = A/B Dual Phase
11 = A/B Independent
mode
VTT 4 Enable SW4 in VTT mode (4)
UNUSED 7:5 UNUSED
Notes
3. Only on OTP SW1AB CONFIG and OTP SW3A CONFIG registers. UNUSED on all other OTP SWx
CONFIG registers.
4. Only on OTP SW4 CONFIG register. UNUSED on all other OTP SWx CONFIG registers.
Table 17. OTP SWBST VOLT Register Description
Name Bit # Description
SWBST_VOLT 1:0 SWBST OTP output voltage setpoint
00 = 5.00 V
01 = 5.05 V
10 = 5.10 V
11 = 5.15 V
UNUSED 7:2 UNUSED
Table 18. OTP SWBST SEQ Register Description
Name Bit # Description
SWBST_SEQ 4:0 Assign the power-up sequence slot 0-31 for SWBST
UNUSED 7:5 UNUSED

AN4536 Application Note Rev. 2.0 1/2014
16 Freescale Semiconductor
OTP Overview
Table 19 shows a summary of all the registers related to the linear regulators, and Table 20 to Table 22 provide a
general bit description of the linear regulator OTP registers.
Table 19. OTP Linear Regulators Register Summary
Register Address Output
OTP VSNVS VOLT 0xC0 VSNVS OTP Output voltage set point
OTP VREFDDR SEQ 0xC4 VREFDDR OTP power-up sequence selection
OTP VGEN1 VOLT 0xC8 VGEN1 OTP Output voltage set point
OTP VGEN1 SEQ 0xC9 VGEN1 OTP power-up sequence selection
OTP VGEN2 VOLT 0xCC VGEN2 OTP Output voltage set point
OTP VGEN2 SEQ 0xCD VGEN2 OTP power-up sequence selection
OTP VGEN3 VOLT 0xD0 VGEN3 OTP Output voltage set point
OTP VGEN3 SEQ 0xD1 VGEN3 OTP power-up sequence selection
OTP VGEN4 VOLT 0xD4 VGEN4 OTP Output voltage set point
OTP VGEN4 SEQ 0xD5 VGEN4 OTP power-up sequence selection
OTP VGEN5 VOLT 0xD8 VGEN5 OTP output voltage set point
OTP VGEN5 SEQ 0xD9 VGEN5 OTP power-up sequence selection
OTP VGEN6 VOLT 0xDC VGEN6 OTP output voltage set point
OTP VGEN6 SEQ 0xDD VGEN6 OTP power-up sequence selection
Table 20. OTP VSNVS VOLT Register Description
Name Bit # Description
VSNVS_VOLT 2:0 Sets the VSNVS output voltage to be programmed on the
OTP fuses and loaded during power-up
000 = 1.0 V
001 = 1.1 V
010 = 1.2 V
011 = 1.3 V
100 = 1.5 V
101 = 1.8 V
110 = 3.0 V
111 = RSVD
UNUSED 7:3 UNUSED
Table 21. OTP VGENx VOLT Register Description
Name Bit # Description
VGENx_VOLT 3:0 Sets the VGENx output voltage to be programmed on the
OTP fuses and loaded during power-up. Refer to the VGENx
output voltage configuration table on Data Sheet for all
possible configurations.
UNUSED 7:4 UNUSED
Table 22. OTP xxxx SEQ Register Description
Name Bit # Description
xxxx_SEQ 4:0 Assign the power-up sequence slot 0-31 for the specific linear
regulator or VREFDDR voltage
UNUSED 7:5 UNUSED

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 17
OTP Overview
2.4.2 OTP Redundant Bits
Some functions are assigned redundant bits, which are XORed, to allow that function to be changed multiple times.
These are the functions that have redundant OTP fuse bits:
• Sequence Clock Frequency (Sequence delay)
• DVS Clock Frequency (Initial slew rate)
• Power button function
• Fuse POR
Table 23 shows the I2C registers in the Extended Page 1 dedicated to redundant bits for the four functions
mentioned. The XORed bits are read-only.
Table 23. OTP Redundant Bits Registers
Extended Pg 1 I2C Data Bits
Addr Reg Name 7 6 5 4 3 2 1 0
E0 OTP PU
CONFIG1 –––PWRON CFG1 SWDVS_CLK1[1:0] SEQ_CLK SPEED1[1:0]
0 0 0 x x x x x
E1 OTP PU
CONFIG2 –––PWRON CFg2 SWDVS_CLK2[1:0] SEQ_CLK SPEED2[1:0]
0 0 0 x x x x x
E2 OTP PU
CONFIG3 –––PWRON CFG3 SWDVS_CLK3[1:0] SEQ_CLK SPEED3[1:0]
0 0 0 x x x x x
E3 OTP PU
CONFIG XOR –––PWRON CFG_XOR SWDVS_CLK3_XOR SEQ_CLK_SPEED XOR
0 0 0 x x x x x
E4 OTP FUSE
POR1 TBB_POR SOFT_FUSE POR – – – – FUSE POR1 –
0 0 0 0 0 0 x 0
E5 OTP FUSE
POR1 RSVD RSVD – – – – FUSE POR2 –
0 0 0 0 0 0 x 0
E6 OTP FUSE
POR1 RSVD RSVD – – – – FUSE POR3 –
0 0 0 0 0 0 x 0
E7 OTP FUSE
POR XOR RSVD RSVD – – – – FUSE POR_XOR –
0 0 0 0 0 0 x 0

AN4536 Application Note Rev. 2.0 1/2014
18 Freescale Semiconductor
OTP Overview
Table 24. OTP PU CONFIGx Bits Definition
Bit Name Description
1:0 SEQ_CLK_SPEEDx[1:0] Sequence delay between steps, bits are XORed
00 = 500 μs
01 = 1000 μs
10 = 2000 μs
11 = 4000 μs
3: 2 SWDVS_CLKx[1:0] Start-up slew rate, bits are XOR'd
00 = 25 mV/2 μs
01 = 25 mV/4 μs
10 = 25 mV/8 μs
11 = 25 mV/16 μs
4PWRON_CFGx Set the power on button initial configuration
0 = Power button is level sensitive
1 = Power button is edge sensitive and turn-off is based on time held low
7:5 RSVD Reserved
Table 25. OTP_PU_CONFIG XOR Bits Definition
Bit Name Description
1:0 SEQ_CLK_SPEED_XOR Final result of the XOR function of the SEQ_CLK_SPEEDx[1:0] bits
3: 2 SWDVS_CLK_XOR Final result of the XOR function of the SWDVS_CLKx[1:0] bits
4 PWRON_CFG_XOR Final result of the XOR function of the SEQ_PWRON_CFGx bits
7:5 RSVD Reserved
Table 26. OTP_FUSE_PORx Bits Definition
Bit Name Description
0 RSVD Reserved
1 FUSE_PORx(5) Load fuse values to TBB_OTP registers
0 = No Fuse value loaded
1 = Programmed fuse values loaded to TBB_OTP registers
5:2 RSVD Reserved
6 SOFT_FUSE_POR(6) Software version of the FUSE_PORx bit
7:5 TBB_POR(6) Prototyping enable bit
0 = Prototyping disabled
1 = Prototyping enabled
5. In MMPF0100 FUSE_POR1, FUSE_POR2 and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The
FUSE_POR_XOR has to be 1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx
bits. In MMPF0100A, the XOR function is removed. It is required to set all of the FUSE_PORx bits to be able to load the
fuses.
6. Reserved on Addresses E5 and E6

AN4536 Application Note Rev. 2.0 1/2014
Freescale Semiconductor 19
OTP Overview
For example, if FUSE_POR1 is programmed to “1”, then fuse values are loaded as FUSE_POR_XOR is “1”. If
FUSE_POR2 is then programmed, FUSE_POR_XOR becomes “0” and fuses values cannot be loaded.
SOFT_FUSE_POR is a software version of the FUSE_PORx bits, i.e. it is XORed with the FUSE_PORx bits to
determine whether fuses can be loaded.
See Table 28 for the XOR truth table for the previous functions listed.
Note: The desired function of the redundant bits must be determined when ECC is configured and its bits
programmed, or the ECC logic attempts to correct thenewly programmed redundant bits. ECC is discussed inError
Correction Code (ECC).
2.4.3 OTP Register Reloading without Turn-on Event
After the fuses are programmed, their values may be loaded into the digital control logic without toggling VIN or
PWRON. To update the TBBOTP registers by reloading the fuse values automatically, set bits in the
OTP LOAD MASK register depending on the functionality required. Refer to Table 30 for a description of the
OTP LOAD MASK register.
Table 27. OTP FUSE POR XOR Bits Definition
Bit Name Description
0 RSVD Reserved
1 FUSE_POR_XOR Final result of the XOR function of the FUSE_PORx bits
7:2 RSVD Reserved
Table 28. Redundant Bit XOR Function Truth Table
Bit1 Bit2 Bit3 XOR bit
000 0
100 1
110 0
111 1
Table 29. OTP Load Mask Register
Extended Page 1 I2C Data Bits
Addr Reg Name 7 6 5 4 3 2 1 0
84 OTP LOAD MASK START RL PWRTN FORCE
PWRCTL RL PWRCTL RL OTP RL OTP ECC RL OTP FUSE RSVD
00 0 0 0 0 00

AN4536 Application Note Rev. 2.0 1/2014
20 Freescale Semiconductor
OTP Overview
Often only bits 1, 2, and 3 need to be set, as well as the START bit, to reload the TBBOTP registers after the fuses
are programmed. The TBBOTP register values could then be checked to make sure the correct values have been
loaded from the fuses. Setting bits 4 and 5, updates the regulator parameters immediately. This should be done with
caution if PWRON is already asserted. A PWRON event triggers a complete reload using the same logic. When a
'1' is written to Bit 7 of the OTP_LOAD_MASK registers, the MMPF0100 is turned off momentarily and then turned
back on to reload the fuses. If it is desired to reload the fuses without first turning off the MMPF0100, clear Bit 0 of
the PWRCTRL_OTP_CTRL register prior to writing to the OTP_LOAD_MASK register. Note that the
OTP_LOAD_MASK is register 0x84 in Extended Page 1 whereas the PWRCTRL_OTP_CTRL is register 0x88 in
Extended Page 2.
Table 30. OTP Reload Mask Register Bit Description
Bit Name Description
0RSVD Reserved
1 RL_OTP_FUSE Reload the OTP fuse latch from the analog fuse bit
0 = Disable loading
1 = Enable loading
2 RL_OTP_ECC Reload the OTP ECC registers. Set this bit irrespective of whether ECC is
enabled or disabled.
0 = Disable loading
1 = Enable loading
3 RL_OTP Reload the TBBOTP registers from the fuses
0 = Disable loading
1 = Enable loading of fuses if ECC is disabled. Enable loading of ECC corrected
fuses if ECC is enabled.
4 RL_PWRCTL Reload the power control registers from the TBBOTP registers
0 = Disable loading
1 = Enable loading
5 FORCE_PWRCTL Forces the power control registers to be reloaded if they are being used to control
the regulators
0 = No reload forced
1 = Power control register value affects regulators when the reload sequence is
enabled and RL PWRCTL bit is enabled.This is needed when changing output
voltage of switching regulators from low-voltage range to high-voltage range
6 RL_PWRTN Reloads the register that controls how the PWRON button works
0 = PWRON configuration setting does not change until a shutdown and restart
event
1 = PWRON behavior switch to new OTP PWRON button configuration when
START bit is enabled
7 START Reload sequence start bit
0 = Reload sequence disabled
1 = Starts the reload sequence, when the sequence is done all of the
OTP_LOAD_MASK bits are reset