NXP Semiconductors QorIQ T1040 User manual

QorIQ T1040 Reference Design Board
User Guide
Document Number: T1040RDBPAUG
Rev. 0, 06/2015

QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
2 Freescale Semiconductor, Inc.

Contents
Section number Title Page
Chapter 1
Overview
1.1 Related documentation....................................................................................................................................................7
1.2 Acronyms and abbreviations...........................................................................................................................................7
1.3 Silicon features................................................................................................................................................................8
1.4 Board features................................................................................................................................................................. 9
1.5 Block diagram.................................................................................................................................................................10
Chapter 2
Architecture
2.1 Processor.........................................................................................................................................................................13
2.2 Power.............................................................................................................................................................................. 13
2.3 Clocks............................................................................................................................................................................. 15
2.4 Reset................................................................................................................................................................................18
2.5 DDR................................................................................................................................................................................18
2.6 SerDes port......................................................................................................................................................................20
2.6.1 PCIe support.......................................................................................................................................................21
2.6.2 SGMII support................................................................................................................................................... 22
2.6.3 QSGMII support................................................................................................................................................ 22
2.6.4 SATA support.................................................................................................................................................... 23
2.7 Ethernet controllers.........................................................................................................................................................23
2.8 Ethernet management interface.......................................................................................................................................24
2.9 I2C...................................................................................................................................................................................25
2.10 SPI interface....................................................................................................................................................................26
2.11 Local bus.........................................................................................................................................................................27
2.12 SDHC interface...............................................................................................................................................................28
2.13 USB interface..................................................................................................................................................................29
2.14 Serial port........................................................................................................................................................................30
2.15 SLIC/SLAC and TDM interface.....................................................................................................................................32
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Section number Title Page
2.16 JTAG/COP port.............................................................................................................................................................. 33
2.17 Connectors, headers, jumper, push buttons and LED.....................................................................................................34
2.17.1 Connectors......................................................................................................................................................... 35
2.17.2 Headers...............................................................................................................................................................36
2.17.3 Jumper................................................................................................................................................................36
2.17.4 Push buttons....................................................................................................................................................... 37
2.17.5 LEDs.................................................................................................................................................................. 37
2.18 Temperature.................................................................................................................................................................... 37
2.19 DIP switch definition......................................................................................................................................................38
Chapter 3
CPLD specification
3.1 CPLD programming........................................................................................................................................................41
3.2 CPLD memory map........................................................................................................................................................44
3.2.1 Chip ID1 register (CHIPID1).............................................................................................................................44
3.2.2 Chip ID2 register (CHIPID2).............................................................................................................................45
3.2.3 Hardware version register (HWVER)................................................................................................................45
3.2.4 Software version register (SWVER)..................................................................................................................46
3.2.5 Reset control register (RSTCON1)....................................................................................................................46
3.2.6 Reset control register (RSTCON2)....................................................................................................................47
3.2.7 INTSR................................................................................................................................................................ 48
3.2.8 Flash control and status register (FLHCSR)......................................................................................................49
3.2.9 Fan control and status register (FANCSR)........................................................................................................ 49
3.2.10 Panel LED control and status register (LEDCSR).............................................................................................50
3.2.11 SFP+ control and status register (SFPCSR).......................................................................................................51
3.2.12 Miscellaneous control and status register (MISCCSR)..................................................................................... 51
3.2.13 Boot configuration override register (BOOTOR)..............................................................................................52
3.2.14 Boot configuration register 1 (BOOTCFG1).....................................................................................................52
3.2.15 Boot configuration register 2 (BOOTCFG2).....................................................................................................52
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Section number Title Page
Chapter 4
Software configuration
4.1 Preparing board...............................................................................................................................................................55
4.2 Ethernet port map............................................................................................................................................................57
4.3 NOR flash image layout..................................................................................................................................................57
4.4 Switch settings................................................................................................................................................................ 58
4.4.1 Switch default settings (NOR flash boot).......................................................................................................... 58
4.4.2 Other boot source settings..................................................................................................................................59
4.4.3 Switch detailed description................................................................................................................................ 59
4.5 SDK Build details........................................................................................................................................................... 60
4.6 Flashing and updating images.........................................................................................................................................60
4.6.1 Flashing images on and booting from NOR flash..............................................................................................60
4.6.2 Flashing eSPI boot images.................................................................................................................................61
4.6.3 Flashing NAND boot images.............................................................................................................................62
4.6.4 Flashing SD card boot images........................................................................................................................... 63
4.6.5 Booting Linux.................................................................................................................................................... 63
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6 Freescale Semiconductor, Inc.

Chapter 1
Overview
This manual describes the features and operation of a high performance reference
platform that supports QorIQ Power Architecture® processors including:
• T1040
• T1020
The T1040RDB is optimized to support high-bandwidth DDR3L memory and a full
complement of high-speed SerDes ports.
NOTE
The dual-core version of the T1040 SoC is known as T1020.
1.1 Related documentation
The documents below may be available only under a non-disclosure agreement (NDA).
To request access to these documents, contact your local field applications engineer or
sales representative.
Table 1-1. Related documentation
Document name Description
QorIQ T1040, T1020 Data Sheet
(T1040, T1020)
Provides specific data regarding bus timing, signal behavior, and AC, DC, and thermal
characteristics, as well as other design considerations
QorIQ T1040 Reference Manual
(T1040RM)
This document provides a detailed description on the QorIQ T1040 multicore processor,
and its features, such as memory map, serial interfaces, power supply, chip features,
and clock information.
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1.2 Acronyms and abbreviations
The following table contains acronyms and abbreviations used in this document.
Table 1-2. Acronyms and abbreviations
Term Description
COP Common On-chip Processor
CPC CoreNet Platform Cache
CPLD Complex Programmable Logic Device
DIMM Dual in-line memory module
DIP Dual in-line package
DMA Direct Memory Access
DPAA Data Path Acceleration Architecture
DRAM Dynamic random-access memory
DUT Device under test
ECC Error detection and correction
EMI Ethernet Management interface
eSDHC Enhanced Secure Digital Host Controller
eSPI Enhanced Serial Peripheral Interface
FXS Foreign Exchange Station
FXO Foreign Exchange Office
I2C Inter - Integrated Circuit
IFC Integrated Flash Controller
JTAG Joint Test Action Group
MDC Management Data Clock
MDIO Management Data Input/Output
PCIe PCI Express
POR Power-on reset
PSU Power Supply Unit
QMan Queue Manager
SATA Serial Advanced Technology Attachment
SD Secure Digital
SerDes Serializer/Deserializer
SGMII Serial Gigabit Media Independent Interface
SPI Serial Peripheral Interface
SYSCLK System Clock
UART Universal asynchronous receiver/transmitter
VCC Voltage for circuit
VTT Voltage for terminal
Silicon features
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1.3 Silicon features
NOTE
For a description of the features of the T1040 SoC, see QorIQ
T1040 Reference Manual (T1040RM).
1.4 Board features
The features of the T1040RDB-PA board are as follows:
•Eight lanes of SerDes connections with support for:
• PCIe that supports Gen 1 and Gen 2
• SGMII
• QSGMII
• SATA 2.0
• DDR controller
• Supports data rates up to 1600 MHz
• Supports one DDR3L DIMM of single-, dual-, or quad-rank type
• DDR power supply (1.35 V) with automatic tracking of VTT
• IFC
• NAND flash: 8-bit, async, 1 GB
• NOR: 16-bit, non-multiplexed, 128 MB, support of eight virtual banks
• Ethernet
• Two onboard RGMII 10/100/1G Ethernet ports, PHY #0 remains powered up
during deep-sleep
• One onboard SGMII 10/100/1G Ethernet Port
• Two onboard QSGMII 10/100/1G PHYs connecting to 8 GE ports
• CPLD
• Manages system power and reset sequencing
• Manages DUT, board, clock configuration
• Reset and interrupt monitor and control
• General fault monitoring and logging
• Sleep mode control
• Clocks
• SYSCLK at 100 MHz
• DDRCLK at 66.66 MHz
• USBCLK at 24 MHz
• Single Oscillator Source reference clocking at 100 MHz
• Power Supplies
Chapter 1 Overview
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• Dedicated PMBus regulator for core power adjustable from 0.7 V to 1.3 V at 35
A
• USB
• Supports two USB 2.0 ports with integrated PHYs. Two type A ports with 5
[email protected] A per port
• SDHC port that connects directly to card slot
• SPI
• One onboard 64 MB SPI flash
• Onboard support of SPI EEPROM, TDM SLAC control, and TDM riser card
control
• TDM interface through optional riser card, also support FXS/FXO on board
• I2C bus
• Devices connected: EEPROM, thermal monitor, VCore power controller
• Other IO
• Two serial ports
1.5 Block diagram
This section provides a high-level overview of the T1040 SoC and the T1040RDB board.
The figures below show the major functional units within the T1040 device and the
T1040RDB board.
(Peripheral access
management unit)
CoreNet™ Coherency Manager
Security monitor
Power management
SD/eSDHC/eMMC
2x DUART
16b IFC
eSPI, 4x GPIO
32/64-bit
DDR3L/4
memory controller
Real-time
debug
Watchpoint
cross
trigger
Perf
Monitor
2 x USB2.0 w/PHY
4x I2C
Power Architecture®
e5500
32 KB
D-Cache
32 KB
I-Cache
256 KB
backside
L2 cache 256 KB
platform cache
Security fuse processor
DIU
Security
5.4
(XoR,
CRC)
Pattern
match
engine
2.2
Queue
Manager
Buffer
Manager
1G 1G 1G
Parse, classify,
distribute
8-port
switch
1G 1G 1G 1G
1G 1G 1G 1G
2x DMA
PCl Express 2.0 PCI Express 2.0 PCI Express 2.0 PCI Express 2.0
SATA 2.0
SATA 2.0
TDM/HDLC
TDM/HDLC
QUICC
Engine
Trace
8-lane, 5 GHz SerDes
PAMU
Frame Manager
1G
Aurora
Figure 1-1. T1040 SoC block diagram
Block diagram
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Clocks, POR, reset and
power supply circuit
JTAG
USB Type A x2
USB Conn *2
DDR3L 72bit
I2C_1
MT18KSF71272HZ-1G6 (4GB)
1.6G,DDR3L/72bit 4GB
(UDIMM)
Address:0x4c
Address:0x50
EEPROM(AT24C256)
Temp sensor (ADT7461)
CPLD
(EPM240G)
RESET
Interrupt
Power on conf
Other control
Local bus (16bit)
Local bus (8bit)
SPI bus
NOR FLASH
S29GL01GP11TFIV10
(128MB)
PCIe x1
SATA (T1040 only)
SDXC Card
T1/E1
QUICC Engine connector for
PMC plug-in card
QUICC Engine
Interface
SATA
RJ45
TXD,RXD,RTS,CTS
RGMII
SGMII T1040
IFC
SPISATA
QE
TDM DUART RGMII USB2.0 COP
DDR3
I2C
Mini PCle
PClex1
QSGMII
QSGMII
F104S8A
(QGMII->Copper)
Magnetic
X4
Magnetic
X4
RJ45
X4
RJ45
X4
Magnetic
(GSTS009LF)
RTL8211DN
(SGMII>Copper)
2Pin-Conn FXO
Relay
FXS1
Le88266DLC
MAX3232
SerDes
RJ45
RJ45
RJ45
RJ45
RJ11
RJ11
RJ11
RJ11
FXS2
FXS3
FXS4
TXD,RXD,RTS,CTS
Le88266DLC
MAX3232
RGMII
F104S8A
(QGMII->Copper)
Magnetic
(GSTS009LF)
Magnetic
(GSTS009LF)
RTL8211E-VB
(RGMII->Copper)
RTL8211E-VB
(RGMII->Copper)
SDXC PCle
NAND FLASH
MT29F8G08ABABAWP.121T
(1GB)
SPI FLASH
N25Q512A13GSF40F
(64MB)
Mini PCle
PCIe x1
PCIe x1
Figure 1-2. T1040RDB board block diagram
Chapter 1 Overview
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Block diagram
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Chapter 2
Architecture
This section explains:
•Processor
•Power
•Clocks
•Reset
•DDR
•SerDes port
•Ethernet controllers
•Ethernet management interface
•I2C
•SPI interface
•Local bus
•SDHC interface
•USB interface
•Serial port
•SLIC/SLAC and TDM interface
•JTAG/COP port
•Connectors, headers, jumper, push buttons and LED
•Temperature
•DIP switch definition
2.1 Processor
The T1040RDB supports as many features of the T1040 as possible, as detailed in the
following sections. The T1040RDB supports this by isolating OVDD-powered signals
through external translation devices or the CPLD wherever required.
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2.2 Power
The power supply system of the T1040RDB board uses power from a standard ATX
power supply unit (PSU) to provide the required power supplies to the processor, CPLD,
and peripheral devices. In addition to meeting required power specifications, the
following goals guide the power supply architecture:
• Monolithic power supply for VCC that powers internal cores and platform logic
• T1040RDB can access IR36021 via software to check the current and voltage values
or to program the voltage changes
• All power supplies are sequenced per hardware specifications
The figure below shows an overview of the power supply.
Power
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BEAD
ATX PS
12V_SLP
5V0_SLP
VCORE_EN
VCORE_PGOOD
CPLD
PM_BUS
VPG
Regulator
IR36021/
3550
3V3_SLP VCC_DRV_3.3V
VCC_DRV_7V
12V_SLP MIC30102
YM
SVO_SLP
IOPWR_EN 1V0 (4A)
1V5 (1.5A)
IR3473
1V35
1V8
2V5
3V3
VTT/MVREF
1V0S
DVDD
MIC47100
TPS51200
1V35_SLP
1V8_SLP
VDD_EN
2V5
EVDD_SEL
For T1040,DVDD=3.3V
3V3
EVDD
3V3
1V8
T2081_EN
12V_SLP
OPWR_EN
3V3
12V
1V0_LP
NCP571
12V BATH/BATL
DC/DC 3V3
OVDD_SLP
3V3_SLP
1V8_SLP
EPM570
VDD PCA9546
BATH/BATL
3V3
5V0_SLP USB:MIC2506
DVDD/AVDD
Le88266*2
SD Card
IN
VDD
3V3
SPI FLASH
N25QS12A13G
VCC
3V3
3V3
NAND FLASH
MT29F8G08ABBAWP
VCC/VCOD
VIO
OVDD
3V3 VCC
NOR FLASH
JS28F00AM29EWHA
2V5 VDD25/VDD25A
VSC8514*2
VDD1/VDD1A
1V0
OVDD_SLP
VCCRE J11
IDT9FGV0641
ICS843002*2
3V3
1V8_SLP
OVDD
OVDD_SLP 100M OSC
Sys_refclk
66.67M OSC
DDR_refclk
VCORE_SLP_40A VCORE
VDD_EN
VCORE_EN
CPLD 1V35
OVDD_SLP
0.33ohm
OVDD
VCORE_SLP
3V3_SLP
OVDD_SLP
1V05
1V35
1V8_SLP
3V3_SLP
1V8
3V3 0ohm[NC]
MVREF
1V0_LP
OVDD
OVDD
OVDD_SLP
0ohm[NC]
0ohm
BEAD XVDD
AVDD_SD1_PLL1
AVDD_SD1_PLL2
AVDD_PLAT
AVDD_D1
AVDD_CGA1
AVDD_CGA2
USB_SVDD[1:2]
USB_HVDD[1:2]
USB_OVDD[1:2]
S1VDD[1:7]
X1VDD[1:5]
T1040
O1VDD[1:3]
OVDD[1:8]
D1_MVREF
VDD_IP
TH_VDD
FA_VL
PROG_MTR
PROG_SFP
EVDD1
DVDD[1:3]
CVDD1
LVDD[1:2]
L1VDD[1:2]
G1VDD[1:19]
VDD[1:47]
VDDC[1:7]
PIPCIE3212*5
VDD
3V3
3V3
3V3_SLP
VDD MAX3232*2
AVDD/DVDO
RTL8211E-VB
U49
DVDD(15/21)
2V5_SLP
3V3 AVDD/DVDD
RTL8211E-VB/DN
U46/U52
DVDD(15/21)
2V5
3V3
12V
3V3
12V
TDM SLOT
PCIEX4 SLOT
1V5
3V3 MINI PCIE SLOT*2
12V FAN Conn *4
SVO_SLP
IOPWR_EN IR3473
IR3473
SVO_SLP
IR3473
SVO_SLP
IR3473
SVO_SLP
IR3473
SVO_SLP
OPWR_EN
(Always_On)
3V3_SLP(9A)
OPWR_EN
(Always_On)
2V5_SLP(1.5A)
ODRPWR_EN
(Always_On)
1V35_SLP(6.5A)
(Switchable)
(Switchable)
VDD_EN
IOPWR_EN
DDRPWR_EN
EVDD_SEL
T2081_EN
OPWR_EN
(Always_On)
1V8_SLP(2A)
SVDD
0ohm
BEAD
BEAD
BEAD
0.33ohm
5.1ohm
5.1ohm
5.1ohm
5.1ohm
J10
J9
EVDD
DVDD
OVDD
2V5
2V5_SLP
1V5_SLP
VCORE
VCORE_SLP
Figure 2-1. Power distribution
2.3 Clocks
The clock circuitry provides clocks for the processor for:
•SYSCLK (single-ended and differential)
• DDRCLK
• SerDes clocks (two independent options)
Chapter 2 Architecture
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• Ethernet clocks
• USB clock
The architecture of the clock section is shown in the figure below.
Clocks
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P
E
X
S
L
O
T
M
I
N
I
P
E
X
S
L
O
T
M
I
N
I
P
E
X
S
L
O
T
25MHz
ICS843002
(ONLY FOR T1040)
125MHz
ICS843002
25MHz
OSC-100MHz
OSC-66.66MHz
OSC-24MHz
IDT9FGV0641
DIFSYSCLK_OE
PEXCLK_OE
25MHz
MPEX2_REFCLK_P/N(100M)
T1040
DDRCLK (66.66MHz)
USB_REFCLK (24MHz)
SYSCLK (100MHz)
SD_REFCLK1_P/N
(125MHz)
QSG2_REFCLK_P/N
(125MHz)
QSG1_REFCLK_P/N
(125MHz)
F104S8A
F104S8A
MPEX1_REFCLK_P/N(100M)
PEX_REFCLK_P/N(100M)
SD_REFCLK2_P/N(100M)
SYS_REFCLK_P/N(100M)
Figure 2-2. Clock distribution
Chapter 2 Architecture
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2.4 Reset
The CPLD manages the reset signals to and from the T1040 processor and the other
devices on the T1040RDB board. The figure below shows an overview of the reset
architecture.
ATX PS PWR_GODD
GND Push-Button
MAX811S
(Power-on RST)
PON_RST_N
COP_SRST_N
COP_ITF
T1040
HESET_REQ_N
HRSET_N
PORESET_N
Reset
source
select
RST_CTL
DDR_RSTN
TDMR_RST TDMR
SLOT
QSG2_RST_N QSGMII
GE PHY
QSG1_RST_N
EC1_RST_N RGMII
GE PHY1
Soft reset register
RSTCON1 & RSTCON2
SW_RST
7
CPLD
COP_HRST_N
6543210
EC2_RST_N RGMII
GE PHY2
DDR3/
DDR3L
CORE_power
(IR36021)
VCORE_PGD
NOR
FLASH
PEX SLOT
MINI PEX
SLOT
MINI PEX
SLOT
SGMII
GE PHY
QSGMII
GE PHY
MPEX2_RST
PEX_RST
MPEX1_RST
NOR_RSTN
SG_RST_N
Figure 2-3. CPLD logical
2.5 DDR
The T1040RDB supports high-speed DRAM with an unbuffered DDR3L (240pin) socket
(UDIMM), featuring single-, dual-, and quad-rank support. The memory interface
includes all the necessary termination and I/O power, and is routed so as to achieve
maximum performance of the memory bus, as shown in the below figure.
Reset
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IV35_SLP
DDR_DQ[0:63]
DDR_ECC[0:7]
DDR_MA[0:15]
DDR_MDQS[0:8]
DDR_MDM[0:8]
DDR_MBA[0:2]
DDR_MDOT[0:1],DDR_MAPAR_OUT,DDR_MPAR_ERR
DDR_MCS[0:3]
DDR_MCK_P[0:1]_P/N
DDR_CAS,DDR_RAS,DDR_WE
DDR_MCKE[0:1]
IV35_SLP
DDR_RST_N
(CPLD)
I2C1_SCL,I2C1_SDA
MV_REF
VTT
IV35_SLP
(SPD_ADDR-0X51)
DDR3 DIMM SOCKET 240PIN
DIMM
T1040
DL_MDIC1
DL_MDIC0
IR3475 TPS
51200
For T1040:R-162Ohm
CKE_ISO_EN(CPLD)
Figure 2-4. T1040 and DDR connection
Although the platforms support all types, ranks and speeds of DIMMs within the
specification of the T1040, not all combinations of these three exist on the memory
market. Thus, the system is shipped with a “representative” DIMM, as noted in the below
table.
Other suitable memory DIMMs can be purchased and installed if needed; however,
Freescale only supplies the device shown.
Table 2-1. DDR3L UDIMM support
Platform Type Speeds Ranks DIMM
T1040RDB DDR3L 1600 MT/s Single Micron MT9KSF51272AZ-1G6
Table continues on the next page...
Chapter 2 Architecture
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Table 2-1. DDR3L UDIMM support (continued)
Dual Micron MT18KSF51272AZ-1G6
Quad (TBD)
2.6 SerDes port
The T1040 SerDes block provides eight high-speed serial communication lanes
supporting a variety of protocols, including:
•SGMII 1.25 Gbit/s
• QSGMII 5 Gbit/s
• PCIe Gen 1 x1 2.5 Gbit/s
• PCIe Gen 2 x1 5 Gbit/s
• SATA x1 1.5/3 Gbit/s
The following table explains the SerDes protocols supported on the T1040RDB board.
Table 2-2. SerDes protocol distribution
SerDes
SRDS_PRTCL A B C D E F G H Option
T1040/T1020 PCIe SGMII QSGMII QSGMII PCIe PCIe PCIe SATA 0x66
To comply with T1040 specifications, multiplexers are used to re-route and group the
SerDes lanes as shown in the figure below.
SerDes port
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