NXP Semiconductors UM11565 User manual

UM11565
NAFExx388 evaluation board
Rev. 1 — 29 March 2023 User manual
Document information
Information Content
Keywords SPI-bus, NAFE11388, NAFE71388, NAFE13388, NAFE73388 (Future release) analog front-end,
ADC, RTD, TC, HVDD, HVSS
Abstract The NAFExx388 evaluation board is easy to test and design for the NAFE11388, NAFE71388,
NAFE13388, and NAFE73388 1 which is a highly configurable, industrial-grade multichannel
analog input analog front-end (AFE) that meets high-precision measurement requirements. The
device is composed of a low-leakage, high-voltage multiplexer, low-offset drift buffers, a low noise
and drift PGA, a precision 24-bit sigma-delta analog-to-digital converter (ADC), low-drift voltage
reference. This evaluation board, along with the LPC54628 MCU board, provide an easy-to-use
evaluation platform.

NXP Semiconductors UM11565
NAFExx388 evaluation board
Rev Date Description
v.1 20230329 Initial release
Table 1.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
2 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES
ONLY. It is provided as a sample IC pre-soldered to a printed-circuit board to make it easier to access
inputs, outputs and supply terminals. This evaluation board may be used with any development
system or other source of I/O signals by connecting it to the host MCU computer board via off-the-
shelf cables. This evaluation board is not a Reference Design and is not intended to represent a final
design recommendation for any particular application. Final device in an application heavily depends
on proper printed-circuit board layout and heat sinking design as well as attention to supply filtering,
transient suppression, and I/O signal quality.
The product provided may not be complete in terms of required design, marketing, and or
manufacturing related protective considerations, including product safety measures typically found
in the end device incorporating the product. Due to the open construction of the product, it is the
responsibility of the user to take all appropriate precautions for electric discharge. In order to minimize
risks associated with the customers’ applications, adequate design and operating safeguards must be
provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact
NXP sales and technical support services.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
3 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
1 Introduction
The NAFExx388 evaluation board features a highly configurable, industrial-grade, multichannel AI-AFE family
of parts (11388, 13388, etc. …) that meets high-precision measurement requirements. The device is composed
of a low-leakage, high-voltage multiplexer, low-offset drift buffers, a low noise and drift PGA, a precision 24-bit
sigma-delta analog-to-digital converter (ADC), and low-drift voltage reference.
The AI-AFE family integrates:
•Input protection circuit for electromagnetic compatibility (EMC) and misuse wire scenarios
•Diagnostic circuits for input, open, and short circuit and impedance detection
To simplify diagnostic and functional safety, an advanced diagnostic circuit is implemented for channel loopback
reading, and output voltage or current bias circuits. The two precise reference voltage sources enable end-to-
end system self-calibration and advanced anomaly detection for predictive maintenance.
A graphical interface allows the user to easily explore the different functions of the driver. The IC communicates
to the host via the industry standard SPI-bus port. The evaluation software runs under the Microsoft Windows 7,
8, and 10 PC platform.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
4 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
2 Finding kit resources and information on the NXP website
NXP Semiconductors provides online resources for evaluation board and its supported device(s) on http://
www.nxp.com.
The information page for NAFExx388-EVB evaluation board is at http://www.nxp.com/NAFExx388-EVB. The
information page provides overview information, documentation, software and tools, parametrics, ordering
information and a Getting Started tab. The Getting Started tab provides quick-reference information applicable
to using the NAFExx388-EVB evaluation board, including the downloadable assets referenced in this document.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
5 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
3 Getting ready
Working with the NAFExx388-EVB requires the kit contents, additional hardware, and a Windows PC
workstation with installed software.
3.1 Kit contents
•Assembled and tested evaluation board in an antistatic bag
•USB 2.0 cable
•Spare jumpers
•AC-DC wall in 24 V power adapter
3.2 Assumptions
Familiarity with the SPI-bus is helpful, but not required.
3.3 Static handling requirements
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during
transport and handling. You must use a ground strap or touch the PC case or other grounded source
before unpacking or handling the hardware.
3.4 Minimum system requirements
•PC Pentium processor (or equivalent)
•One USB port (either 3.0 or 2.0 compatible)
•Windows 7, 8, 10
•OM13098 (LPC54628) MCU evaluation board (from www.nxp.com)
3.5 Power requirements
For NAFExx388 setup, connect the PC to the USB port J2 (out of the three USB ports J1, J2, and J3) to power
up the OM13098 MCU evaluation board.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
6 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
4 Getting to know the hardware
4.1 Board features
Device Description Location
NAFExx388 Eight-input SW configurable AI-AFE U1
MAX13256ATB Transformer driver U4
TGMR-511V6LF Transformer U5
Si8641BC-B-IS1 Quad-channel digital isolators U7
Si8642BC-B-IS1 Quad-channel digital isolators U8
MAX14761ETB Analog switches U14
CMXDM7002A N-channel MOSFET U16
LP2950ACDT-3P3RG +3.3 V LDO U17
Table 2. NAFExx388 evaluation board main components
4.2 Kit featured components
•A complete evaluation platform for the NAFExx388
•Eight input SW configurable AI-AFE
•Easy-to-use GUI-based software demonstrates the capabilities of the NAFE11388 and NAFE13388,
depending on the part installed on the board.
•Onboard transformer to provide DC-DC power supply (+3.3 V, ±15 V) to NAFExx388
•Convenient test points for easy scope measurements and signal access
•USB interface to the host PC
•Alternatively, an external power supply can be used to power the NAFExx388 evaluation board
4.2.1 Jumpers
Setting Jumper Comment
EXT_3V3 J78A pin 1 – J78B pin 1 External +3.3 V power selection
EXT_-15V0 J78A pin 2 – J78B pin 2 External -15 V power selection
EXT_15V0 J78A pin 3 – J78B pin 3 External +15 V power selection
Table 3. Jumper settings for external power supply (+3.75 V, +15.4 V, -15.4 V)
Setting Jumper Comment
3V3_LDO J78B pin 1 – J78C pin 1 AC-DC adapter/transformer +3.3 V power selection
TX_-15V0 J78B pin 2 – J78C pin 2 AC-DC adapter/transformer -15 V power selection
TX_15V0 J78B pin 3 – J78C pin 3 AC-DC adapter/transformer +15 V power selection
Table 4. Jumper settings for AC-DC adapter/transformer power supply (+3.75 V, +15.4 V, -15.4 V)[1]
[1] Warning: Make sure J88 = OPEN before connecting AC-DC adapter.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
7 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
5 Configuring the hardware
The NAFExx388 evaluation kit includes the NAFExx388 evaluation board, an OM13098 (LPC54628) evaluation
board, and a USB cable.
To set up the hardware, do the following:
1. Firmly connect the NAFExx388 (AFE) evaluation board to the LPC54628 (microcontroller) evaluation board
using the Arduino connectors.
2. To connect both boards, slide J15, J18, J19, and J22 male connectors at the bottom side of the NAFExx388
(AFE) evaluation board into the appropriate female connectors on the LPC54628 (microcontroller)
evaluation board as shown in Figure 1.
3. Apply AVDD/DVDD = 3.75 V on J9, HVDD = +15.4 V on J10, and HVSS = -15.4 V on J11 banana jack
connectors and turn on the power supply. An approximately 0.4 V additional supply on J9, J10, and J11
accounts for the voltage drop across the Schottky diode for reverse polarity protection and voltage drop
across 5 Ω resistor because of the supply current flowing into the pin of the device.
4. Use cable a USB to uUSB to connect the PC (USB) to the LPC54628EVAL (uUSB).
Figure 1. NAFExx388 evaluation board paired with OM13098 (LPC54628) evaluation board
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
8 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
Figure 2. Test setup showing connectivity between computer and evaluation system
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
9 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
6 Schematic, board layout, bill of materials
aaa-049224
AGND
HVDD
AGND
REFCAL_ H
REFCAL_ L
AI4N
AI4P
AGND
AICOM
AI3N
AI3P
AI2N
AI2P
AI1N
AI1P
HVDD
RE
F
_E
XT
RE
FN_A
D
C
RE
FP_
AD
C
CA
PN
_
AD
C
CA
PP
_
AD
C
A
G
N
D
A
VDD
RE
F
_INT
RE
F
_N
R
RE
F
_BYP
RE
F
_
B
U
F
A
G
N
D
A
VDD
A
G
N
D
DUT_3V3
REF_BYP
REF_INT
DUT_-15V0
DUT_-15V0
ADC/RESET
DUT_15V0
DUT_15V0
C24
4.7 µF
C23
0.1 µF
GND
A
G
N
D
A
G
N
D
HV
SS
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
17
XO
EXTCLK/XI
AGND
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
DVDD
DGND
GPIO4
GPIO3 GPIO2
GPIO1
GPIO0
AGND
AGND
AGND
AVDD
RSTB
SPI_ADDR
DGND
INTB
SYNC
CSB
SCLK
DIN
DOUT
DRDYB
DVDD
DGND
LDO_DIG
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
EPAD 65
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
GND
REFP1
ADC/RESET
1
2
3
4
(5) ADC _nRESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DUT_3V3
C22
100 pF
C21
0.1 µF
C20
4.7 µF
GND
C19
4.7 µF
C18
0.1 µF
C13
1 nF
R2
47 Ω
GND
C17
0.1 µF
C16
4.7 µF
C9
0.1 µF
C6
1 µF
C2
C3
4.7 µF
0.1 µF
C15
NOB
C11
0.1 µF
C244
4.7 µF C12
NOB
GNDGND
GND LDO O1
C5
0.1 µF
C4
4.7 µF
R153
100 Ω
J49
Header 3
Header_1X10
J89
Header 2
J81
R222
47 Ω
R25, 47 Ω
R27, 47 Ω
R30, 47 Ω
R29, 47 Ω
R28, 47 Ω R2 6, 47 Ω
R24, 430 Ω
R31, 47 Ω
D22
LED
J71
EXTCLK
C10
12 pF
C14
12 pF
GND GND GND GND
GND 1
2
2
1
3
2
4
13
GND
GND GND
GND
X1
18.432 MHz
C8
4.7 µF
C25
0.1 µF
C27
4.7 µF
R33
RTD
R32
1.25 kΩ
R34
1.25 kΩ
R205
250 Ω
D10
Diode TVS BI -DR
C43
0.1 µF
C42
0.1 µF
C238
NOB
C246
0.1 µF
R45
2.4 kΩ
C7
0.1 µF
GND
GND
GND
ADC AI1-
ADC AI1+
AI1-
AI1+
AI1-
GND2
J83
1
2
3
4
5
6
AI1+
GND
GND
GNDGND
AUX_-15V0 AUX _15V0
AUX_-15V0
EPAD
U14
MAX14761ETB
10
11
9 8 7 6
VCC
GND
B1
VN
B2
EN1 EN2 A1 VP A2
1 2 3 4 5
GND
GND GND
C28
0.1 µF
C26
4.7 µF
C23
Diode Zener
GND
C32
0.1 µF
C30
4.7 µF
GND
VREF_EXT
VREF_EX T
AUX_3V3 DUT_-15V0
C1
0.010 µF
U1
R20
10 kΩ
SW1
Push -button(red)
Header 3
J1
R3
R21
10 kΩ
D17
Diode
Zener
R4
R6
R5
R7
R9
R8
47 Ω
47 Ω
47 Ω
47 Ω
47 Ω
47 Ω
47 Ω
[5] ADC_nINT
[5] ADC_SYNC
[5] ADC_SPI0_nCS
[5] MCU_SPI0_SCK
[5] MCU_SPI0_MOSI
[5] MCU_SPI0_MISO
[5] ADC_nDR DY
DUT_3V3
AUX_3V3
DUT_3V3
DUT_3V3
REF_BUF
AUX_3V3
R1
10 kΩ
GND
R23
0 Ω
AUX_3V3
2
1
3
GND
10
9
8
7
6
5
4
3
2
1
GND
TP32
R206
250 Ω
R44
2.4 kΩ
GND GND
D9
Diode TVS BI -DR
GND
GND
C41
1 nF
GND GND
1 2 GND
ADC AI2+ AI2+
AI2+
R204
250 Ω
R43
J85
Jumper
Screw conn
GND1
2.4 kΩ
D8
Diode TVS BI-DR
D7
Diode TVS BI-DR
C4 0
1 nF
GND GND
1 2 GND
ADC AI2- AI2-
AI2-
R203
250 Ω
R42
J86
Jumper
2.4 kΩ
C227
0.1 µF
C226
4.7 µF
C230
0.1 µF
R52
NOB
D6
Diode TVS BI-DR
C39
0.1 µF
C38
0.1 µF
C237
NOB
R41
2.4 kΩ
GND
ADC AI3-
AICOM 21
ADC AI3+
AI3-
AI3+
AI3 -
GND3
J82
1
2
3
4
5
6
AI3+
GND
R51
NOB
R40
2.4 kΩ
GND
GND GND
GND GND
C33
0.010 µF
C3 4
0.010 µF
GND
D5
Diode TVS BI-DR
GND
GND
GND
C36
1 nF
GND GND
GND
ADC AI4+
AICOM
AI4+
AI4+
R38
Screw conn
GND4
2.4 kΩ
R39
2.4 kΩ
C37
1 nF
GND
R50
NOB
GND
R49
NOB
GND
D4
Diode TVS BI -DR
REFCA L_L
C35
1 nF
GND GND
ADC AI4-
ADX_REFCAL _L
ADX_REFCAL _H
AI4-
REFCAL_ L
AI4 -
R37
2.4 kΩ R48
NOB
GND
C228
0.1 µF
D3
Diode TVS BI -DR
J6
Header 2
R47
1 kΩ C45
10 nF
GND
REFCA L_H
REFCAL_ H
R46
1 kΩ C44
10 nF
GND
Figure 3. NAFExx388 portion schematic
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
10 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
aaa-049225
DUT POWER SUPPLIES MCU POWER SUPPLIES
3x3 HEADEROPTIONAL VOLTAGE REFERENCE. NOT ON BOARD
POWER DELIVERY TO U1 (DUT RAILS)
J9
Banana Jack Red
D11
RB058LAM-60TFTR
C46
0.1 µF
R10
5.11 Ω
C233
330 pF
C243
4.7 µF
R207
NOB
C47
4.7 µF
C48
NOB
GND
NC
U13
NOB
VIN
NC_1
GND
DNC
NC_3
VOUT
NC_2
1
2
3
4
8
7
6
5
EXT_3V3
C
A
1
GND
C61
0.1 µF
C62
1 µF
GND
GND_M
GND_M
C239
0.1 µF
GND
C232
1 µF
PWM2 PWM1
C242
NOB
J10
Banana Jack Red
D12
RB058LAM- 60TFTR
C49
0.1 µ F
C50
4.7 µF
C51
NOB
GND GND
EXT_15V0
C
A
1
GND
GND_M
GND_M
GND_M
GND_M
C241
NOB
GND_M
GND
GND_M
GND
TXI_-15V0
D1 S2
D2
G1
S1
G2
GND_M
GND_M
456
321
GND_M
3V3_LDO
VREF_EXT
R214
J87
J75
Header 3
Header 2
1 Ω
R212
100 Ω
VDD
EPAD
U4
MAX13255ATB
P3_10-CT3MAT0
P3_10-CT3MAT0
VDD
CLK
*EN
ITH
ST1
ST2
GND
GND
*FAULT
1
2
3
4
10
11
9
8
7
5 6
GND_M
C59
1 µF
C60
0.1 µ F
R189
1 kΩ
GND_M
R215
NOB
R191
91 Ω
U16
CMXDM7002A
C235
NOB
C231
NOB
C234
330 pF
GND
24 V
3V3_ D
2
1
1
2
3
R211
100 Ω
R216
NOB
R209
91 Ω
R213
1 Ω R221
0 Ω
D18 D19
D21D20
Diode Schottk y Diode Schottky
Diode Schottk y
Diode Schottky
R187
0 Ω
R196
0 Ω
R210
0 Ω
R195
0 Ω
R188
NOB
GND
LDO_IN
LDO_OUT
R190
10 kΩ
R198
0 Ω
GND
C240
1 µF
R200
1 kΩ
D26
LED
3V3_D
24 V
J11
Banana Jack Red
J12
Banana Jack Red D13
RB058LAM-60TFTR
C52
0.1 µF
C53
4.7 µF
C54
NOB
GND
EXT_-15V0
A
C
1
11
1
1
1
1
1
J34
Banana Jack Red
D15
RB058LAM- 60TFTR
C148
0.1 µ F
C149
4.7 µF
C150
NOB
R185
5.11 Ω
GND_M
3V3_D
GND_M
C
A
1
1
EXT_15V0
TX _15V0
J78C
U17
LP2950ACDT-3P3RG
HDR 1X3
1
2
3
TX_15V0
TX _-15V0
3V3_ LDO
13
2
OUTPUT
INPUT
GROUND
AUX_15V0
R184
5.11 Ω
R220
5.11 Ω
TXI_-15V0
J36
Banana Jack Red
J39
Banana Jack Red
D16
RB058LAM-60TFTR
C154
0.1 µF
C155
4.7 µF
C156
NOB
R183
5.11 Ω
24 V
C
A
1
1
J7
694103303002
D27
RB058LAM-60TFTR
C
A
132
GND_M GND_M
DUT_15V0
P1_22- CT2MAT3 P1_22-CT2MAT3
Annapurna demonstration board
J88
Header 2
U5
TGMR-511V6LF
1
2
1
2
3
6
5
4
GND
R208
10 kΩ
C236
NOB
C245
1 µF
EXT_-15V0
TX _-15V0
J78B
HDR 1X3
1
2
3
AUX_-15V0
R217
5.11 Ω
R219
5.11 Ω
DUT_-15V0
EXT_3V3
3V3_ LDO
J78A
HDR 1X3
1
2
3
AUX_3V3
R186
5.11 Ω
R218
5.11 Ω
DUT_3V3
Figure 4. Power supplies portion schematic
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
11 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
aaa-049226
Install jumper if all four DACs be reset at the same time. LPC54628 ARDUINO INTERFACE HEADERS
2P0_16-ADC0IN4
J15
P0_31-ADC0IN5
P1_0 -ADC0IN6
P3_4 -ACCL_INTR
P4_6 -FC9_SSELn1
P3_16-GPIO_SPI_CS2
P3_12-CLKOUT
P3_11-MCLK-PMOD2_GPIO
6x2 Header
Mate to J4/J12 of Kinetis/LPC546xx
P1_1-USER PB-USB1_OVRCURn
4
6
8
10
12
1
3
5
7
9
11
1
J17
P3_21-FC9_MOSI
SPI Header
GND_M
AARDVARK SPI Interface header
3
5
7
9
2
4
6
8
10
2
J18
3V3_D
R81
R83
R82
R84
47 Ω
47 Ω
47 Ω
R86
47 Ω
47 Ω
GND_M
nRESET_ULP
10x2 Header
Mate to J3/J10 of Kinetis/LPC546xx
+5 V should be supplied on J34
to power up LPC5 4628 kit
VDD_TARGET from LPC54628
connected to pin 8, 12
nRESET ULP
SJ24 from LPC54628
connected to pin 20
4
6
8
10
12
1
3
5
7
9
11
1413
1615
1817
2019
2
J19
P4 7- ARDUINO D8
GND_M
P3_20-FC9_SCK
P3_23-FC2_SCAX
JS19 on LPC54628 connected to pin 5
P3_24- FC2_SCLX P1_18-CAN1_RD
P1_17-CAN1_TD
P2_20-FC7_I2S _RX_WS
ADC_nDRDY
ADC_nINT
P3_22-FC9_MISO
P3_21- FC9_MOSI
P3_30-FC9_SSELn0
MCU_SPI0_SCK
MCU_SPI0_MISO
MCU_SPI0_MOSI
MCU_SPI0_nCS
10x2 Header
Mate to J2/J9 of Kinetis/LPC546xx
4
6
R65
47 Ω
R67
47 Ω
R69
47 Ω
R66
47 Ω
R68
47 Ω
R63
47 Ω
P0_24-SPIFI_IO0
P1_18-CAN1_RD
P3_22- FC9_MISO
P3_20-FC9_SCK
ADC_nDRDY
ADC_nINT
P1 18-CAN1_RD
P3_ 30-FC9_SSELn0
8
10
12
1
3
5
7
9
11
1413
1615
1817
2019
2
J22
P3_1-PDM0 DATA
P3_10-CT3MAT0
P1_22- CT2MAT3
P1_22- CT2MAT3
P3_10-CT3MAT0
P0_26- SPIFI_CLK
P0_25- SPIFI_IO1
R87
47 Ω
P0_24- SPIFI_IO0 ADC_SYN
ADC_nRESET
10x2 Header
Mate to J1/J13 of Kinetis/LPC546xx
Outputs are default to `L'
4
6
8
10
12
1
3
5
7
9
11
1413
1615
1817
2019
P3_22- FC9_MISO
P0_24- SPIFI_IO0
P0_25-SPIFI_IO1
P1_17-CAN1_TD
P2_20-FC7_I2S_RX_WS
P3_30-FC9_SSELn0
P1_22- CT2MAT3
P0_26-SPIFI_CLK
P3 1-PDM0_DATA
P4_6FC9_SSELn1
P3_16-GPIO_SPI_CS2
P3_11-MCLK-PMOD2_GPIO
P3_12-CLKOUT
P1_16-ADC0IN4
P3_23-FC2_SDAX
P4_7-A RDUINO_D8
P3_24- FC2_SCLX
P0_31-ADC0IN5
P1_0 -ADC0IN6
P3_4 -ACCL_INTR
GND_M
Molex 68 pins con
GND_M
P3_21-FC9_MOSI
P3_20-FC9_SCK
P3_10-CT3MAT0
1
J16
2
3
4
5
6
35
36
37
38
39
40
741
842
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
R60
47 Ω
R61
47 Ω
R62
47 Ω
U7
Si8641BC-B-IS1
GND_M
GND_M
GND_M
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
GND11
VDD1
A1_IN
A2_IN
A3_IN
A4_OUT
EN1
GND12
GND21
VDD2
B1_OUT
B2_OUT
B3_OUT
B4_IN
EN2
GND22
GND_M GND
P0_25-SPIFI_IO1
P0_24- SPIFI_IO0
P3_30-FC9_SSELn0
P1_17-CAN1_TD
ADC_nRESET
ADC_SYN
ADC_nINT
3V3_ D AUX_ 3V3
3V3_D AUX_3V3
GND
GND
R79
47 Ω
C56
0.1 µF
R164
47 Ω
R132
47 Ω
R141
47 Ω
R64
47 Ω C57
0.1 µ F
21
J79
CONN 4x2
43
65
87
ADC_nRESET (3)
ADC_SYNC (3)
ADC_SPIO_nCS (3)
ADC_nINT (3)
Outputs are default to `L'
U8
Si8642BC-B-IS1
GND_M
GND_M
GND_M
15
16
14
13
12
11
10
9
2
1
3
4
5
6
7
8
GND11
VDD1
A1_IN
A2_IN
A3_OUT
A4_OUT
EN1
GND12
GND21
VDD2
B1_OUT
B2_OUT
B3_IN
B4_IN
EN2
GND22
GND_M GND
P3_20-FC-9_SCK
P3_21-FC-9_MOSI
P3_22-FC-9_MISO
P1_18-CAN-1_RD
MCU_SPI0_SCK
MCU_SPI0_MOSI
MCU_SPI0_MISO
ADC_nDRDY
3V3_ D AUX_ 3V3
3V3_D AUX_3V3
GND
GND
R72
47 Ω
C55
0.1 µF
R74
47 Ω
R73
47 Ω
R75
47 Ω
C58
0.1 µ F
21
J78
CONN 4x2
43
65
87
MCU_SPI0_SCK (3)
MCU_SPI0_MOSI (3)
MCU_SPI0_MISO (3)
ADC_nDRDY (3)
TP43 TP42 TP33 TP34 TP35 TP36 TP37
Spread GND test points uniformly
across the board
Stand-offs spread uniformly
across the board
TP38 TP39 TP40 TP41
GND GND GND GND GND GND GND GND GND_M GND_M GND_M
H1
Standoff
1 1 1 1 1 1
H2
Standoff
H3
Standoff
H4
Standoff
H5
Standoff
H6
Standoff
Figure 5. Connectors and isolators portion schematic
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
12 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
Figure 6. Component and jumpers locations
The schematic, board layout and bill of materials for the NAFExx388 evaluation board are available at http://
www.nxp.com/NAFExx388-EVB.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
13 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
7 Tool interface
7.1 GUI installation
•Right click on the executable (SetupNAFExx388_x.x.x), run as administrator, and follow the prompts to install
the application.
•Click the Windows start button on bottom left and find the NAFExx388_EVB GUI application.
Figure 7. GUI screenshot
7.2 MCU (OM13098) board firmware update
1. The GUI shows an MCU Firmware Update Required message if an older firmware in the MCU board is
detected as shown in Figure 8.
2. Click OK to update the firmware in the MCU board.
3. Press SW1 (reset button) to reset the MCU board.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
14 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
Figure 8. MCU board firmware update
7.3 Connectivity check
1. Click the NAFExx388_EVB GUI application to open the GUI. If there isn’t connection with the MCU or the evaluation
board, the message on the left top of GUI will be the following:
2. The label "Disconnected" indicates if the connection is established between the MCU board and the PC. Upon USB
connection, the part read command is issued by the MCU, which updates the part label and type (low power or
high speed) accordingly. Upon successful connection with the MCU board, the GUI will be updated with the label
“Connected”. Furthermore, the GUI will recognize the part number and update itself accordingly.
3. The part number will follow the data sheet nomenclature:
a. NAFE11388B40 → No VIEX, low power, factory calibration.
b. NAFE71388B40 → No VIEX, high speed, factory calibration.
c. NAFE13388B40 → VIEX, low power, factory calibration.
d. NAFE73388B40 → VIEX, high speed, factory calibration.
e. NAFE13188B40 → VIEX, low power, no factory calibration.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
15 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
4. The NAFExx388 GUI is a smart GUI that caters to the full part family. The block diagram is updated based on the part
read back, that is, the VIEX block shows up for NAFEx3388 devices only.
7.4 Using the tool
7.4.1 Channel configuration
1. Select the channel gain using the dropdown menu of the programmable gain amplifier (PGA).
2. Configure the data rate, SINC filter order, and Settling mode via the corresponding dropdown menu of the
ADC
7.4.2 Conversion modes
Five types of reading (conversion) modes are possible from the device:
•Single-Channel Single-Reading (CMD_SS)
•Single-Channel Continuous Reading (CMD_SC)
•Multi-Channel Single-Reading (CMD_MS) (available in future revision)
•Multi-Channel Multi-Reading (CMD_MM)
•Multi-Channel Continuous Reading (CMD_MC)
Refer to the data sheet for more about these conversion modes.
1. Single-Channel Single-Reading
a. Click the Single Reading button after picking Inputs under test from MUX drop-down menu.
b. Read the input voltage on Reading Result box.
2. Single-Channel Continuous Reading
a. Enter the number of samples required in the box and click the Continuous Reading button. Once the
Continuous Reading button is clicked, a dialog box will open to pick a folder to create a .csv conversion
results file on the hard drive with the number of samples requested.
3. Multi-Channel Multi-Reading
a. Preconfigure appropriate channels to be sequenced using the AFE configuration dropdown menu and
enable those channel numbers accordingly under the Multi-Channel section at the bottom right of the
GUI.
b. Click the Multi-Reading button
c. Read the input voltages in Reading Result multibox.
4. Multi-Channel Continuous Reading
a. Preconfigure the appropriate channels to be sequenced using the AFE configuration dropdown menu
and enable those channel numbers under the Multi-Channel section at the bottom right of the GUI.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
16 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
b. Click the Continuous Reading button and wait for the dialog box to pick the folder to create a .csv
conversion results file on the hard drive with the number of samples requested.
7.4.3 Data-rate selection
The AI-AFE provides a flexible ADC configuration that enables the user to configure Settling mode, digital SINC
filter, and data rate. As reported in the data-rate table, the data-rate output is a function of the combination of
Settling mode, digital SINC filter, and data rate.
The easier way to configure the AI-AFE is:
1. Select the Settling mode (normal or single cycle)
2. Select the digital SINC filter
3. Select the data rate
For example, to select 9000 sps in Single-Cycle Settling mode and SINC4:
1. Select normal settling in the Settling mode dropdown menu.
2. Select SINC 4 in the filter dropdown menu.
3. Select 9000 sps in the data-rate dropdown menu.
Normal settling Single-cycle settling
DRO code OSR SINC4 SINC4+
SINC1
SINC4+
SINC2
SINC4+
SINC2
SINC4+
SINC4
SINC4 SINC4+
SINC1
SINC4+
SINC2
SINC4+
SINC2
SINC4+
SINC4
0 8 288000 72000
1 12 192000 48000
2 16 144000 36000
3 24 96000 24000
4 32 72000 18000
5 48 48000 12000
6 64 36000 9000
7 96 24000 6000
8 128 18000 4500
9 192 12000 3000
10 256 9000 2250
11 384 6000 1500
12 512 4500.00 4500.00 4500.00 4500.00 2250.00 1500.00 1125.00 900.00
13 768 3000.00 3000.00 3000.00 3000.00 1500.00 1000.00 750.00 600.00
14 1024 2250.00 2250.00 2250.00 2250.00 1125.00 750.00 562.50 450.00
15 2048 1125.00 1125.00 1125.00 1125.00 562.50 375.00 281.25 225.00
16 4096 562.50 562.50 562.50 562.50 281.25 187.50 140.63 112.50
17 5760 400.00 400.00 400.00 400.00 200.00 133.33 100.00 80.00
18 7680 300.00 300.00 300.00 300.00 150.00 100.00 75.00 60.00
19 11520 200.00 200.00 200.00 200.00 100.00 66.67 50.00 40.00
20 23040 100.00 100.00 100.00 100.00 50.00 33.33 25.00 20.00
21 38400 60.00 60.00 60.00 60.00 30.00 20.00 15.00 12.00
22 46080 50.00 50.00 50.00 50.00 25.00 16.67 12.50 10.00
23 76800 30.00 30.00 30.00 30.00 15.00 10.00 7.50 6.00
24 92160 25.00 25.00 25.00 25.00 12.50 8.33 6.25 5.00
25 115200 20.00 20.00 20.00 20.00 10.00 6.67 5.00 4.00
26 153600 15.00 15.00 15.00 15.00 7.50 5.00 3.75 3.00
27 230400 10.00 10.00 10.00 10.00 5.00 3.33 2.50 2.00
28 307200 7.50 7.50 7.50 7.50 3.75 2.50 1.88 1.50
Table 5. Data rate dropdown menu
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
17 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
CHANNEL POINTER/
GAIN OFFSET POINTER PGA SETTING OFFSET COEFF GAIN COEFF
0 PGA0: Channel gain = 0.2 V/V SINGLE ENDED AIxP 0x0000FD 0x7EC2EA
1 PGA1: Channel gain = 0.4 V/V SINGLE ENDED AIxP 0x0000FA 0x7EC43D
2 PGA2: Channel gain = 0.8 V/V SINGLE ENDED AIxP 0x0000FA 0x7EC0BB
3 PGA3: Channel gain = 1.0 V/V SINGLE ENDED AIxP 0x000000 0x800000
4 PGA5: Channel gain = 2.0 V/V SINGLE ENDED AIxP 0x000000 0x800000
5 PGA7: Channel gain = 4.0 V/V SINGLE ENDED AIxP 0x000000 0x800000
6 PGA8: Channel gain = 8.0 V/V SINGLE ENDED AIXP 0x000000 0x800000
7 PGA9: Channel gain = 16 V/V SINGLE ENDED AIxP 0x000000 0x800000
8 PGA0: Channel gain = 0.2 V/V SINGLE ENDED AIxN 0x0000FC 0x7EC25C
9 PGA1: Channel gain = 0.4 V/V SINGLE ENDED AIxN 0x0000FF 0x7EC3F2
10 PGA2: Channel gain = 0.8 V/V SINGLE ENDED AIxN 0x0000FF 0x7EC089
11 PGA3: Channel gain = 1.0 V/V SINGLE ENDED AIxN 0x000000 0x800000
12 PGA5: Channel gain = 2.0 V/V SINGLE ENDED AIxN 0x000000 0x800000
13 PGA7: Channel gain = 4.0 V/V SINGLE ENDED AIxN 0x000000 0x800000
14 PGA8: Channel gain = 8.0 V/V SINGLE ENDED AIXN 0x000000 0x800000
15 PGA9: Channel gain = 16 V/V SINGLE ENDED AIxN 0x000000 0x800000
Table 6. Calibration coefficients table
7.5 Application test cases
7.5.1 Single-Channel Reading (SCR) example
1. Select which channel configuration (channel #0-16 config) will be used to read the voltage in the AFE Config
dropdown menu.
Figure 9. AFE Config
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
18 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
2. Select input channels from the MUX dropdown menu (HV_INP, HV_INV).
Figure 10. Input channels
3. Select PGA, SINC FILTER, ADC SETTING MODE, ADC DATA RATE, CHANNEL PROGRAM DELAY and
CALIBRATION COEFFICIENT settings in the dropdown menus.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
19 / 39

NXP Semiconductors UM11565
NAFExx388 evaluation board
Figure 11. Dropdown menus
4. Click the Single Reading button to read a single-channel voltage value in the Reading Result box.
Figure 12. Single Reading button
7.5.2 Single-Channel Continuous Reading (SCCR) example
1. Follow steps 1 through 3 described in Section 7.5.1.
2. Key in the number in the Number of samples box.
UM11565 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1 — 29 March 2023
20 / 39