NXP Semiconductors P4080 User manual

Freescale Semiconductor
User Guide
© 2011 Freescale Semiconductor, Inc. All rights reserved.
1Overview
The P4080 development system (DS) is a high-performance
computing, evaluation, and development platform
supporting the P4080 Power Architecture® processor. The
P4080 development system’s official designation is
P4080DS, and may be ordered using this part number.
The P4080DS is designed to the ATX form-factor standard,
allowing it to be used in 2U rack-mount chassis, as well as in
a standard ATX chassis. The system is lead-free and
RoHS-compliant.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Block Diagram and Placement . . . . . . . . . . . . . . . . . . 4
4. Evaluation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7. Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 45
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
P4080 Development System User’s Guide
by Networking and Multimedia Group
Freescale Semiconductor, Inc.
Austin, TX
Document Number: P4080DSUG
Rev. 0, 07/2010

P4080 Development System User’s Guide, Rev. 0
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Features Summary
2 Features Summary
The features of the P4080DS development board are as follows:
• Support for the P4080 processor
— Core processors
– Eight e500mc cores
– 45 nm SOI process technology
— High-speed serial port (SerDes)
– Eighteen lanes, dividable into many combinations
– Five controllers support five add-in card slots.
– Supports PCI Express, SGMII, Nexus/Aurora debug, XAUI, and Serial RapidIO®.
— Dual DDR memory controllers
– Designed for DDR3 support
– One-per-channel 240-pin sockets that support standard JEDEC DIMMs
— Triple-speed Ethernet/ USB controller
– One 10/100/1G port uses on-board VSC8244 PHY in RGMII mode.
– One USB ULPI
– Combo USB/RJ45 stack
— Local bus
– 128-Mbyte NOR Flash (fast boot)
– PromJet debug port
— eSDHC
– Connects to SDMedia card slot for boot code or mass storage
—SPI
– 16-Mbyte EEPROM device for boot code and storage
—I
2C
– Three controllers
–I
2C-based, real-time clock and battery-backed SRAM
– EEPROM storage for boot-sequencer, SystemID, ngPIXIS(FPGA) processor code, and so
on
— UART
– Two serial ports at up to 115200 Kbps
— Debug features
– Both Legacy COP/JTAG and Aurora/Nexus debug support
– EVT support
— Package
– 1295-pin, 1 mm pitch BGA
– Socket and solder attach can be supported.

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Features Summary
• System Logic ngPIXIS(FPGA)
— Manages system reset sequencing
— Manages system and SerDes clock speed selections
— Implements registers for system control and monitoring
— Manages boot and RCW source selection
— Internal 8-bit MCU allows independent VCore/temperature monitoring and reconfiguration.
•Clocks
— System clock
– SYSCLK switch settable to oneof eight commonsettings inthe interval 66 MHz–133 MHz.
– Software settable in 1-MHz increments from 1–200 MHz.
— SerDes clock
– Supports three domains
– 100-MHz, 125-MHz and 156.25-MHz configurations to support PCI Express, SGMII and
XAUI
• Power supplies
— Three dedicated programmable regulators supplying two cores and platform power pools
— PMBus control
— GVDD (DDR power) and VTT/VREF adjustable for DDR3
— 2.5-V power for Ethernet PHY

3 Block Diagram and Placement
This figure shows the major functions of the P4080DS.
Figure 1. Block Diagram
P4080
ULI
,
SATA
Add-in
Card
SATA
Add-in
Card
USB
1
CPU B DDR2
DUART 2
I2C 3
JTAG
Plug-INPlug-IN
CPU 0:3
CPU 4:7
Platform/Serdes
DDR3Regulator
RCW
NOR FLASH
RCW
NOR FLASH
DDR3 1
DDR3 DIMM
DDR3 2
DDR3 DIMM
x2
x2
PCI Exp 2.0 Video slotPCI Exp 2.0 Video slot
PCI Exp 2.0 slot/ SRIO/ SGMII
x4
System
Control /PM
Logic FPGA Local BusLocal Bus
Emulator
PromJet
Emulator
PromJet
SYS/PEX
Clocks
SGMII/XAUI Riser Slot
SPI
4- bi t S D/ MM C4- bi t S D/ MM C Each riser
supports 1 XAUI
OR 4 SGMII
using x4 lanes
Three power pools supported by three
independent programmable regulators
SGMII/XAUI Riser Slot
FlashFlash
(OCTAL CORE)
Regulators
AB CD E-H
Bank3 A-D
Bank1
FLASH/RCWFLASH/RCW
X2X2 Aurora DEBUGAurora DEBUG
IJ
RTC/BATRTC/BAT
COP Legacy connCOP Legacy conn Run Control/Trace connRun Control/Trace conn
PCI Exp 2.0 Video slotPCI Exp 2.0 Video slot
TSE C x1
10/100/1G RGMII10/100/1G RGMII
X4X4
X4
Bank2 A-D

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Block Diagram and Placement
This figure highlights more difficult-to-find connections that are commonly used.
Figure 2. Expedition Top View
Notes:
I2C HEADERS
AURORA and LEGACY COP CONNECTORS
ATX POWER CONNECTORS
CPU FAN HEADER

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Evaluation Support
4 Evaluation Support
The P4080DS is intended to evaluate as many features of the P4080 as are reasonable within a limited
amount of board space and cost limitations. This table shows an evaluation of the P4080DS.
4.1 Development System Use
For generalhardware and/or software development andevaluationpurposes,the P4080DScan beused just
like an ordinary desktop computer. In the absence of special hardware or software configuration, the
P4080DS operates identically to a development/evaluation system such as ArgoNavis(8641DS) or other
Table 1. P4080DS Evaluation Summary
P4080 Feature Evaluation Support/Methods
SerDes • Connects to PCI Express slots for use with graphics or other PEX cards
• Testable via PCI Express card (typically graphics) or CatalystTM PCI Express control/monitoring card
• Traffic monitoring via Tek/Agilent passive mid-point probing
Memory Controller
DDR3
• Combined GVDD (VIO), VTT and MVREF supplies
• Debugging uses Tek/NextWave analyzer breakout cards.
• No special MECC/debug tap
eSDHC Supports SDMedia cards and MMC cards
SPI Supports standard and x4 devices
Local Bus • 1 bank of 16-bit, 8-Mbyte–1-Gbyte Flash (64 Mbytes by default)
• Option for PromJet access
• System controller (ngPIXIS) registers implementing the following: board ID, VDD control, frequency reset,
self-reset reset, and so on
Serial • UART supports two 4-wire serial ports.
I2CI
2C bus #1 for the following:
• Boot initialization code
• System EEPROM (MAC address storage, serial number, and so on)
• PMBus power regulator control
•I
2C bus #2 for the following:
• DDR bus DIMM module SPD EEPROMs
• PCI/PCI Express slots (as “SMBus”)
• ngPIXIS access
Clocking • Digitally settable SYSCLK and DDRCLK clock generator
• Switch-selectable coarse settings
• Software-selectable fine settings
• SerDes reference clocks to SerDes on P4080, NVidia, and slots
• Reference clock
GPIO • All GPIO attached to test 0.1” header
• Some GPIO have predefined board functions that can be eliminated.
DMA Controlled and executable by ngPIXIS logic.
IRQs EVENT switch normally asserts IRQ* but can drive SRESET0, and/or SRESET1 via software setting.
Power • VDD (VCORE+VDD) VID switch-settable
• ngPIXIS software-monitored/controlled voltages

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Evaluation Support
members the HPC family. This figure shows an example of the P4080DS system in a desktop
configuration.
Figure 3. P4080DS Desktop Configuration
4.2 Rackmount Server Use
For use in a rackmount chassis, the P4080DS requires the following modifications:
• Low-profile heatsink
• Non-socketed board
Otherwise, it is similar to the desktop case.
4.3 Embedded Use
For general embedded hardware and/or software development and evaluation purposes, the P4080DS can
be used just like an ordinary desktop computer. Perpiherals and embedded storage can be connected to the
PromJet superset connector.
The ngPIXIS FPGA is used to provide startup configuration information for DINK, UBOOT or Linux and
other advanced features are used or ignored.
4.4 AVP-Controlled Evaluation
Formany test situations, itis desirable to download a test vector program and run the results. TheP4080DS
can do this by using a PCI-based control card, such as the DataBlizzard, or a PCI Express-based control
P4080DS

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Architecture
card, such as Freescale’s Komodo card, either stand-alone or in coordination with the ngPIXIS. This table
lists an overview example of the steps required to accomplish this.
5 Architecture
The P4080DS architecture is primarily determined by the P4080 processor, and by the need to provide
“typical,” OS-dependent resources (disk, Ethernet, and so on).
5.1 Processor
This table lists the major pin groupings of the P4080.
Table 2. AVP Execution Steps
Step Details
Assert Target Reset Set target reset Control card asserts “flying lead” reset line; alternately, the
ngPIXIS register bit PX_RST[RSTL] is set to ‘0’.
Target processor (not the system) is reset.
Setup New Target Environment Set target core VDD VCTL[VCORE]=1
VCORE=xxxxxxxx
Set requested SYSCLK VCTL[SYSCLK]=1
VSPEED[SYS]=xxx
Restart Target Set target reconfiguration VCTL[GO]=1
System is reconfigured, target processor remains in reset. This may take several milliseconds.
Download Target Download to target execution space. Presumably the DDR and PCIExpress resources were
configured by the I2C sequencer. If so, a PCIMaster such as the DataBlizzard can simply write
test code to system memory via PCI->DDR path.
Release Target Reset Release target reset Control card deasserted “flying lead” reset line; alternately
the ngPIXIS register bit PX_RST[RSTL] is set to ‘1’.
Target processor executes code.
Collect Results Results can be extracted from system DDR, PCI Express graphics memory (used as a buffer),
or other memory (SDMedia, Flash, PromJet).
Table 3. P4080 Pin Groupings Summary
Signal Group Details
Memory Controllers Section 5.1.1, “DDR”
SerDes x18 Section 5.1.2, “SerDes x18”
Ethernet Section 5.1.3, “Ethernet (EC)”
IEEE 1588 Section 5.1.4, “Support for IEEE Std 1588™Protocol”
Local Bus Section 5.1.5, “Local Bus”
eSDHC Section 5.1.6, “eSDHC”
SPI Section 5.1.7, “SPI Interface”
USB Section 5.1.8, “USB Interface”
DMA Section 5.1.9, “DMA Controller”

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Architecture
5.1.1 DDR
The P4080 supports DDR2 and DDR3 devices; however, the P4080DS supports only DDR3 , using
industry-standard JEDEC DDR3 2-rank and 4-rank DIMM modules. However, the system is shipped and
supported by software to support UDIMM 2-rank modules for targeted vendors. The type and vendor may
change as memory availability varies. The memory interface includes all the necessary termination and
I/O power, and is routed so as to achieve maximum performance on the memory bus.
eOpenPIC Section 5.1.10, “eOpenPIC Interrupt Controller”
GPIO Section 5.1.11, “GPIO Controller Port”
System Control Section 5.1.12, “Control Group”
UART Section 5.1.13, “UART Serial Ports”
I2C Section 5.1.14, “I2C”
EM1 and EM2 Management Section 5.1.15, “EM1 and EM2 Management Busses”
Debug/Power Management Section 5.1.16, “Debug and Power Management”
Clock Section 5.1.17, “Clock”
Thermal Section 5.1.18, “Temperature”
Power Section 5.1.19, “Power”
Table 3. P4080 Pin Groupings Summary (continued)
Signal Group Details

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Architecture
This figure shows the general DDR memory architecture per controller.
Figure 4. P4080DS Memory Architecture per controller
Note that the P4080DS does not directly support the use of the MECC pins to access internal debug
information, because the P4080DSdoes not provide the special multiplexer, and thus has a simpler routing
and signal integrity status. On the other hand, the P4080DS does not interfere with this path, so access to
debug information on the MECC pins is possible with the use of a NextWave (or equivalent) DDR logic
analyzer connector and the use of non-ECC DDR modules.
32-bit DDR3 interface mode is supported; from the viewpoint of the P4080DS board, the unused lower
MDQ/MDS/MDM signals are simply inactive.
The DDR3 power supplies the following interface voltages:
• VDD_IO up to 20 W (10 A at 1.5 V nominal)
• VDDQ+VTT up to 2 A
• MVREF up to 10 mA
P4080 DDR3 DIMM
MRAS RAS
CAS
WE
CKE[1:0]
A[15:0]
DQ[63:0]
DQS/DQS
DM[8:0]
CB[7:0]
MCAS
MWE
MCKE[1:0]
MCS[3:0]
MA[15:0]
MBA[2:0]
MDQS[8:0]/MDQS[8:0]
MDM[8:0]
MDQ[63:0]
MCK[0:2]
MCK[0:2]
MVREF
I2C_SDA
I2C_SCK
S[3:0]
BA[2:0]
MECC[7:0]
CK[0:1]
CK[0:1]#
RESET#
SDA
SCL
VREF
DDR3 Power VTT
MEM_RST
GVDD VDD