NXP Semiconductors LPCXpresso54S018M User manual

UM11192
LPCXpresso54S018M Board User Manual
Rev. 1.0 —13th February 2019
User manual
Document information
Info
Content
Keywords
LPC54S018M-EVK, LPC54S018J2M, LPC54S018J4M, LPC54018J2M,
LPC54018J4M
Abstract
LPCXpresso54S018M User Manual

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0 —13th February 2019
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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Revision history
Rev
Date
Description
1.0
20180204
Initial revision

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0 —13th February 2019
3 of 34
1. Introduction
The LPCXpresso™ family of boards provides a powerful and flexible development
system for NXP's LPC Cortex®-M family of MCUs. They can be used with a wide range
of development tools, including NXP’s MCUXpresso IDE. The LPCXpresso54S018M
development board has been developed by NXP to enable development with the
LPC54S018JxM and LPC54018JxM family devices. It is very similar to the
LPCXpresso54S018 design, with only a few minor modifications to accommodate the
differences between these two series of devices. The board uses an LPC54S018J4M in
a BGA180 package.
The LPCXpresso54S018M can provide CAN-FD support when combined with the
OM13099 CAN-FD shield or using external transceivers connected via the available
expansion site connectors.
Fig 1. LPCXpresso54S018M underside view
The following aspects of interfacing to the board are covered by this guide:
•Main board features.
•Setup for use with development tools.
•Board interface connectors.
•Jumper settings.

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
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© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0 —13th February 2019
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2. Feature summary
The LPCXpresso54S018M board includes the following features:
•On-board, high-speed USB based, Link2 Debug Probe with CMSIS-DAP and
SEGGER J-Link protocol options:
Link2 probe can be used with on-board LPC54S018J4M or external target.
UART and SPI port bridging from LPC54S018J4M target to USB via the on-board
Debug Probe.
Support for external Debug Probe.
•3 x user LEDs
•Target Reset, ISP (3) and user buttons
•Expansion options based on popular standards:
Arduino UNO compatible expansion site with additional LPCXpresso V3 standard
connections
PMod™ compatible expansion port
Host connection / general purpose expansion port
•On-board 3.3V regulator with external power supply options.
•Built-in power consumption measurement for target LPC54S018J4M MCU.
•Winbond 128Mb W9812G6JB-6I SDRAM
•Knowles SPH0641LM4H digital microphone.
•Full size SD/MMC card slot.
•NXP MMA8652FCR1 accelerometer.
•Stereo audio codec with line in/out.
•High and full speed USB ports with micro A/B connector for host or device
functionality.
•10/100Mbps Ethernet (RJ45 connector).
•Rocktech RK043FN02H 272x480 color LCD with capacitive touch screen. Available
separately.
2.1 Board layout and settings
This section provides a quick reference guide to the main board components,
configurable items, visual indicators, and expansion connectors. Fig 2 shows the layout
of the components on the LPCXpresso54S018M board.

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
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© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0 —13th February 2019
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Fig 2. LPCXpresso54S018M main feature layout
The optional LCD panel is mounted on the reverse side of the board, connected to the
circuitry via two flex cable connectors. 4 double-sided adhesive pads are provided on the
board to attach the LCD. The LCD panel is available for purchase separately - visit
https://www.nxp.com and search for part number RK043FN02H-CT or contact an NXP
distributor to order this panel.
Fig 3 shows the location of indicators and jumpers.

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User Manual for LPCXpresso54S018M Development Board
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User manual
Rev. 1.0 —13th February 2019
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Fig 3. Jumper locations
Table 1 lists the function of each jumper.
Table 1. Jumpers
Circuit ref
Description
Section
JP1
Target processor selection for the on-board Debug Probe.
Jumper open (default) the LPC54S018J4M Target SWD interface
enabled. Normal operating mode where the Target SWD is
connected to either the on-board Link2 Debug Probe or an external
Debug Probe.
Jumper shunted, the LPC54S018J4M Target SWD interface is
disabled. Use this setting only when the on-board Link2 Debug
Probe is used to debug an off-board target MCU.
3, 4
JP2
Buffer Power Selection
For On-board Target place in position 1-2 (default)
For Off-board Target place in position 2-3
3, 4
JP3
This header (not installed by default) provides a convenient
connection point to provide external ADC positive and negative
voltages. To inject these voltages at this header SJ22 (for VREFN)
and/or SJ23 (for VREFP) need to be moved from the default 1-2
position to the 2-3 position.
See
Schematic

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
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User manual
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Circuit ref
Description
Section
JP4
This set of 3 jumpers control various selections for power
measurement:
Position 1-2 and 3-4 are in parallel with 1 ohm resistors. Current
can be measured across these jumper headers to determine
current flow into the LPC54S018J4M target.
Position 5-6 (installed by default) can be left open and a current
meter connected between these pins to directly measure current
flow into the LPC54S018J4M target.
6
JP5
Link2 (LPC43xx) force DFU boot –2 position jumper pins.
1) Jumper open (default) for Link2 to follow the normal boot
sequence. The Link2 will boot from internal flash if image is found
there. With the internal flash erased the Link2 normal boot
sequence will fall through to DFU boot.
Jumper shunted to force the Link2 to DFU boot mode. Use this
setting to reprogram the Link2 internal flash with a new image
(using the LPCScrypt utility) or to use the MCUXpresso IDE with
CMSIS-DAP protocol.
Note that the LPCXpresso54S018M Link2 flash is pre-programmed
with a version of CMSIS-DAP firmware by default.
4
JP6
When open (default), the “Bridge” UART and SPI connections from
the Link2 probe are driven to the LPC54S018J4M target.
Install JP6 when using the SPI interface at connector J14 and/or
FC0 UART at P4 (FTDI). Note that this disables the Link2 SPI and
UART (bridge) probe connections.
8.3
JP7
(not
installed by
default)
JP7 may be fitted to provide a convenient way to enable/disable
the reset signal to/from the expansion connectors. Solder jumper
JS28 should be removed if JP7 is to be used.
See
schematic
JP9
USB host Vbus selection
Note that only one of USB0 or USB1 can be configured as a USB
host port at any given time (this is a board restriction, not a
limitation of the LPC54S018J4M.)
Install jumper in position 1-2 for USB1 (High Speed) to provide
Vbus (i.e. enable USB host capability) (Default)
Install jumper in position 2-3 for USB0 (Full Speed) to provide Vbus
(i.e. enable USB host capability)
8.2
JP10
USB host power control selection
This jumper selects routing of USB port power and overcurrent
detect from either the USB0 or USB1 ports of the
LPC546x8/540xx. Note that only one of USB0 or USB1 can be
configured as a USB host port at any given time (this is a board
restriction, not a limitation of the LPC546x8/540xx.)
Leave open when using USB1 (High Speed) as a USB host
(Default)
Install jumper for USB0 (Full Speed) to provide Vbus (i.e. enable
USB host capability)
8.2

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User Manual for LPCXpresso54S018M Development Board
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Circuit ref
Description
Section
JP11 &
JP12
USB0 host / Ethernet TXD/RXD selection
Due to sharing of pin functionality on this development board, it is
not possible to support the Ethernet port and USB0 overcurrent
feature simultaneously. For both JP11 and JP12:
Install jumper in position 1-2 to enable Ethernet (Default)
Install jumper in position 2-3 for USB0 (Full Speed) (i.e. enable
USB host capability)
8.2
JP13
USB0 host / Ethernet selection
Due to sharing of pin functionality on this development board, the
P4-7 port pin is used for either the USB0 port or as a general
purpose signal on the expansion connector.
Install jumper in position 1-2 to route P4-7 to the expansion
connector.
Install jumper in position 2-3 for USB0 (Full Speed) (i.e. enable
USB host capability)
8.2, 8.6
JP14
P1_16 Ethernet / EMC selection
Due to sharing of pin functionality on the 180 pin LPC54S018J4M
package, on this board port pin P1_16 must routed via JP14 to
either be used as the Ethernet MDC signal or EMC address line
A10. Place in location 1-2 (EN) when using Ethernet or position 2-3
(SD) when using EMC.
JP15
P1_23 Ethernet / EMC selection
Due to sharing of pin functionality on the 180 pin LPC54S018J4M
package, on this board port pin P1_23 must routed via JP15 to
either be used as the Ethernet MDIO signal or EMC address line
A11. Place in location 1-2 (EN) when using Ethernet or position 2-3
(EN) when using EMC.
Table 2 describes the board LED and button functions, and connectors.
Table 2. LEDs, buttons and connectors
Circuit Ref
Description
Section
D7
SD card slot power enable
This LED illuminates when power is enabled to the SD card slot
(controlled by LPC54S018J4M port P2-5.)
n/a
D9, D11,
D12
User LEDs
These LEDs are for application use. They are illuminated when the
driving signal from the LPC54S018J4M is low. The LEDs are driven by
ports P2-2 (D9), P3-3 (D11) and P3-14 (D12).
n/a
D10
Link2 boot mode
Link2 LPC43xx BOOT0_LED indicator. Reflects the state of LPC43xx
Link2 MCU P1_1. When the boot process fails, D1 will toggle at a 1 Hz
rate for 60 seconds. After 60 seconds, the LPC43xx is reset.
n/a

NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
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User manual
Rev. 1.0 —13th February 2019
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Circuit Ref
Description
Section
D14
Target power
This LED illuminates when the 3.3V supply to the LPC54S018J4M is
present.
n/a
D15
Reset LED
This LED illuminates when reset is asserted either via the expansion
connector or when reset button SW1 is pressed.
n/a
SW1
Reset button
Press and release this button to reset the LPC546x8/540xx. Note that
this does not reset the Link2 Debug Probe.
n/a

NXP Semiconductors
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User Manual for LPCXpresso54S018M Development Board
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User manual
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Circuit Ref
Description
Section
SW2, SW3,
SW4
ISP / User buttons
These switches can be used to force the LPC54S018J4M in to ISP boot
modes, as shown below. Note that ISP boot is also affected by OTP bit
settings, and behavior will also be modified based on port activity as the
boot ROM executes. Refer to the device User Manual for more
information. Signal is low when the button is pressed.
Mode / Boot source
ISP2
(P0-6)
ISP1
(P0-5)
ISP0
(P0-4)
Auto boot:
If OTP BOOT_SRC not set,
LPC54S018J4M will look for a valid
image in internal flash, then external
SPI flash, then external parallel flash.
High
High
High
USART/I2C/SPI boot
High
High
Low
SPI Boot:
Boot from SPI NOR flash connected to
Flexcomm 9. If no valid image is found,
ISP boot will commence. This board
does not have on-board SPI flash, but
the SPI port signals to support this are
available on connectors J9 and J13.
High
Low
High
Reserved
High
Low
Low
SPIFI boot:
Boot from internal flash memory. If no
valid image is found, ISP boot will
commence, depending on OTP bit
settings.
Low
High
High
USB0 (full speed) ISP DFU
Low
High
Low
USB1 (high speed) ISP DFU
Low
Low
High
The ISP pins are sampled by the LPC54S018J4M boot ROM code
immediately following reset, so to initiate an ISP boot press and hold the
required ISP buttons while pressing and releasing the reset button
(SW1.)
Following reset, these buttons may also be used by a user application.
Note: A board power cycle (holding down ISP required buttons while
power is applied) may be required to ensure correct driving of the ISP
pins when the EMC bus has been initialized, since these pins are shared
with the EMC D2-D3 pins, and the SDRAM chip select may float at reset.
SW5
User button
This button is connected to LPC54S018J4M port pin P1-1 and is
provided for user applications. Port P1-1 is pulled to ground when the
button is pressed.
J1
External +5V power
Micro USB connection for power to the LPC54S018J4M target and
peripheral circuitry (excluding Link2 Debug Probe).