NXP Semiconductors UM11586 Instruction Manual

UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
Rev. 1 — 3 May 2021 User manual
Document information
Information Content
Keywords VR5510, KITVR5510SKTEVM, evaluation kit, automotive, multi-output power
management integrated circuit
Abstract This user manual describes how to use the KITVR5510SKTEVM evaluation
kit. The VR5510 is an automotive multi-output power management integrated
circuit which focuses on gateway, V2X, and infotainment applications.

NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
Rev Date Description
v.1 20210503 Initial release
Modifications NA
Revision history
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NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
1 Introduction
This document is the user guide for the KITVR5510SKTEVM evaluation boards. This
document is intended for engineers involved in the evaluation, design, implementation,
and validation of VR5510 Power Management Integrated Circuit (PMIC) for high
performance applications.
The scope of this document is to provide the user with information that covers interfacing
with the hardware, installing the GUI software, using other tools, and configuring the
board for the application environment.
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KITVR5510SKTEVM Evaluation Kit User Guideline
2 Finding Kit Resources and Information on the NXP Web Site
NXP Semiconductors provides online resources for this evaluation board and its
supported device(s) on http://www.nxp.com.
The information page for KITVR5510SKTEVM evaluation board is at http://www.nxp.com/
KITVR5510SKTEVM. The information page provides overview information,
documentation, software and tools, parametrics, ordering information and a Getting
Started tab. The Getting Started tab provides quick-reference information applicable
to using the KITVR5510SKTEVM evaluation board, including the downloadable assets
referenced in this document.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions,
and receive input on just about any embedded design topic.
The NXP community is at http://community.nxp.com.
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KITVR5510SKTEVM Evaluation Kit User Guideline
3 Getting Ready
Working with the KITVR5510SKTEVM requires the kit contents, additional hardware and
a Windows PC workstation with installed software.
3.1 Kit contents
•Assembled and tested KITVR5510SKTEVM connected to FRDM-K82F in an antistatic
bag
•2.6 ft USB-STD A to USB-B-micro cable
•Quick Start Guide
3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when
working with this kit.
•Power supply with a range of 5.0 V to 24.0 V and current limit set initially to 100 mA
•Two power supply cables with banana connectors at one end
3.3 Windows PC workstation
This evaluation board requires a Windows PC workstation. Meeting these minimum
specifications should produce great results when working with this evaluation board.
•USB-enabled computer with Windows 7 or Windows 10
3.4 Software
Installing software is necessary to work with this evaluation board. All listed software
is available on the evaluation board's information page at http://www.nxp.com/
KITVR5510SKTEVM.
•NXP_GUI_ PR_4.1.0: software interface GUI tool to configure OTP and to generate
debug and OTP scripts
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NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
4 Getting to Know the Hardware
The KITVR5510SKTEVM evaluation board is the socket programming kit of the VR5510
family of power management ICs from NXP Semiconductors. This section describes the
kit features and provides information on the board and its components.
4.1 KITVR5510STKEVM overview
The KITVR5510SKTEVM is a development platform built around the VR5510 PMIC as
the Device Under Test (DUT). The board allows designers to evaluate various functions
of the DUT. Connectors on the board provide the capability of measuring power-related
functions such as power, efficiency, loop stability, load transients, etc. Jumpers on the
board enable the selection of various capabilities, such as I/O control and switching
regulator feedback. The EVM also allows the VR5510 to be set into Debug Mode to
facilitate the debugging of faults generated by the device.
The KITVR5510SKTEVM includes NXPs FRDM-K82F development platform board.
The FRDM-K82F attaches to the bottom of the board and serves as the communication
interface between the KITVR5510SKTEVM and GUI software on the PC.
The board contains a socket that allows for the insertion and removal of individual
VR5510 devices. This feature—in conjunction with the FRDM-K82Z—enables the One
Time Programing of the VR5510 device.
4.1.1 KITVR5510SKTEVM features
The KITVR5510SKTEVM evaluation board offers the following features:
•VR5510 debug mode support
•One Time Programming (OTP) capability for KITVR5510SKTEVM device
•Connectors for measuring:
–Loop stability
–Load transients (BUCK12 or VPRE)
–AMUX/JTAG
–Signal and power
–Efficiency
•Load terminals for VPRE, BUCKs, BOOST, LDOs, and HVLDO regulator output
•Jumper selection for:
–I/O control (RSTB, PGOOD, STANDBY, PWRON2, PSYNC, VDDIO)
–Debug mode entry/exit
–Switching regulators (BUCKx, VPRE) feedback
•Multiple test points
4.1.2 Board descriptions
The KITVR5510SKTEVM board provides connectors, jumpers, and test points for all of
the evaluation functions supported by the kit. It also contains the socket that enables One
Time Programming of the VR5510.
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NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
4.1.2.1 LEDs, switches, and sockets
Figure 1. LEDs, switches, and sockets
Label Color Name Indication
D4 Green PGOOD_G External PGOOD signal – PGOOD released
D6 Green RSTB_G External RSTB signal – RSTB released
D12 Red RSTB_R External RSTB signal – RSTB asserted low
D13 Red PGOOD_R External PGOOD signal – PGOOD asserted low
D14 Red INTB External INTB signal
D15 Red FSOB_R External FSOB signal – FSOB asserted low
D18 Green VPRE VPRE_OUT enabled
D20 Green VBST BOOST_OUT enabled
D21 Green VBAT VBAT on
D29 Green FSOB_G External FSOB signal – FSOB released
Table 1. LEDs
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NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
4.1.2.2 Connectors
Figure 2. Connectors
Figure 2 shows all of the connectors on the KITVR5510SKTEVM. Pinouts for individual
connectors are shown in the schematic.
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KITVR5510SKTEVM Evaluation Kit User Guideline
4.1.2.3 Jumpers
Figure 3 shows the location of jumpers on the KITVR5510SKTEVM board. Table 2
describes the jumper functions and settings.
Figure 3. Jumpers
Jumper Function Position Description
1 – 2 shorted VPRE
3 – 4 shorted LDO1
5 – 6 shorted LDO2
7 – 8 shorted BUCK3
J8 VDDIO selection
9 – 10 shorted
(default)
VDDIO external LDO (supplied from FRDM- K82F board )
1 – 2 shorted 5 V to debug mode
J11 Debug mode selection 2 – 3 shorted
(default)
GND to normal mode
1 – 2 shorted 7P5V generated from VBAT/VIN directly
J12 Debug mode selection 2 – 3 shorted
(default)
7P5V generated from an onboard regulator
1 – 2 shorted PWRON2 pin controlled by FRDM-K82F board
2 – 3 shorted
(default)
PWRON2 pin to GND
J13 PWRON2 I/O control
open PWRON2 pin user controlled
1 – 2 shorted PSYNC pin pulled up to VBOS
J14 PSYNC I/O control 2 – 3 shorted
(default)
PSYNC pin to GND
Table 2. Jumpers
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NXP Semiconductors UM11586
KITVR5510SKTEVM Evaluation Kit User Guideline
Jumper Function Position Description
open PSYNC controlled by FRDM-K82F board
1 – 2 shorted STANDBY pin pulled up to VPRE
2 – 3 shorted STANDBY pin to GNDJ15 STANDBY I/O control
open (default) STANDBY pin controlled by FRDM-K82F board
1 – 2 shorted BUCK1_OUT as VCOREMON input
J60 VCOREMON source
selection 2 – 3 shorted
(default)
BUCK1/BUCK2_DUAL_PHASE_OUT as VCOREMON input
1 – 2 shorted VSUP 2 as HV_HDLVO input
J70 HDLVO high-voltage
input source selection 2 – 3 shorted
(default)
VPRE_OUT as HV_HDLVO input
1 – 2 shorted
(default)
BUCK1_OUT as LV_LDLVO input
J71 HDLVO low-voltage
input source selection 2 – 3 shorted VPRE as LV_HDLVO input
1 – 2 shorted 1P8V
J72
Voltage setting for
VDDIO external
regulator (J8: 9–10)
selection
2 – 3 shorted
(default)
3P3V
1 – 2 shorted Pull up to VDDIO
J82 PGOOD pin and pull-
up source control 2 – 3 shorted
(default)
Pull up to VPRE
1 – 2 shorted Pull up to VDDIO
J83 RSTB pin and pull-up
source control 2 – 3 shorted
(default)
Pull up to VPRE
J95 Not used 1 – 2 (default open)
1 – 2 shorted
(default)
VMON1 = VPRE (3.3 V)
3 – 4 shorted
(default)
VMON2 = BUCK3 (1.1 V)
5 – 6 shorted
(default)
VMON3 = LDO2 (1.8 V)
7 – 8 shorted
(default)
VMON4 = LDO1 (1.8 V)
9 – 10 shorted VMON4 = BOOST (5 V)
J101
Regx outputs to
VMONx (divided down
to 0P8V) connection
11 – 12 shorted VMON4 = External (0.8 V)
1 – 2 shorted
(default)
Feedback from capacitor close to inductor
J102 VPRE feedback
selection 2 – 3 shorted Feedback from external source, if needed
1 – 2 shorted Feedback from the load
J103 BUCK2 feedback
selection 2 – 3 (default) Feedback from capacitor close to inductor
1 – 2 shorted Feedback from the load
J104 BUCK1 feedback
selection 2 – 3 shorted
(default)
Feedback from capacitor close to inductor
1 – 2 shorted Feedback from the load
J105 BUCK3 feedback
selection 2 – 3 shorted
(default)
Feedback from capacitor close to inductor
open (default) BUCK1/BUCK2 in Single Phase
SJ3
BUCK1/BUCK2
Multiphase
configuration shorted BUCK1/BUCK2 in Dual Phase
Table 2. Jumpers...continued
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