Panasonic 3DO FZ-1 User manual

erviceManual
•
•
u
[n]OI¾r~
DIGITAL AUDIO
A
WARNING
3D0
Interactive Multiplayer
FZ-1
This is the Service
Manual
for
the
following
area.
[Q]
...
for
Canada.
[I]
...
for
U.K.
This service information is designed for experienced repair technicians only and is not designed for use by the general public. It
does not contain warnings
or
cautions
to
advise non-technical individuals
of
potential dangers in attempting
to
service a product.
Products powered by electricity should be serviced or repaired only by experienced professional technicians. Any attempt to service
or
repair the product or products dealt
with
in
this
service
information
by anyone else could result in serious injury or death.
Panasonic®
©
1994
Matsushita Electric Industrial Co., Ltd.
All rights reserved. Unauthorized copying and
distribution
is a violation
of
law.

FZ-1
WARNING
•PRECAUTION OF LASER DIODE
[g[fil
CAUTION:
This
unit utilizes a
class
1
laser.
Invisible laser
radiation
is
emitted
from
the
optical
pickup
lens
when
the
unit
is
turned
on:
1.
Do
not
look directly
into
the
pickup
lens.
2.
Do
not
use
optical
instruments
to
look
at
the
pickup
lens.
3.
Do
not adjust
the
preset
variable
resistor
on
the
optical
pickup.
4.
Do
not
disassemble
the
optical
pickup
unit.
5.
If
the
optical
pickup
is
replaced,
use
the
manufactures
specified
replacement
pickup
only.
6.
Use
of
control,
adjustments
or
performance
of
procedures
other
than
those
specified
herein
may
result
in
hazardous
radiation
exposure.
0
11111
11111
CLASS
1
LASER
PRODUCT
LASER
KLASSE
1
•SAFETY
PRECAUTION
[g
[fil
1.
Before
servicing,
unplug
the
power
cord
to
prevent
an
electric
shock.
2.
When
replacing
parts,
use
only
manufacturer's
recommended
components
for
safety.
3.
Check
the
condition
of
the
power
cord.
Replace
if
wear
or
damage
is
evident.
4.
After
servicing,
be
sure
to
restore
the
lead
dress,
insulation
barriers,
insulation
papers,
shields,
etc.
5.
Before
returning
the
serviced
equipment
to
the
customer.
be
sure
to
make
the
following
insulation resistance
test
to
prevent
the
customer
from
being
exposed
to
a
shock
hazard.
[g
• INSULATION RESISTANCE TEST
1.
Unplug
the
power
cord
and
short
the
two
prongs
of
the
plug
with
ajumper
wire.
2.
Turn
on
the
power
switch.
DAHGER·lnv1s1blt
lasefradiationwhen
-·
AVOIOOIRECTEX·
POSURE
TO
SEAM
3.
Measure
the
resistance
value
with
ohmmeter
between
the
jumpered
AC
plug
and
each
exposed
metal
cabinet
part,
such
as
screwheads
antenna,
control
shafts,
handle
brackets,
etc.
Equipment
should
read
between
4.8
Mn
and
8.8
M!l
to
all
exposed
parts.
(Fig.
A)
Note:
Some
exposed
parts
may
be
isolated
from
the
chassis
by
design.
These
will
read
infinity.
Resistance=4.8-8.B
MQ
4.
If
the
measurement
is
outside
the
specified
limits,
there
is
a possibilty
of
a
shock
hazard.
The
equipment
should
be
repaired
and
rechecked
before
it
is
returnd
to
the
custom
LITHIUM
BATTERY
&
• CAUTION
Danger of explosion if battery is incorrectly replaced.
Replace only with the same or equivalent type recommended
by
the manufacture.
Dispose of used batteries according to the manufacture's instruction.
FUSE REPLACEMENT
&.
• CAUTION
For
continued
protection
against
risk
,
of
fire,
replace
only
with
same
fast
operating
type
3.15A,
125V
fuse.
FUSE
REPLACEMENT
&.
• CAUTION
•ATTENTION
AFIN
D'ASSURER
UNE
PROTECTION
CONTINUE
CONTRE
LES
RISOUES
D'INCENDIE
UTILISER
A
ACTION
RAPIDE
UN
FUSIBLE
DE
RECHANGE
DE
MEME
TYPE
DE
3,15A,
125V.
For
continued
protection
against
risk
of
fire,
replace
only
with
same
type
3.15A,
250V
fuse.
FZ-1

FZ-1
Warning
FOR
YOUR
SAFETY
PLEASE
READ
THE
FOLLOWING
TEXT
CAREFULLY
This appliance
is
supplied with a moulded three pin mains plug for your safety and conve-
nience.
A 3
amp
fuse
is
fitted
in
this plug.
Should the fuse need
to
be replaced please ensure that the replacement fuse has a rating of
3
amps
and that
it
is
approved
by
ASTA
or
BS!
to
BS1362.
Check for the ASTA mark
<%>
or
the
BS!
mark
Won
the body of the fuse.
Ifthe plug contains a removable fuse
cover
you must ensure that
it
is
refitted when the fuse
is
replaced.
Ifyou lose the fuse
cover
the plug must not be used until a replacement
cover
is
obtained.
A replacement fuse
cover
can be purchased from your local Panasonic Dealer.
IF
THE FITTED MOULDED PLUG
IS
UNSUITABLE FOR
THE
SOCKET OUTLET
IN
YOUR HOME THEN THE FUSE SHOULD
BE
REMOVED AND THE PLUG CUT OFF
AND DISPOSED OF SAFELY.
THERE
IS
A DANGER
OF
SEVERE ELECTRICAL
SHOCK
IF
THE CUT OFF PLUG
IS
INSERTED INTO ANY
13
AMP SOCKET.
If a new plug
is
to be fitted please observe the wiring code as shown below.
If
in
any doubt please consult a qualified electrician.
Important
The wires in this mains lead are coloured
in
accordance with the following code:
Blue: Neutral
Brown: Live
As the colours of the wires in the mains lead of this appliance may not correspond with the
coloured markings identifying the terminals
in
your plug, proceed as follows:
The wire which
is
coloured BLUE must be connected to the terminal
in
the plug which
is
marked with the letter N
or
coloured BLACK.
The wire which
is
coloured BROWN must be connected to the terminal
in
the plug which
is
marked with the letter L
or
coloured
RED.
Under no circumstances should either of these wires be connected to the earth terminal of
the three pin plug, marked with the letter E
or
the Earth Symbol
c!=-
.
•
How
to
replace
the
fuse
~
Open
the fuse compartment with a screwdriver and
replace the fuse.
This equipment
is
produced to
BSS00/1983.
The unit
is
in
the standby condition when the AC power
supply cord
is
connected.
The primary circuit
is
always "live" as long as the power
cord
is
connected to an electrical outlet.
Fuse
FZ·l
Contents
1.
System Overview
1-1
. General Description .........................................................................
1-1
1-2. Specifications...................................................................................
1-1
1-3. Location of Controls
and
Components ............................................1-2
1-4. Block Diagram .................................................................................1-4
1-5. Block Explanation ............................................................................1-6
2.
Checking Information
2-1. Handling Precautions for Traverse Deck.........................................
2-1
2-2. Disassembly
I
Reassembly .............................................................2-2
2-3. Troubleshooting Flowchart ............................................................2-16
2-4. Interconnection for Operation Check.............................................2-17
2-5. Terminal Function of IC's...............................................................2-18
2-6. Pin Configurations of
PCB
.............................................................2-28
3. Diagrams and Replacement Parts List
3-1. Wiring Connection Diagram.............................................................
3-1
3-2. Schematic Diagrams........................................................................3-2
3-3. Printed Circuit Boards ...................................................................3-10
3-4. Exploded Views .............................................................................3-12
3-5. Replacement Parts List..................................................................3-15

FZ-1
1. System Overview
1-1.
General
Description
The
FZ-1
is
a high performance audio/video entertainment and education system capable of realistic
interactive video and CD-quality audio presentations.
The
FZ-1
will play standard audio CDs at full 16-bitprecision and bandwidth like audio stereo CD player.
Also display and play Kodak Photo CD disc and Portfolio photo CD disc (Photo with CD sound).
The
FZ-1
will produce composite video, S-video and
RF
modulated composite video
([g:
NTSC ;
~:
PAL)
outputs to almost broadcast quality.
1-2.
Specifications
CPU CPU 32-bit RISC orocessor ARM60 112.5 MHz\
Memory
RAMNRAM
3
MB
(Total) 2 MB: Main-RAM
1
MB:VRAM
SRAM 32
KB
/Batterv back up\
ROM 1 MB
DSP /Diaital
Si1mal
Processor\ Oriainal 16-bitdiaital sianal orocessor
Video/Audio Video output
[g
Composite video, NTSC (RS170A standard)
S-Video, NTSC
RF
Video NTSC Channel 3
or
4 /Switch selectable\
~
Composite video, PAL
S-Video, PAL
RF
Video PAL-I, channel
21
Resolution
[g
640 IHI x 480 IV\ dots {Inside 320 x 240 dots\
~
768
{H)
x 576 {V) dots (Inside 384 x 288 dots\
Colors Max. 16.7
Million/
Std.
32K
/Pixel Clock: 12.3 MHz\
Audio Stereo 16-bit /CD sinale\ PCM ISamPlina:
44.1
kHz\
Storage CD-ROM drive Size: 4.7
and
3.1
inch (12 and 8 cm)
Double Speed CD-ROM Drive (Read Buffer:
32
KB)
Extension memorv /via ExPansion Port\
I/OPart
Control
port
Low speed 1/0: Dsub 9-pin x 1
Daisv-chain svstem
Expansion port Hiah speed 1/0: 30-Pin x 1
AV Expansion port Hiah sPeed AV-I/O /Video CD
adaptor\:
68-pin x 1
System System dimensions 284 x 268 x 88 mm (11.2 x 10.6 x 3.5 inch)
(Wx
DxH)
Weiaht 2.9 ka (6.4 lb.I
Power requirement
[g
120VAC
~
230 -240 V AC
Power consumPtion
30W
Indicator Power indicator Red-LED x 1
CD-access indicator Green-LED x 1
Temperature Qperatina
50
°F
to
86
°F
110
°c
to 30 °C)
Storage
-4
°F
to
140 °F
(-20
°C to 60
°C}
(When packed for shipment)
FMV: Full Motion Video
1-1

1-3. Location of Controls and Components
• Front View
Power switch ( 19 POWER)
(~POWER/ <9)
• Rear View
Ready indicator
(READY)
Lights up when
power is on.
Expansion Port
(EXPANSION)
Slot for peripheral devices which
utilize high speed data transfer.
19 Channel 3/4 switch
(CH SELECT)
Disk tray
Extended and retracted using
the OPEN/CLOSE button. Disk tray open/close
switch
(OPEN/CLOSE)
Controller port
(CONTROLLER)
Dedicated port for the
provided controller.
CD access indicator
(ACCESS)
Lights up when CD is being
accessed.
S-vldeo output socket
(S-VIDEO
OUT)
When using atelevision which
supports $-video, connecting a
separately sold $-video cable
results in a sharper picture.
ODO 000
When connecting an RF cable,
specifies whether to use channel 3 \i
or channel 4 as the output channel. \
Power cord
Righi/left audio output socket
(AUDIO OUT R/L)
~ There is no switch.
RF output socket (RF OUT)
When connecting with atelevision
which does not have an audio/video
jack, the provided RF cable is used.
1-2
Video output socket
(VIDEO OUT)
FZ-1
• Right Side View
AV expansion slot (AV-EXPANSION)
Dedicated slot, visible upon opening the cover, used with
separately sold Video CD adaptor.
I
/'"------""\
,------,
I
10=
01
I
I
II I I: I I
II
II I I
1'----------"
__ .,)
---
\...
Extension port (EXTENSION)
Participation by more than one player is
achieved by connecting a separately sold
controller to this port.
\
Left shift button (L)
X button (X •>
Connector
Connected to the Multiplayer
unit.
Volume (VOLUME)
Stereo Headphone Jack (PHONES)
Headphones, when used, are
connected to this port.
Used to adjust volume when
using headphones.
Play/pause button (P ~/II)
1-3

1-4.
Block
[?iagram
MAIN
LOGIC
PCB
IC
100
DA86C06020XV
CPU
A0-3I
00-31
IC
340
MASK
ROM
I024K
X
B
bit
A2-I9
00-07
VBACK
SRAMCSB
IC350
DA58257
AM2TS
SRAM
32K
X
8
bit
+5V
IC400
DABA6I62FT2E
Bock-up
Control
FZ-1
CD-ROM
Drive
L..
_____
__.BT400
(
Lithium
Battery
l
A2-I9
00-7
Address
Doto
Slow
BUS
FZ-1
Open/Close
SW
Power
SW
SW5I
Power
Supply
LD630"'633
0630
INDICATORS
CN700
Porwer
Transformer
AV EXPANSION PORT
(Video
CD
adaptor)
(
68-pin
l
AC
6
32
8
N
IC600
~
DA623827PFJ
~--------"'I
CD-ROM
Interface
14---------------------i
Gate
Array
EXPANSION
PORT
(
30-pin
l
r
:;;
0
08
D
~ci
Xio
IC120
DAC700HF1010
OR
MN7A020UDA
System
IC
MADAM
36
Address
32
Doto
IC140
MN7A021UDB
System IC CL10
32
Serio! Doto
,----------
-----
-----,
I
C300,'302,320,322
DA8I825I7JTJ
2M-bit
VRAMX4
I
I
I
I
I
I
I
I
I
I
I
I
IC3I0,3II,330,33I
I
MN4I4270SJ08
4M-bit
DRAM x
4 )
~-----L--
-
---
-----
-~-
1
-4
IC200
OA4318VSE2XO
16-bit
Audio
DAG
Buffer
IC2I0
Df-J
X200
16.9344
MHz
Memory
3M
bytes
L/R
1
C
220
Monaural
DA324DL-Ql-'-'----'--'----+--
OP-AMP
IC160
DA9103KPJ-XN
Digital
Color
Encoder
Composite
Y/C
Mute
Circuit
0260-264,
0500,
0501
Monaural
Composite
L/R
IC520
IQ
ENC-36402
[]
ENC-27454
RF
Modulator
RIGHT/LEFT AUDIO OUTPUT SOCKET
VIDEO OUTPUT SOCKET
S-VIDEO OUTPUT SOCKET
RF
MODURATED
VIDEO OUTPUT
(RF OUTPUT SOCKET)
CHANNEL
3/4
SWITCH
(IQ
only)
CONTROLLER
PORT
(9-pin Dsub)
CONTROLLER PORT
PCB
1-5

1-5. Block Explanation
CPU
CPU is ARM60. This RISC type micro processer has 32-bit address and 32-bit data path.
MADAM supplies CPU with 12.5 MHz clock.
ROM
1 MB ROM stores the system management program. The ROM is connected to Slow bus and its data is
read by MADAM and MADAM arranges 8-bit data into 32-bit word and send it to CPU.
SAAM
32 KB SRAM is connected to Slow bus. Since Lithium battery backs up SRAM while power is down,
SRAM can retain data. It may be used to back up game data, for example.
DRAM/VRAM
DRAM and VRAM is used as main memory.
VRAM is dual-port memory. This means one port is used as normal DRAM and the other one is used to read
and write data simultaneously with the former port. Therefore, it is used as Frame Buffer which is required
fast access.
MADAM
MADAM is Address Engine. It includes OMA logic, CPU control logic, bus sharing logic and Cell Engine.
Aoscillator provides MADAM with 50 MHz clock, and MADAM divides it by two, and itprovides CLIO, CPU
and CD-ROM interface with 25 MHz clock.
CLIO
CLIO is Data Engine. It includes pixel decoding logic, 16-bit Digital Signal Processer and video interface
logic. With acrystal, CLIO oscillates 24.5454 MHz ( [g) or 29.5 MHz ( ~) clock and supplies MADAM with
24.54 MHz ( [g) or 29.5 MHz (~)and supplies Digital Color Encoder with 12.27 MHz ( [g) or 14.75 MHz
(~)-
Digital Color Encoder
CLIO supplies Digital Color Encoder with RGB data and some control signals. And Digital Color Encoder
modifies them into NTSC or PAL signals. It outputs both composit signal and Y/C signal.
Audio DAC
16-bit Audio DAC converts digital audio data from CLIO into analog audio data.
CLIO sends DAC data with serial communication manner.
CD-ROM interface
CD-ROM interface Gate Array is the interface between CLIO and both internal CD-ROM drive and External
drives which are connected through Expansion Port.
1-6
FZ-1

FZ-1
2. Checking Information
2-1. Handling Precautions for Traverse Deck
The laser diode in the traverse deck (optical pickup) may break down due to potential difference caused by static
electricity
of
clothes or human body.
So,
be
careful of electrostatic breakdown during repair of the traverse deck (optical pickup).
• Handling
of
traverse
deck
(optical pickup)
1.
Do not subject the traverse deck (optical pickup)
to static electricity as it is extremely sensitive to
electrical ~hock.
2.
To prevent the breakdown
of
the laser diode, an
antistatic shorting pin is inserted into the flexible
board (FPC board).
When removing
or
connecting the short pin, finish
the job
In
as short time as possible.
3.
Take care not to apply excessive stress
to
the
flexible board (FPC board).
4. Do not
tum
the variable resistor (laser power
adjustment). It has already been adjusted.
•
Grounding
for
electrostatic
breakdown
prevention
1. Human body grounding
Use the ant~static wrist strap to discharge the
static electricity from your body.
2.
Work
table grounding
Put a conductive material (sheet) or steel sheet on
the area where the optical pickup is placed, and
ground the sheet.
Caution:
The static electricity
of
your clothes
will
not be
grounded through the wrist strap. So, take care not
to
let your clothes touch the traverse deck (optical pickup).
FPC boards
Lens (Do not touch) (Handle then carefully)
I
Traverse Deck Variable resistor Be sure to short this portion
2-1
(Do not touch) (Use the shorting pin or clip)
Wrist strap
(Anti-static bracelet)
Iron plate or some metals
to
conduct electricity
2-2. Disassembly / Reassembly
Note:
Before disassembling, be sure to perform the following procedures first.
1. Remove the CD-ROM disk
if
it is inserted
in
the CD-ROM drive.
2.
Turn the power switch off.
3.
Disconnect the
AC
power cord.
4.
Remove the optional units.
Caution:
Please follow directions carefully.
Do
not interchange screws
in
any part of the system.
Top
Case
CO-ROM
Drive
with
Shield
Panel
Figure
1
(1)
Turn this unit (FZ-1) upside down
and
place
it
on a flat surface.
(2)
Remove four screws <A>
(3
x 14
mm)
as
shown
in
Figure
1.
(3)
Turn it over again and gradually raise the
top case.
"Reassemble
in
the reverse order.
(1)
Remove four screws <B> (2.6 x 8 mm)
as
shown
in
Figure 2.
FZ-1
Figure
2
(2)
Gradually raise the front end of the CD-ROM
drive and then disconnect the flat cables from
two connectors
(CN
620,
CN
630)
as
shown
in
Figure
3.
None Prinling side
r--~--------.
I I
I I
:-'S:J:'.>,,--.....,1
~
:
I
CN630
~
I
I
C.N~
I
I CN620
I
\.._
_________
.)
Figure
3
2-2

FZ-1
<C>
Figure 4
Power
Transformer
AC
Power
Cord
/
-®'\
\
CD
I
CN1
\.
/
-..._
Figure 5
2-3
(3)
Unhook
four
hooks
<C>
as
shown
in
Figure
4.
(4)
Raise
the
CD-ROM
Drive
shield
plate.
'Reassemble
in
the
reverse
order.
(1)
After
removing
the top
case
and
the
CD-ROM
drive,
remove
two
screws
<D>
(3
x
10
mm).
[g
Then
disconnect
two
connectors
(CN
1,
CN
3)
as
shown
in
Figure
5.
(g]
Then
disconnect
a connector
(CN
1)
as
shown
in
Figure
5.
(2)
Raise
the
power
transformer
(with
the
AC
power
cord).
'Reassemble
in
the
reverse
order.
Main
PCB
OPEN/CLOSE Button
Figure
6
I
Hooks
I
\.
_________
..)
Figure 7
Shield
Plates
Figure 8
2-4
(1)
After
removing
the top
case,
the
CD-ROM
drive
and
the
power
transformer,
raise
FZ-1
the
power
button
and
the
open/close
button
as
shown
in
Figure
6.
(2)
Gently
pull
out
the
light
leading
panel
from
the
bottom
cabinet
while
pushing
two
hooks
as
shown
in
Figure
7.
(3)
Remove
all
eleven
screws
<E>
(2.6
x8
mm)
as
shown
in
Figure
8.
(4)
Carefully
raise
shield
plate.

FZ-1
<F>
Figure
9
Figure
10
FMV
Connector
P1ate
?-~
(5)
After
removing
the
top
case,
the
CD-ROM
drive
and
the
power
transformer,
remove
three
screws
<F>
(2.6
x
8
mm),
then
remove
the
AV
connector
plate
and
the
FMV-connector
plate
as
shown
in
Figure
9.
(6)
Disconnect
the
flat
cable
from
connector
(CN
541).
(7)
Gradually
raise
the
front
end
of
the
main
PCB
and
remove
it
from
bottom
cabinet
as
shown
in
Figure
1
O.
·Reassemble
in
the
reverse
order.
Controller Port PCB
Controller
Port
PCB
,-----
1
I
I
I
I
I
I
=======-I
1-------1
\._
________
J
Figure
11
CD-ROM Drive
(1)
After
removing
the
top
case,
the
CD-ROM
drive,
the
power
transformer,
and
the
main
PCB,
gradually
raise
the
Controller
Port
PCB
as
shown
in
Figure
11.
*Reassemble
in
the
reverse order.
Precaution
for
replacing
the
CD-ROM
Drive
Mechanism
When
replacing
the
Mechanism
(P/N:
LMXY0047S),
the
Solder
and
the
Lens
Cap
should
be
removed
as
shown
below.
Remove
the
Solder from
the
solder
point.
r------,
r------7
:~Solder
Point
l
I I
I
'•'
I
I
,_,
I
I I
L
______
J
: =DSolder
Point
:
¢ :
(~)
l
I I
L
______
_j
Remove
the
Lens
Cap
from
the
Optical
Pickup.
r-------1
,-------,
~\¢~
~ti
I
I
LensGap
I I I
L
_______
J
L
_______
J
2-6
FZ-1

FZ-1
• Tray
Figure 12
Tray
Figure
13
/,~ .......
/ CD Hook"
r,~j
,,:Jf' /
--- -
Figure 14
Figure 15
2-7
(1) Remove two screws <A> (3 x 6 mm),
then remove the Front Beam as shown
in Figure 12.
(2) Push the Emergency Button by using
a thin screwdriver as shown
in
Figure 13.
(3)
Draw out the Tray to limit.
(4)
Push up the hook from the reverse side
as shown
in the arrow <D of Figure 14.
(5) Pull out the Tray as shown in the
arrow
<2l of Figure 14.
caution: Don't touch the Cleaning Brush
in Figure 15.
• Tray Reassembly
Figure
16
Figure 17
• Mechanism
~--
<il>
\ I
' Hooks__,Z.,,-
.._ - I
Holder Beam
Figure 18
Figure 19
C[}.ROM Drive Cover
2-8
(1) The Tray can be fitted into the
mechanism unit as shown
in Figure 16.
(2) Gradually insert the Tray.
(1) Remove two screws <B> (3 x 6 mm),
then remove the Rear Beam as shown
in Figure 18.
(2) Remove the screw <C> (2.6 x 8 mm) in
Figure 18.
(3) Remove the Holder Beam while
pushing three Hooks as shown
in
Figure 18.
(4) Remove five screws <D> (2.6 x 8 mm),
then remove the CD-ROM Drive Unit
cover.
FZ-1

FZ-1
Figure
20
CNS
Figure
21
•
Mechanism
Reassembly
Figure
23
2-9
(5)
Disconnect the connector (CN 4) as
shown
in
Figure
20.
(6)
Turn the CD-ROM Drive Unit upside
down and remove four screws <E> (2.6
x 8 mm) as shown
in
Figure
21.
(7)
Disconnect three connectors (CN
5,
CN 7, CN
8)
as shown
in
Figure
21.
(8)
Gradually raise the PCB and then
disconnect two connectors (CN 3,
CN
6)
as shown
in
Figure 22.
(9)
Remove the PCB.
(1)
After removing the Tray, unhook
two
Hooks securing the Traverse Deck as
shown
in
Figure 23.
Figure
24
CN7
Figure
25
Figure
26
Figure
Z1
<F>
2-10
(2)
Remove the Traverse Deck.
(3)
Turn the CD-ROM Drive Unit
as
shown
in
Figure 25.
(4)
Secure the PCB with four screws <F>
(2.6 x 8 mm) as shown
in
Figure 25.
(5)
Connect the connector (CN 7) as
shown
in
Figure 25.
(6)
Turn over the CD-ROM Drive Unit
again.
(7)
Connect the connector (CN 4)
as
shown
in
Figure 26.
(8)
Connect the flat cable
to
CN 3 as
shown
in
Figure 27.
FZ-1

FZ-1
FlatCable ,,- - '-
~N8 \\
Figure 28
Figure 29
Figure 30
CNS
Figure 31
\ rt? I
/
'-- ---
r--- --)
I _fp I
I ,::jfl11 I
I --1J.lL_ I
I I
I v
.. I
==91l:
I
\. _____ .)
2-11
(9) Connect the flat cable to CN 6 as
shown in Figure 28.
(10) Fit the front end of the Traverse Deck
as shown in Figure 29.
(11) Lock the rear end of the Traverse
Deck as shown in Figure 30.
(12) Turn the CD·ROM Drive Unit.
(13) Connect the connector (CN 5) as
shown in Figure 31.
Replacing the Mechanism Base parts . .
[ Perform the following procedures in removed the Traverse Deck, as shown in Figure 24.]
• Disassembling the Load Gear ass'y and Slide Lever
Figure 32
Cut portion of !he 0-ring
Figure 33
Figure 34
2-12
(1) Remove the Loading Belt as shown in
Figure 32.
(2) Remove the 0-ring (open the cut
portion of it}, and lift the pulley to
remove.
(Replace the O-ring, if it is damaged.)
(3) While pressing the knob in direction
arrow A, as shown in Figure 34, move
the Slide Lever in direction arrow B
until to stop.
FZ-1

FZ-1
Agure 36
Slide
Lever
-2
Agure 37
(4)
Flip
the
Base
upside
down
in
state of
procedure
(3).
Unfasten
the
hook
of
Load
Gear
ass'y,
and
remove
the
Gear
ass'y.
(5)
Move
the
Slide
Lever
in
direction
arrow
A,
as
shown
in
Figure
36,
until
to
stop.
Press
down
the
latch,
and
move
the
Slide
Lever
to
stop
again.
Lift
the
Slide
Lever
to
remove.
(6)
After
removing
the
spring,
move
the
projection
of
Slide
Lever ·2
into
the
shape
section
of
Slide
Lever •
1
,
to
separate
them.
Reassemble
the
Slide Levers
in
the
reverse
order.
•
Reassembling
the
Load
Gear
ass'y
and
Slide
Lever
A
a"-
~
Agure 38
2-13
(1)
Insert projection of
Slide
Lever
into
the
shape
section
of
Base.
While
pressing
the
Knob
in
direction
arrow
A,
as
shown
in
Figure
38,
move
the
Slide
Lever
in
direction
arrow
B
until
to
stop.
Agure
39
Agure
40
•
Removing
the
OPEN
Switch
ass'y
Agure
41
2-14
(2)
While
keeping
procedure
(1),
insert
the
projection
of
Load
Gear
ass'y
into
the
hole
of
Slide
Lever
and
the
hook
into
the
portion
A,
as
shown
in
Figure
39,
then
fasten
the
hook.
(3)
Insert
the
pulley
into
the
shaft,
and
fix
it
with
an
O·ring
as
shown
in
Figure
40.
(1)
Unfasten
lead
wires
from
the
hook.
Unsolder
two
lead
wires
on
the
motor.
Remove
the
screw
<G>,
and
lift
the
OPEN
Switch
out.
•
Reassemble
in
the
reverse
order.
FZ-1

FZ-1
[g)
AC Cord
Figure 42
[g)
• AC Cord Reassembly
Figure 43
Brown
Brown
Clamps
Figure 44
2-15
(1) After cutting two cord clamps, move
rubber tube aside, and unhooking
hook of connector, disconnect AC
cable as shown in Figure 42.
(1) Connect AC cord with transformer as
shown in Figure 43.
(2) Move rubber tube so as to place
connector at
the center of the tube,
and tie tube using clamps as shown
in Figure 44, and cut needless portion
of the clamps.
2-3. Troubleshooting Flowchart
Start
END
Check Power Logic.
Check CLIO and
Video Process
Section.
Check Sound
Proces~ Section
Check CD-ROM
Drive and CD-ROM
Drive Interface.
Check Controller
Port
and MADAM.
2-16
The following main parts and portions should
be
checked:
Power Logic
IC11 T1
IC31 D1
F1 D2
SW51 (Power Switch)
CLIO and Video Section ----~
IC160, IC140
IC300,302,320,322
CN500
Sound Process Section ----~
IC200 0200
IC140 0240
0260
0270
CD-ROM Drive and CD-ROM Drive Interface
FZ-1
CD-ROM Drive---~
Mechanism CD-ROM Drive Interface
Flat
Cables 0630
CD-ROM Drive
PCB.
IC120 CN620
IC600 CN630
Controller Port and
MADAM ----
CN900, 901 IC120
CN541 IC200

FZ-1
2-4.
Interconnection of Operation Check
CN1
CN3
*1
lg!
CN660
sws,
POWER SWITCH
CO-
ROM DRIVE
EXTENSION CABLE
(12·
PIN)
IP/N DFWV95C0079)
CD
-ROM DRIVE
EXTENSION CABLE
(30·
PIN)
(P/N
DFWV95COOSO)
=-==:.---
-
----
CN640
MAIN LOGIC
BOARD
CN700
*1
[f] only
2-17
0
CD-
ROM DRIVE
AV EXPANSION SLOT
TO OPTIONAL
FMV CARTRIDGE
DISC TRAY OPEN/CLOSE SWITCH
0
2-5. Terminal Function of IC's
IC100
CPU
(P/N:
DA86C0602:
<Vl
Pin 1/0 Pin Name Comment
No.
1 1/0,
TTL
027
Data Bus 21'
2 1/0,
TTL
028
Data Bus
2'
0
3 1/0, TTL
029
Data Bus
2'"
4
1/0, TTL
030
Data Bus
2'"
5 1/0,
TTL
031 Data Bus 2'
11
6 In,
TTL
CPA
Coprocessor absent
7
Vss
8
Vdd
9 Out LOCK
Locked
Operation
10
In,
TTL
BIGEND Big Endian configuration
11
Out
CPI-
Coprocessor
Instruction
12
In,
TTL
DBE Data Bus Enable
13
Out
WORD Byte-/Word
14
In,
TTL
MCLK
Memory
Clock input
15 In,
TTL
WAJT- Wait signal Input
16
In,
TTL
1.ATEABT Late
Abort
input
17
In, TTL PROG32 32-blt Program configuration
18
In,
TTL
DATA32 32-bit data configuration
19
Out
WRITE
Read-/Write
20
Out
OPC-
Opecode fetch
21
Out
MREQ- Memory Request
22
Out
SEQ Sequential address
23 In,
TTL
ABORT
Memory
Abort
input
24 In, TTL tRQ- Interrupt Request input
25 In,
TTL
FIRQ- Fast Interrupt Request input
26 In,
TTL
RESET- Reset signal Input
27
1/0,TTL
ALE
Address Latch Enable
28
UO,
TTL
CPB Coprocessor Busy
29 1/0, TTL TRANS- Memory Translation
30
Out
A31
Address
2"
31
Out
A30 Address
2~
32
out
A29 Address
2'"
33
Out
A28 Address
2"
8
34
Out
A27 Address
2''
35
Out
A26
Address
2'
0
36
Out
A25 Address
2''
37
Out
A24 Address
2'
4
38
Out A23 Address
2''
39
Out
A22 Address
2''
40
Out
A21 Address
2''
41
Out A20 Address
2"'
FZ-1
Continued
CIC100
Pin
uo
Pin Name Comment
No.
42
Out A19
Address
21'::II
43 Out A18 Address 2
1•
44 Out A17 Address 217
45
Out
A16
Address
2'
0
46 Out A15 Address
2"
47 Out A14 Address 2
14
4B
Out A13 Address 2
1•
49 Out A12 Address 2
12
50 Out A11 Address
2"
51
Vdd
52
Vss
53 Out A10 Address 2
10
54 Out
A9
Address
'l"
55 Out
A8
Address
2°
56 Out
A7
Address
2'
57 Out
A6
Address
't'
58 Out
AS
Address
2°
59
Out
A4
Address
2'
60 Out
A3
Address 23
61
Out
A2
Address
2'
62 Out
A1
Address
2'
63
Out
AO
Address
2"
64
Vss
65 Vdd
66
In,
TTL
ABE
Address Bus Enable
67 In, TTL,
TCK
TestClock
w/pullup
68
In,
TTL,
TMS Test
Mode
Select
wioull-up
69
In,
TTL,
TRST- Test
Mode
Reset
wlouli-up
70
In,
TTL, TOI Test Data Input
w/oull-uo
71
Out TOO Test Data Output
72
UO,
TTL
DO
Data Bus
2"
73 1/0,
TTL
D1
Data Bus 2
1
74
UO,
TTL
D2 Data Bus 23
75 1/0,
TTL
03
Data Bus
2'
76 1/0,
TTL
04
Data Bus
2•
77
UO,
TTL
05
Data Bus
2°
78
UO,
TTL
06
Data Bus
2'
79 1/0,
TTL
07
Data Bus
2°
80
Vss
81
Vdd
2
-18

FZ-1
FZ-1
Continued (IC120) Continued (IC120)
Continued IC100
Pin 1/0 Pin
Name
Comment
No.
82 1/0, TTL
D8
83 1/0, TTL D9
84 1/0, TTL D10
85 1/0, TTL D11
86 1/0, TTL
D12
87 1/0, TTL D13
88 1/0,
TTL D14
89 1/0, TTL D15
90 1/0, TTL D16
91 1/O, TTL D17
92 1/O, TTL
D18
93
1/0, TTL
D19
94 1/0, TTL D20
95
1/O, TTL D21
Data Bus
96 1/0,TTL D22
Data Bus
97 1/0, TTL
D23
Data Bus
98 1/0, TTL D24 Data Bus
99 1/O, TTL D25 Data Bus
100 1/O,TTL
D26
Data Bus
1~120
Continued IIC1201
Pin 1/0 Pin Name Comment
No.
18 Out, TTL
CLC0
Device conlrol code '1'
19 Out, TTL PBCLK Conlrol portserial clock
20 Out,
TTL PBDOUT
Conlrol port serial dataoutput
21 In, TTL
PBDIN Control portserial data input
22 In, TTL, DIAGRQ- Olag.
test request input
w/null-uo
23 In,
TTL PCSC- Pixel sync signal
24 In,
TTL
DMAREQ
DMArequest
25 Vss
26 In, X25MIN Main clock input
CMOS
27 Vdd
28 In, XV25M Video clock input
CMOS
29 In, TTL
CREADY- Device control hand shake signal
30 In, TTL, RESET-
Master reset signal input
w/null-uo
31 Out, TTL PDCS3- Chip selectfor slow device 3
32
Vss
33 Out.
TTL
PDCS2- Chip
select tor slow device 2
34 Out,
TTL SRAMW-
SRAM Write signal
35 Out,
TTL SRAMR-
SRAM Read signal
36 Out,
TTL PDCSO- Chip select
tor slow device0
37 Out,
TTL PDWR- Write signal
tor slow bus
38 Out, TTL PDRD- Read signal for slow bus
Svstem IC MADAM
IP/N: DA1205FDBX0ZI
Pin 1/0 Pin Name Comment
Pin 1/0 Pin Name Comment
No.
56 Out,
XOUT
Crystal Oscillator input for X25M
s=ial
57 In, TTL
A3 CPU address 23
58
Vss
59 Vdd
60 In,
TTL
A4
CPU address 2"
61 In, TTL AS
CPU address 2'
62 In, TTL A6 CPU address
i'
63 In, TTL A7
CPU address 27
64 In,
TTL A8
CPU address i'
65 In,
TTL A9
CPU address 'l"
66 In, TTL
A1O CPU address 21"
67 In, TTL A11 CPU address 21'
68 In, TTL A12
CPU address 212
69 In, TTL
A13
CPU address 213
70 In, TTL A14
CPU address 214
71
In, TTL A15
CPU address 210
72 In, TTL A16
CPU address 2
10
73 In, TTL AO
CPU address i'
74 In, TTL
A1
CPU address 21
75 In,
TTL A17 CPU address
2"
76 In, TTL
A18
CPU address 21•
77 In, TTL A19 CPU address 21"
Pin 1/0 Pin Name Comment
No.
96 Vss
97
Vdd
98 Out, TTL
ABORT
CPU Abort signal
99 In,
TTL SEQ
CPU Sequential signal
100 In,
TTL
MREQ-
CPU Memory Request signal
101 In, TTL
READ-
CPU Read-/Wrile signal
102
Vss
103 In, TTL OPC-
CPU OPC- signal
104 Out, TTL MCLK CPU
clock
105
Vdd
106 In, TTL BYTE-
CPU Byle-/Word signal
107 Out, TTL
DBE
CPU Data Bus Enable signal
108
Vss
109 In, TTL CPI-
CPU CPI- signal
110 In,
TTL LOCK
CPU LOCK signal
111 Out,
TTL CPA
CPU CPA signal
112 Out,
TTL MCLK2
CPU clock (copy of MCLK)
113
Vss
114 1/0, TTL DO
Main system data bus
115 1/0, TTL D1 Main
system dala bus 21
116 1/O, TTL D2
Main system dala bus
117
1/O, TTL D3
Main system dala bus 2
118
Vss
39 Vss
40 1/0, TTL
PD0 Data bus '1' tor slow devices
41 1/0, TTL PD1 Data bus 21 for slow devices
42 1/0,
TTL
PD2 Data bus 'i' for slow devices
43 1/0,
TTL PD3 Data bus
2> for slow devices
44 Vdd
45 1/0,
TTL
PD4 Data bus 2" for slow devices
46 1/0, TTL PD5 Data bus 25 for slow devices
47 1/0, TTL PD6 Data bus
i' for slow devices
48 1/0,
TTL PD7 Data bus 2 for slow devices
49 Vss
50 Out, TTL ROMCS-
ROM Chip Selectsignal
51 Out. TTL SIPDEL Stalus output
52 A2 CPU address 'i'
53 Out, TTL X25M X25M clock output
54 Vss
55 In. XIN Cryslal Oscillator input for X25M
SnPrial
No.
1 Out,
TTL RA10 Right pert
memory address 210
2 Out, TTL RA9 Right pert memory address 'l9
3 Out, TTL
RA8
Right pert memory address ;ii'
4 Out, TTL
RAO
Right part memory address i'
5 Oul TTL RA7
Right pert memory address 27
6 Vss
7 Out, TTL RA1 Right part memory address 2
8 Out,
TTL RA6 Right part memory address
i'
9
Oul TTL RA2 Right part memory address 'i'
10 Out, TTL RAS Right part memory address
2•
11
Vss
12 Out, TTL
RA3 Right partmemory address 23
13 Out, TTL
RA4 Right part memory address
2"
14 Vdd
15
Oul TTL CLC2
Device control code 2'
16 Out, TTL CLC1 Device control code 21
17
Vss
78 Vss
79 Vdd
80 In, TTL A20 CPU address
2""
81 In, TTL A21 CPU address
2"'
82 In, TTL A22
CPU address 2''
83 In,
TTL A23 CPU address 2"'
84 In, TTL A24 CPU address
2''
85 In, TTL A25 CPU address
2''
86 In, TTL A26 CPU address
:12
6
87 In, TTL A27 CPU address 2"'
88 In, TTL A28 CPU address
2""
89 In, TTL A29 CPU address
2''
90 In, TTL A30 CPU address
2'°
91
In, TTL
A31 CPU address
2"
92 In, TTL TRANS-
CPU TRANS signal
93
Out, TTL CPBUSY CPU BUSY signal
94 Out, TTL CPURES- CPU Reset signal
95 In,
TTL
MIRO- lnlerrupt request input
119 1/0,
TTL
D4 Main SfSlem dala bus
120 1/0,
TTL D5
Main system dala bus 2
121
Vdd
122 1/0,
TTL
D6
Main system dala bus
123 1/0,
TTL D7
Main system dala bus 2
124
Vss
125 1/0, TTL DB Main system data bus
126 1/0, TTL 09
Main system data bus
127 1/0,
TTL D10
Main system data bus 210
128 1/0, TTL D11 Main
system dala bus 21
1
129 Vss
130 1/0, TTL D12
Main system dala bus 21
131 1/0, TTL D13 Main system data bus 21
132 1/0, TTL D14 Main system dala bus 2
14
133 1/0, TTL
D15 Main system dala bus 21
134
Vss
135 110, TTL
D16
Main system dala bus 21
2-19
2-20

FZ-1.
FZ-1
Continued (IC120} Continued (IC120) Continued (IC140) Continued (IC140}
Pin
VO
Pin Name Comment
No.
136
VO,
TTL
D17 Main system data
bus
2
17
137 Vdd
138
VO,
TTL
D18 Main system data
bus
2
18
139
VO.TTL
D19 Main system data
bus
21§
140
Vss
141
VO,
TTL
D20
Main system data bus
2'
0
142
VO,
TTL
D21
Main system data
bus
2'
1
143
VO,
TTL
D22
Main system data
bus-
:l22
144
VO,
TTL
D23
Main system data bus
2'
3
145
Vss
146
VO,
TTL D24 Main system data bus
2'
4
147
VO,
TTL
D25 Main system data bus
2'5
148 Vdd
149
VO,
TTL D26 Main system data bus
:128
150
VO,
TTL
D27 Main system data bus
2'
7
Pin 1/0 Pin Name Comment
No.
176 Out,
TTL
LA10 Left
part
memory address 2
1"
1TT Out, TTL
LA9
Left
part
memory address
'l:'
178 Out,
TTL
LAB
Leftpart
memory
address
2"
179 Out, TTL
LAO
Left part memory address
2"
180 Out,
TTL
LA7 Left
part
memory address 2
181 Out,
TTL
LA1 Leff part memory address 2
1
182
Vdd
183
Vss
184
Out, TTL LA6 Left
part
memory
address
'Z'
185 Out,
TTL
LA2
Leftpart memory address
2'
186 Out,
TTL
LAS
Left
part
memory
address
2"
187 Out, TTL
LA3
Left partmemory address 23
188 Out, TTL LA4 Leff part memoryaddress
2'
189 Out,
TTL
RPSC.
Right Part Serial Clock
for
sync.
190 Out, TTL
RSPARE
Reser,ed
signal
Pin 1/0 Pin Name Comment
No.
4 In,
TTL
so
VRAM
Serial data
bus
2°
5 In,
TTL
S3
VRAM
Serial data
bus
23
6 In,
TTL
S2
VRAM
Serial data
bus
2'
7 In,
TTL
S21
VRAM
Serial data
bus
2'
1
8 Vdd
9
Vss
10
In,
TTL
S20
VRAM
Serial data bus
2""
11
In,
TTL
S23
VRAM
Serial data bus
2'
3
12
In,
TTL
S22
VRAM
Serial data
bus""¥
13
In,
TTL
S5
VRAM
Serial data
bus
'l5
14
In,
TTL
S4
VRAM
Serial data
bus
-2'
15
In,
TTL
S7
VRAM
Serial data
bus
2
16
In,
TTL
S6
VRAM
Serial data
bus
2"
17
Vdd
18
In,
TTL
S25
VRAM
Serial data
bus
'1.2
5
19
In,
TTL
S24
VRAM
Serial data
bus
'1.2
4
Pin 1/0 Pin Name Comment
No.
45
Out,
TTL
XV25MO
Video Clock Oulput
46
Out,
TTL
FIRQ-
CPU Fast
lntemipt
signal
47
Out,
TTL
PCSC.
Video timing signal
48
Out,
TTL
DMAREQ
DMA
Requestsignal
49
1/0,TTL
CREADY·
Hand
shake
conlrol for devices
50 Out.
TTL
RESET·
System Reset signal
51
In, TTL, CLC2 Opera device conlrol signal
:22
w/oull-un
52 In, TTL, CLC1 Opera deviceconlrol signal 2
1
w/null-un
53
Vss
54 In, TTL, CLCO Opera device control signal
2'
W/oul~UD
55 1/0,
TTL
D31
Main
system
data
bus
2"
56 1/0,
TTL
D30
Main system data
bus
2
30
57
Vss
58 1/0, TTL D29 Main system data
bus 'l""
59 1/0, TTL
D28
Main system data
bus
2""
151
Vss
191
Vss
20
In,
TTL
S27
VRAM
Serial data
bus-2'
7
60
VO,
TTL
D27
Main
system
data
bus
'l"'
152
VO,
TTL
D28
Main
system data
bus
2'
8
192 Out, TTL
RRAS3-
RAS
signal for Right Bank 3
21
In,
TTL
S26
VRAM
Serial data
bus
'i"'
61
vo.m
D26
Main system data
bus
2""
153
VO,
TTL
D29
Main system data
bus
2'
9
193 Out,
TTL
RRAS2·
RAS
signal
for
Right Bank 2
22
In,
TTL
S9
VRAM
Serial data
bus 'l:' 62
Vss
154
UO,
TTL
D30
Main system data
bus
2
30
194 Out,
TTL
RRAS1·
RAS
signal
for
Right
Bank
1 23
Vss
63
VO,
TTL
D25
Main
system
data
bus
'1.2
5
155
VO,
TTL
D31 Main system data bus
:23°
1
195 Out, TTL RRASO-
RAS
signal for Right Bank o 24 X25M System clock
64
1/0,
TTL
D24
Main system data
bus
'l."
4
156
Vss
196 Out, TTL
RSC
Serial Clock
for
Right
part
VRAM
25
Vss
65 1/0,
TTL
D23
Main
system
data
bus
2"
3
157 Out,
TTL
LPSC.
Left
PartSerial Clockfor sync. 197
Vss
26
In,
TTL
S8
VRAM
Serial data
bus°¥
66
Vss
158 Out,
TTL
LSPARE
Reser,ed
signal 198 Out,
TTL
RSOEO-
SOE
signal for Right Bank O
memory
27 In,
TTL
S11
VRAM
Serial data
bus
2 67
Vdd
159 Out,
TTL
LRAS3-
RAS
signal for Left Bank 3 199 Out, TTL RSOE1-
SOE
signal
for
Right
Bank
1
memory
28
In,
TTL
S10
VRAM
Serial data
bus
2
10
68
VO.TTL
D22
Main system data
bus
2"'
160 Out,
TTL
LRAS2- RAS signal for Leff Bank 2
200
Out,
TTL
RDTOE-
DTOE
signal
for
Right partmemory
29
In,
TTL
S29
VRAM
Serial data
bus
2'9
69
vo,m
D21
Main
system
data
bus
'1.2
1
161
Vss
201
Out,
TTL
RDSF
DSF
signal for Right part
VRAM
30 In,
TTL
S28
VRAM
Serial
data
bus
2'
8 70
Vss
162 Out,
TTL
LRAS1- RAS signal for Leff Bank 1
163 Out,
TTL
LRASO- RAS signal for Leff Bank 0
201
Vdd
203
Vss
31
In,
TTL
S31
VRAM
Serial data
bus
2
31
32
In,
TTL
S30
VRAM
Serial data
bus
iJ0
71
VO,
TTL
D20
Main
system
data
bus 2""
72
VO,
TTL
D19
Main
system
data
bus
2
19
164 Vdd
204
Out, TTL
RCAS·
CAS
signal for Right part
memory
33
In,
TTL
S13
VRAM
Serial data
bus
2
13
73 1/0,
TTL
D18 Main system data bus 2
1•
165
Vss
205 Out, TTL
RWEL·
WE
signal for Right Upperbyte 34 In,
TTL
S12
VRAM
Serial data
bus
2
12
74
Vss
166 Out,
TTL
LSC
Serial Clock for Left part
VRAM
167 Out, TTL LSOEO-
SOE
signal for Leff Bank Omemory
206 Out,
TTL
RWEU·
WE
signal for Right Lower byte
207 In,
TTL
RQSF
QSF
signal
for
Right part
VRAM
35
In,
TTL
S15
VRAM
Serial data
bus
2
15
36
In,
TTL
S14
VRAM
Serial data
bus
2
14
75 1/0,
TTL
D17 Main
system
data
bus
2
1
76 1/0,
TTL
D16 Main
system
data
bus
2
1•
168 Out,
TTL
LSOE1· SOE signal for Leff Bank 1 memory 208
Vss
37
Vss
n
VO,
TTL
D15
Main system data
bus
2'°
169 Out,
TTL
LDTOE-
DTOE
signal for Leffpart memory
170 Out,
TTL
LDSF
DSF signal for Right part
VRAM
171
Out,
TTL
LCAS-
CAS
signal for Right partmemory
172
Vss
173 Out,
TTL
LWEL-
WE
signal for Right Upper byte
174 Out,
TTL
LWEU-
WE
signal for Right Lowerbyte
175
In,
TTL LQSF- QSF signal for Right
part
VRAM
IC140
Svstem
IC
CLIO (P/N:
DA1205GDBX0Z}
Pin 1/0 Pin Name Comment
No.
1 In,
TTL
S19
VRAM
Serial data bus 2
19
2 In, TTL
S18
VRAM
Serial data
bus
2
18
3 In, TTL
S1
VRAM
Serial data bus 2
1
38
In.CMOS
XV25MIN
Video
Clock input
39 Vdd
40
Vss
41
Out,
XOUT
Ctystal Oscillator Output
SOAC'!i31
42
In, special
XIN
Crystal Oscillator Input
43
Vss
44 In, TTL, POINT- Slow Bus
lntemipt
w/oull-uo
78
Vss
79
VO,
TTL
D14 Main systemdata
bus
2••
80 1/0,
TTL
D13 Main system data bus
2»
81
1/0,TTL
D12 Main
system
data bus 2
12
82
Vss
83
Vdd
84
VO,
TTL
D11
Main
system
data
bus
2
1'
2-21
2-
22

FZ-1
FZ-1
Continued
(IC14O)
Continued
(IC140) Con0nued (IC140) Continued (IC14O)
Pin
VO
Pin
Name
Comment
No.
85
VO,
TTL
010
Main system data bus 21"
86
VO,
TTL
D9 Main system data
bus
2"
87
Vss
88
VO,
TTL
08
Main
system
data
bus
'l!'
89
VO,
TTL
07
Main system data bus 2
1
90
VO,
TTL
06
Main
system
data
bus
2"
91
Vss
92
VO,
TTL
05
Main
system
data
bus
2"
93
VO,
TTL
04
Main system data
bus
2'
94
VO,
TTL
03
Main system data bus
2'
95
Vss
Pin 1/0
Pin
Name
Comment
No.
120
In,
TTL
A4
System address input
2'
oull-up
121
In,
TTL
A3
System address input
2•
oull-up
122 In,
TTL
A2
System address Input
2'
DUl~up
123
In, TTL,
SERL
Serial audio data left select
DUI1-uD
124
In, TTL,
SERR
Serial audio data right select
oull-up
125
In, TTL,
SERDAT
Serial audio data Input
cull-up
126
In, TTL, SERCLK Serial audio
clock
input
oull-uo
127
Vss
Pin
VO
Pin
Name
Comment
No.
156 Out, TTL, WDRES- Watch Dog timer reset output
ODoul
157 Vss
158 Oul,
TTL
ADO
Video
pixel data
2"
159 Out,
TTL
AD1 Video pixel data
2'
160 Out,
TTL
AD2 Video pixel data
2'
161
Oul,
TTL
AD3 Video pixel data
2'
162 Vdd
163
Vss
164 Out,
TTL
AD4 Video pixel data z'
165 Oul,
TTL
AD5
Video
pixel data 2"
166 Oul,
TTL
AD6 Video pixel data
'l!'
Pin
VO
Pin
Name
Comment
No.
197 1/0,
TTL
ADBIOO
General
purpose video
VO
1
198
UO,
TTL
ADBI01
General purposa video
UO
2
199
VO,
TTL
ADBI02
General
purpose video
UO
3
200
1/0,
TTL
ADBI03
General purpose video
UO
4
201
Vss
201
In, TTL, EXTREOR External Read OMA Request
cull-down
203 In, TTL. EXTREOW External Write OMA Request
pull-down
204
In, TTL, RPSC- Right partVRAM serial clock
pull-up
205 In, TTL, LPSC- Left partVRAM serial clock
cull-up
206 In,
TTL
S17 VRAM Serial data bus 2
1
96
VO,
TTL
02
Main system data bus
2'
97
VO,
TTL
01
Main
system
data
bus
2
1
98
Vss
128
In.CMOS,
MCLK2
MCLK2inpul
oull-uP
129
In,
TTL
XACLK
Serial audio clock input
130
Vss
167 Out,
TTL
AD7 Video pixel data 2
7
168 Vss
169 Oul,
TTL
ADS Video pixel data
2"
207 In, TTL
S16
VRAM
Serial
data bus 2
16
208
Vss
99
Vdd
100
UO,
TTL
D1
Main system data
bus
21
101
Out
TTL UNCACKR Unclechip read Acknowledge
102
0~
TTL
UNCACKW
Uncle chip Write Acknowledge
103 In, TTL, UNCREQR Uncle chip Read Request
DUlkfown
104
Vss
131
Out,
TTL
AUDByK
Serial audio bilclock
132
Out,
TTL
AUDWS
Serial audio
word
select
133
Out
TTL
AUDDAT
Serial
audio
data
oulpul
134
In, TTL, EINT- External
bus
interrupt input
1
ra
II-UP
135
In, TTL, ERDY- Expansion
bus
Ready signal
ra,11-oown
170 Out,
TTL
AD9 Video pixel data
2"
171
Out,
TTL
AD1O Video pixel data 210
172 Oul,
TTL
AD11 Video pixel data 2
173 Vss
174 Out,
TTL
AD12 Video pixel data
2'
2
175 Out,
TTL
AD13 Video pixel data 2
13
105
In,
TTL, UNCREQR Uncle chip Read Request
136
Out
TTL
ESEL- Expansion
bus
Select signal 176 Oul,
TTL
AD14 Video pixel data 2
14
DUlkfown
106
In, TTL A15 System address input
2"
oull-uo
137
Out, TTL ECMD- Expansion
bus
Command signal
138
Out
TTL
ERST- Expansion
bus
Resat signal
177 Oul,
TTL
AD15
Video
pixel data 2
15
178 Vdd
107 In, TTL A14 System address input
2"
139 Out,
TTL
EWRT- Expansion
bus
Write signal 179 Vss
llUil-uD
108
In, TTL A13 System address input 21'
oull-uo
140 Oul,
TTL
WSTR-
Expansion bus Strobe signal
141
Vdd
180 Out,
TTL
AD16
Video
pixel data 216
181
Out,
TTL
AD17
Video
pixel data 2
109
In,
TTL A12 System address input 21' 142
Vss
182 Oul,
TTL
AD18 Video pixel data 218
oull-uo
110 Vss 143
VO,
TTL
ED7 Expansion
bus
Address/Data 2
7
183 Out,
TTL
AD19 Video pixel data 21"
111
In, TTL
A11
System address input 2
11
I oul~uo
144
VO,
TTL
ED6 Expansion bus Address/Data
2"
145
VO,
TTL
EDS Expansion
bus
Address/Data 2
184 Vss
185 Oul,
TTL
AD20 Video pixel data
2'"
112 In, TTL
A1O
System address input 2
10
oull-uo
113 In, TTL A9 System address input 2
9
146
UO,
TTL ED4 Expansion
bus
Address/Data
2'
147 1/0, TTL ED3 Expansion
bus
Address/Data
2'
186 Oul,
TTL
AD21 Video pixel data
2'
1
187 Oul,
TTL
AD22 Video pixel data
2"
oull-uo
114
In,
TTL
A8
System address input
2"
oull-uo
148
UO,
TTL ED2 Expansion bus Address/Data 2
2
149
UO,
TTL
ED1 Expansion bus Address/Data 21
188 Out,
TTL
AD23 Video pixel data
2''
189 Vss
115 In, TTL A7 System address input 2
7
150 1/0,
TTL
EDO
Expansion bus Address/Data
2"
190 Out,
TTL
AMYCTL Color encoder control signal
oull-un
116 In, TTL A6 System address input
2"
oull-uo
151
Vss
152
In.CMOS
PON
Power
on
reset
input
191
Out,
TTL
TMUXSEL Color encoder control signal
192 Out, TTL BLANK-
Video
Blanking signal
117 Vss 153
In.CMOS
WDIN Walch Dog Timer C/R input 193 Out,
TTL
EXTACKR External Read Acknowledge
118 Vdd 154
In,
TTL, HSYNC-
Video
Hsync input 194 Oul,
TTL
EXTACKW External Write Acknowledge
119
In,
TTL
AS
System
address
input
2
5
I oull-uo null-uo
155 In, TTL, VSYNC- Video Vsync input
oull-up
195 Vdd
196 Vss
2-23
2-24

FZ-1
FZ-1
IC160
Video Encoder (P/N: DA9103KPJ-XN)
Pin
VO
Pin
Name
Comment
No.
Continued (IC160)
IC200
Pin
VO
Pin Name Comment
Audio
DAC
(P/N: DA4318VSE2XOl
Pin
VO
Pin Name
Comment
IC600
CD-ROM
Interface Gate Array
IP/N: DA623827PFJl
1
GND
2
Analogou1j:xJI
COMPO0
Composite
video
output
0
3
GND
4
Analogou1j:xJI
COMPO1
Composite
video
output
1
5 GND
6
Analogou1j:xJI
COUT
Chroma
signal
output
7 GND
8
Analogou1j:xJI
YOUT
Luminance signal output
9 GND
10
N/C
11
N!C
12
GND
13
TTL, Input
RO
Red pixel data input 0
14
TTL, Input
Rl
Red pixel data
inputl
15
GND
16
VAA
17 TTL, Input R2 Red pixel data input 2
18
TTL, Input
R3
Red pixel data input 3
19
TTL, Input
R4
Red pixel data input 4
20
TTL, Input
RS
Red pixel data input 5
21
GND
22
VAA
23
TTL, Input R6 Red pixel data input 6
24
TTL, Input R7 Red pixel data input 7
25
TTL, Input
GAMMA-
GAMMA
CORRECTION
26
TTL, Input YCRCB YCrCb, RGB selector
27
N!C
No.
41
TTL, Input
GS
Green pixel data input 5
42
TTL, Input G6 Green pixel data input 6
43 TTL, Input
G7
Green
pixel
data
input
7
44
GND
45 GND
46 GND
47 GND
48 TTL, Input 2XCLOCK 2x pixel clock input
49 TLL, Input CLOCK Pixel clock input
50 GND
51
VAA
52 TTL, Input RESET-
Reset
control
input
53
TLL,
lnpu1
BLANK- Composite blanking
control
54 TTL, Output
VSYNC
Vertical sync
55 TLL, Output
HSYNK
Horizontal sync
56
GND
57
VAA
58 TTL, Input SQUARE Square pixeVCCIR
601
59
TLL, Input INTERLACE lnterlace/Noninterlace
60 TLL, Input PAL PALJNTSC
61
VAA
62
Analog
irµJt FSADJUST Full-scale adjust control
63
Analogirµ,t
VREFIN Voltage reference input
64
Analogou1j:xJI
VREFOUT Voltage reference output
65
VAA
66
VAA
No.1 N/C
2 Output VREF Voltage Reference output
3
N!C
4 AVDD Analog power supply
5 AVSS Analog ground
6 Input
TST
Test pin
7
Input ZMUTE Mute
8 Input DIF0 Input format 0
9 Input DIF1 Input format 1
10
DVSS Digital ground
11
DVDD Digital power supply
12 Input LRCK
LJR
Clock pin
13
Input BICK Bit clock
14
Input SDATA
Data
input
15 Input
PD•
Reset
16
Input
XT1
Master clock input
17
Output
XTO
Crystal oscillator output
18
Input SMUTE Software mute
19 Input
DEMO
De-emphasis mode 0
20 Input DEM1 De-emphasis mode 1
21
Input CKS Clock select
22 Output DZF Zero output detect
23 Output AOUTR- R-ch Analog minus output
24 Output AOUTR+ R-ch Analog plus output
25 Output AOUTL- L-ch Analog minus output
26 Output AOUTL+ L-ch Analog plus output
Pin
VO
Pin
Name
Comment
No.
1
VO,
TTL, EXD3 Internal expansion bus (2
3)
w/Pull-uo
2
VO,
TTL, EXD4 Internal expansion bus (24)
w/Pull-uo
3
VO,
TTL, EXD5 Internal expansion bus (2
5)
w/Pull-uo
4
VO,
TTL, EXD6 Internal expansion bus
(2
6)
w/Pull-uo
5
VO,
TTL, EXD7 Internal expansion bus
(2
7)
w/Pull-uo
6
In,
TTL EXSTR- Internal Strobe signal
7
In,
TTL EXWRT- Internal Write signal
8
In,
TTL EXRST-
Internal
Reset
signal
9 Tri-out,
TTL
EXRDY- Internal Ready signal
10 Vss
11
Tri-out, TTL EXINT-
Internal
Interrupt
signal
12 In, TTL EXCMD- Internal Command signal
13 In, TTL EXSEL- Internal Selection signal
14
In,
TTL BFRST· External Reset signal
15 Out, TTL IDOUT ID output to next device
16
VO,
TTL, BFWRT- External Write signal
w/Pull-uo
17
Out,
TTL BFSEL- External Selection signal
18
In,
TTL, IDIN ID input from previous device
w/Pull-uo
19 In, TTL, BFRDY- External bus Ready input
w/Pulluo
20 Out, TTL BFCMD- External bus Command
outnut
21
Out,
TTL BFSTR- External bus Strobe output
28
TTL, Input Bo Blue pixel data input 0
29
TTL, Input
Bl
Blue pixel data input 1
27
N!C
28 N/C
22
In,
TTL, BFINT- External bus Interrupt input
w/Pull-uo
23
VO,
TTL, BFD7 External bus data 2
7
30 TTL, Input B2 Blue pixel data input 2
31
TTL, Input B3 Blue pixel data input 3
IC400
w/Pull-uo
24
VO,
TTL, BFD6 External bus data 2
6
w/Pull-uo
32 TTL, Input B4 Blue pixel data input 4
Backuo Controller
CP/N:
DABA6162FT2El
25 Vss
33
TTL, Input
BS
Blue pixel data input 5
34
TTL, Input B6 Blue pixel data input 6
35 TTL, Input B7 Blue pixel data input 7
36 TTL, Input
GO
Green pixel data input 0
Pin 1/0 Pin Name
Comment
No.
1
N!C (Not Connected)
2 Output VREF Voltage Reference Output
3
N!C
(Not Connected)
26 Vdd
27
VO,
TTL, BFDS External bus data 2
5
w/Pull-up
28 1/0, TTL, BFD4 External bus data 24
w/Pull-uo
37 TTL, Input
G1
Green pixel data input 1 4 AVDD 29
VO,
TTL, BFD3 External bus data 2
3
38 TTL, Input G2 Green pixel data input 2
39
TTL, Input
G3
Green pixel data input 3 5 AVSS
6 Input TST Test pin
w/Pull-uo
30
VO,
TTL, BFD2 External bus data 2
2
w/Pull-up
40
TTL, Input
G4
Green pixel data input 4 7 Input LRCK
LJR
Clock input
31
In,
TTL, EN7B General purpose input
w/Pull-up
8 Input BICK Serial data clock
32
In,
TTL, EN15B General purpose output
w/Pull-uo
2 - 25 2 26