Enclustra Mercury ZX5 Series User manual

Mercury ZX5 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury ZX5 SoC module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury ZX5 SoC module.
Summary
This document first gives an overview of the Mercury ZX5 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-ZX5 Mercury ZX5 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-404-002 06 16.02.2021
Approval Information Name Position Date
Written by DIUN Design Engineer 08.07.2016
Verified by GLAC Design Expert 23.08.2016
Approved by DIUN Manager, BU SP 16.02.2021
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2021 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
06 16.02.2021 DIUN Cleaned-up product variants, added information on Mercury
heatsinks, added Mercury+ ST1 to accesories section, added infor-
mation on FPGA fuses and warranty, on differential I/Os, on voltage
monitoring outputs, other style updates
05 25.07.2019 DIUN Added information on voltage monitoring, power supplies, heat sink,
Linux how-to guide, other style updates
04 21.08.2018 DIUN Minor corrections and style updates, added new article codes
03 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information
02 27.12.2016 DIUN Added tool support information and NAND flash programming in-
formation
01 24.08.2016 DIUN Version 01
D-0000-404-002 2 / 53 Version 06, 16.02.2021

Table of Contents
1 Overview 6
1.1 General ................................................... 6
1.1.1 Introduction ................................................ 6
1.1.2 Warranty .................................................. 6
1.1.3 RoHS .................................................... 6
1.1.4 DisposalandWEEE ............................................ 6
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 ElectrostaticDischarge .......................................... 7
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features................................................... 7
1.3 Deliverables ................................................ 7
1.4 Accessories................................................. 8
1.4.1 ReferenceDesign ............................................. 8
1.4.2 EnclustraBuildEnvironment ....................................... 8
1.4.3 EnclustraHeatSink ............................................ 8
1.4.4 Mercury+PE1BaseBoard ........................................ 8
1.4.5 Mercury+ST1BaseBoard ........................................ 9
1.5 XilinxToolSupport ............................................ 9
2 Module Description 10
2.1 BlockDiagram............................................... 10
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 TopandBottomViews .......................................... 14
2.4.1 TopView .................................................. 14
2.4.2 BottomView................................................ 14
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 TopAssemblyDrawing .......................................... 15
2.5.2 BottomAssemblyDrawing........................................ 15
2.6 ModuleFootprint ............................................. 16
2.7 MechanicalData.............................................. 17
2.8 ModuleConnector ............................................ 17
2.9 UserI/O................................................... 18
2.9.1 Pinout.................................................... 18
2.9.2 I/OPinExceptions............................................. 20
2.9.3 DifferentialI/Os .............................................. 21
2.9.4 I/OBanks.................................................. 21
2.9.5 VREFUsage................................................. 22
2.9.6 VCC_IOUsage ............................................... 22
2.9.7 SignalTerminations ............................................ 24
2.9.8 MultiplexedI/O(MIO)Pins........................................ 24
2.9.9 AnalogInputs ............................................... 25
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.11 Power.................................................... 26
2.11.1 PowerGenerationOverview ....................................... 26
2.11.2 PowerEnable/PowerGood........................................ 27
2.11.3 VoltageSupplyInputs........................................... 28
2.11.4 VoltageSupplyOutputs ......................................... 28
2.11.5 PowerConsumption............................................ 28
2.11.6 HeatDissipation.............................................. 29
2.11.7 VoltageMonitoring ............................................ 29
2.12 ClockGeneration ............................................. 30
2.13 Reset .................................................... 30
2.14 LEDs..................................................... 31
D-0000-404-002 3 / 53 Version 06, 16.02.2021

2.15 DDR3LSDRAM............................................... 31
2.15.1 DDR3LSDRAMType ........................................... 31
2.15.2 SignalDescription............................................. 32
2.15.3 Termination................................................. 32
2.15.4 Parameters................................................. 32
2.16 QSPIFlash ................................................. 33
2.16.1 QSPIFlashType .............................................. 33
2.16.2 SignalDescription............................................. 33
2.16.3 Configuration ............................................... 34
2.16.4 QSPIFlashCorruptionRisk........................................ 34
2.17 NANDFlash ................................................ 34
2.17.1 NANDFlashType ............................................. 34
2.17.2 SignalDescription............................................. 34
2.17.3 Parameters................................................. 35
2.18 SDCard................................................... 35
2.19 GigabitEthernet.............................................. 35
2.19.1 EthernetPHYType............................................. 35
2.19.2 SignalDescription............................................. 36
2.19.3 ExternalConnectivity ........................................... 36
2.19.4 MDIOAddress............................................... 36
2.19.5 PHYConfiguration............................................. 37
2.20 USB2.0 ................................................... 37
2.20.1 USBPHYType ............................................... 37
2.20.2 SignalDescription............................................. 37
2.21 Real-TimeClock(RTC)........................................... 37
2.21.1 RTCType .................................................. 38
2.22 SecureEEPROM .............................................. 38
2.22.1 EEPROMType ............................................... 38
3 Device Configuration 39
3.1 ConfigurationSignals........................................... 39
3.2 Pull-UpDuringConfiguration ...................................... 40
3.3 BootMode................................................. 40
3.4 JTAG..................................................... 41
3.4.1 JTAGonModuleConnector ....................................... 41
3.4.2 ExternalConnectivity ........................................... 41
3.5 QSPIBootMode.............................................. 41
3.6 SDCardBootMode............................................ 41
3.7 NANDBootMode............................................. 42
3.8 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.9 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 42
3.10 NANDFlashProgramming........................................ 43
3.11 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 I2C Communication 44
4.1 Overview .................................................. 44
4.2 SignalDescription............................................. 44
4.3 I2CAddressMap ............................................. 44
4.4 SecureEEPROM .............................................. 45
4.4.1 MemoryMap ............................................... 45
5 Operating Conditions 48
5.1 AbsoluteMaximumRatings ....................................... 48
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6 Ordering and Support 50
6.1 Ordering .................................................. 50
D-0000-404-002 4 / 53 Version 06, 16.02.2021

6.2 Support................................................... 50
D-0000-404-002 5 / 53 Version 06, 16.02.2021

1 Overview
1.1 General
1.1.1 Introduction
The Mercury ZX5 SoC module combines the Xilinx Zynq®-7015/7030 All Programmable SoC (System-on-
Chip) device with USB 2.0 On-The-Go PHY, PCIe® Gen2 ×4, Gigabit Ethernet PHY, fast DDR3L SDRAM,
NAND flash, high-speed LVDS I/O, and a real-time clock, forming a complete and powerful embedded pro-
cessing system.
The use of the Mercury ZX5 SoC module, in contrast to building a custom SoC hardware, significantly re-
duces development effort and redesign risk and improves time-to-market for the embedded system.
Together with Mercury base boards, the Mercury ZX5 SoC module allows the user to quickly build a system
prototype and start with application development.
The Enclustra Build Environment [14] is available for the Mercury ZX5 SoC module. This build system allows
the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the
desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).
It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
Warning!
Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This
operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty
product return.
1.1.3 RoHS
The Mercury ZX5 SoC module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury ZX5 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury ZX5 SoC module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury ZX5
SoC module, connecting interfaces, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
D-0000-404-002 6 / 53 Version 06, 16.02.2021

Warning!
It is possible to mount the Mercury ZX5 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
ZX5 SoC module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury ZX5 SoC module is a Class A product (as defined in IEC 61000-3-2 standard) and is not in-
tended for use in domestic environments. The product may cause electromagnetic interference, for which
appropriate measures must be taken.
1.2 Features
•Xilinx Zynq®-7015/7030 All Programmable SoC, CLG485/SBG485 package
•Dual ARM® Cortex™-A9 MPCore™with CoreSight™ and NEON™ extension
•Xilinx Artix-7/Kintex-7 28 nm FPGA fabric
•178 user I/Os
•12 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•Zynq-7015:
•146 FPGA I/Os (single-ended, differential or analog) up to 3.3 V
•Zynq-7030:
•54 FPGA I/Os (single-ended, differential or analog) up to 3.3 V
•92 FPGA I/Os (single-ended, differential or analog) up to 1.8 V
•20 MGT signals (clock and data)
•Zynq-7015: 4 MGTs @ 6.25 Gbit/sec and 2 reference input clock differential pairs
•Zynq-7030: 4 MGTs @ 6.6 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen2 ×4 (Xilinx integrated PCIe block)
•1 GB DDR3L SDRAM
•512 MB NAND flash
•64 MB quad SPI flash
•Gigabit Ethernet
•USB 2.0 On-The-Go (OTG)
•Real-time clock
•Small form factor (56 ×54 mm)
•5 to 15 V supply voltage
1.3 Deliverables
•Mercury ZX5 SoC module
•Mercury ZX5 SoC module documentation, available via download:
•Mercury ZX5 SoC Module User Manual (this document)
•Mercury ZX5 SoC Module Reference Design [2]
D-0000-404-002 7 / 53 Version 06, 16.02.2021

•Mercury ZX5 SoC Module IO Net Length Excel Sheet [3]
•Mercury ZX5 SoC Module FPGA Pinout Excel Sheet [4]
•Mercury ZX5 SoC Module User Schematics (PDF) [5]
•Mercury ZX5 SoC Module Known Issues and Changes [6]
•Mercury ZX5 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mercury ZX5 SoC Module 3D Model (PDF) [8]
•Mercury ZX5 SoC Module STEP 3D Model [9]
•Mercury Mars Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Mercury Heatsink Application Note [17]
•Enclustra Build Environment [14] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury ZX5 SoC module reference design features an example configuration for the Zynq-7000 SoC
device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from Github: https://github.com/enclustra.
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and FSBL. It downloads and compiles all required software, such as U-Boot, Linux,
and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI)
that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [15] describes in more detail how to use the EBE to customize
the provided software for the user application. The document provides information on the configuration
options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization
of device trees and integration of existing or new kernel drivers.
1.4.3 Enclustra Heat Sink
For Mercury modules an Enclustra heat sink is available for purchase along with the product. Please refer
to section 2.11.6 for further information on the available cooling options.
1.4.4 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•microSD card holder
•User EEPROM
D-0000-404-002 8 / 53 Version 06, 16.02.2021

•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin IO headers
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.4.5 Mercury+ ST1 Base Board
•168-pin Hirose FX10 module connectors (3 connectors)
•2×MIPI D-PHY connectors: CSI and CSI/DSI (requires FPGA support)
•Mini DisplayPort connector (requires FPGA support)
•HDMI connector (requires FPGA support)
•SFP+ connector
•Low-jitter clock generator
•USB 3.0 device connector
•USB 3.0 host connector
•FTDI USB 2.0 device controller with micro USB device connector (UART, SPI, I2C, JTAG)
•2×RJ45 Gigabit Ethernet connectors
•1×FMC HPC connector (note: not all pins are available)
•2×40-pin Anios pin header
•3×12-pin IO headers
•microSD card holder
•5 to 15 V DC supply voltage
•Form factor: 100 ×120 mm
Please note that the available features depend on the equipped Mercury module type.
1.5 Xilinx Tool Support
The SoC devices equipped on the Mercury ZX5 SoC module are supported by the Vivado HL WebPACK
Edition software, which is available free of charge. Please contact Xilinx for further information.
D-0000-404-002 9 / 53 Version 06, 16.02.2021

2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury ZX5 SoC module is the Xilinx Zynq-7000 SoC device. Most of its I/O
pins are connected to the Mercury module connector, making 158 regular user I/Os available to the user.
Further, four multi-gigabit transceivers with support for PCIe Gen2 ×4 are available on the module connector.
The SoC device can boot from the on-board QSPI flash, NAND flash or from an external SD card. For de-
velopment purposes, a JTAG interface is connected to Mercury module connector.
The available standard configurations include 512 MB NAND flash, a 64 MB quad SPI flash and 1 GB DDR3L
SDRAM.
Further, the module is equipped with a Gigabit Ethernet PHY and a USB 2.0 OTG PHY, making it ideal for
communication applications.
A real-time clock is available on the module and is connected to the global I2C bus.
On-board clock generation is based on a 33.33 MHz crystal oscillator.
The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
D-0000-404-002 10 / 53 Version 06, 16.02.2021

Two LEDs are connected to the SoC pins for status signaling.
2.2 Module Configuration and Product Codes
Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code SoC DDR3L SDRAM Temperature Range
ME-ZX5-15-2I-D10 XC7Z015-2CLG485I 1024 MB -40 to +85◦C
ME-ZX5-30-1I-D10 XC7Z030-1SBG485I 1024 MB -40 to +85◦C
ME-ZX5-30-3C-D10 XC7Z030-3SBG485E 1024 MB 0 to +70◦C
Table 1: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
D-0000-404-002 11 / 53 Version 06, 16.02.2021

Figure 3: Module Label
The correspondence between article number and article code is shown in Table 2. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury ZX5 SoC Module Known Issues
and Changes document [6].
D-0000-404-002 12 / 53 Version 06, 16.02.2021

Article Number Article Code
EN100640 ME-ZX5-15-2C-D10-R1
EN100641 ME-ZX5-15-2I-D10-R1
EN100642 ME-ZX5-30-1C-D10-R1
EN100643 ME-ZX5-30-1I-D10-R1
EN100873 ME-ZX5-30-2I-D10-R1
EN100981 ME-ZX5-15-2C-D10-R2
EN100982 ME-ZX5-15-2I-D10-R2
EN100983 ME-ZX5-30-1C-D10-R2
EN100984 ME-ZX5-30-1I-D10-R2
EN101173 ME-ZX5-30-3C-D10-R2
EN101485 ME-ZX5-15-2C-D10-R3
EN101486 ME-ZX5-15-2I-D10-R3
EN101487 ME-ZX5-30-1C-D10-R3
EN101488 ME-ZX5-30-1I-D10-R3
EN101489 ME-ZX5-30-3C-D10-R3
EN102231 ME-ZX5-15-2C-D10-R3.2
EN102232 ME-ZX5-15-2I-D10-R3.2
EN102233 ME-ZX5-30-1C-D10-R3.2
EN102234 ME-ZX5-30-1I-D10-R3.2
EN102235 ME-ZX5-30-3C-D10-R3.2
Table 2: Article Numbers and Article Codes
D-0000-404-002 13 / 53 Version 06, 16.02.2021

2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
D-0000-404-002 14 / 53 Version 06, 16.02.2021

2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
D-0000-404-002 15 / 53 Version 06, 16.02.2021

2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [7] and include the required information on the module sizes and holes.
The maximum component height under the module is dependent on the connector type - refer to Section
2.8 for detailed connector information.
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury ZX5 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
ZX5 SoC module.
D-0000-404-002 16 / 53 Version 06, 16.02.2021

2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mercury ZX5 SoC module. A 3D model (PDF) and a
STEP 3D model are available [8], [9].
Symbol Value
Size 56 ×54 mm
Component height top 1.8 mm
Component height bottom 1.2 mm
Weight 20 g
Table 3: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 4. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 4: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J700-1 to J700-168
•Connector B: from J701-1 to J701-168
D-0000-404-002 17 / 53 Version 06, 16.02.2021

Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury ZX5 SoC module pinout can be found in the Enclustra Mercury Master Pinout
[11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury ZX5 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B35_L15_AD12_A2_P is located on pin A2 of I/O bank 35, pair 15, it is an XADC auxiliary
analog input capable pin and it has positive polarity, when used in a differential pair.
The multi-region clock capable pins are marked with “MRCC”, while the single region clock capable pins are
marked with “SRCC” in the signal name. For details on their function and usage, please refer to the Xilinx
documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
D-0000-404-002 18 / 53 Version 06, 16.02.2021

Signal Name Signals Pairs Differential Single-ended I/O Bank
IO_B13_<...> 50 24 In/Out In/Out 13
IO_B34_<...> 48 24 In/Out In/Out 34
IO_B35_<...> 48 24 In/Out In/Out 35
Total 146 72 - - -
Table 5: User I/Os
Please note that for the 7 Series FPGAs there are restrictions on the VCCO voltage when using LVDS I/Os;
refer to Xilinx AR# 43989 for details.
DCI Resistors
On the Mercury ZX5 SoC modules equipped with the bigger SoC device, if the application requires internal
termination (DCI - Digitally Controlled Impedance) for FPGA banks 34 and 35, the user needs to mount two
resistors for each I/O bank: R301 and R302 for I/O bank 34, and R303 and R304 for I/O bank 35.
If DCI is used for banks 34 and 35, besides mounting the resistors mentioned above, it is also required to
remove the default connection for the pins used for DCI resistors connections. This means that the normal
function of these pins will no longer be available. In order to use DCI for bank 34, the I2C level shifter on
the PL side (U1600 component) must be removed, and in order to use DCI for bank 35, resistors R1600 and
R402 need to be removed.
If the same VCCIO voltage is used for banks 34 and 35, the user may activate DCI cascade option and mount
only two of the resistors, respectively remove the default connection for only two of the pins used for DCI
resistors connections.
These details are important when migrating from a Mercury ZX5 SoC module equipped with a smaller SoC
device to a module with a bigger SoC device, because on the XC7Z015 device this termination scheme is
not supported.
Figure 10 shows the DCI resistors connections and Figure 11 indicates the location of the DCI resistors on the
module PCB - upper middle part on the bottom view drawing. Please contact Enclustra support for layout
details for the components that need to be removed.
Figure 10: DCI Resistors
D-0000-404-002 19 / 53 Version 06, 16.02.2021

Figure 11: DCI Resistors - Assembly Drawing Bottom View (upper middle corner) for Revision 3 Modules
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions.
I/O Pins with Level Shifter
There are four signals on the Mercury ZX5 SoC module that are routed from the FPGA banks to the module
connector via level shifters - these are presented in Table 6.
I/O Name Module Connector Pin Description
IO_B34_U2 A-88 These pins have a level shifter from VCC_IO_B34
IO_B34_U1 A-90 to VCC_CFG_MIO
IO_B35_F1 A-92 These pins have a level shifter from VCC_IO_B35
IO_B35_F2 A-94 to VCC_CFG_MIO
Table 6: I/O Pin Exceptions - Level Shifters
The level shifters used for the I/O pins mentioned in Table 6 are NXP NTS0102 and have open-drain outputs
with built-in 10 kΩpull-ups. The maximum achievable data rate on these pins is 50 Mbit/sec.
Please note that there are limitations on the VCCO voltages when using these I/Os. The level shifter requires
the VCC_IO_B34/VCC_IO_B35 (connected to the VCCA port of NTS0102) to be less or equal to VCC_CFG_MIO
(connected to the VCCB port of NTS0102), and it requires the VCC_CFG_MIO voltage to be higher than 2.3
V. Refer to the NTS0102 device’s datasheet for details.
The level shifters on the Mercury ZX5 SoC modules revision 1 and 2 perform shifting from VCC_CFG_MIO
to VCC_IO_B34/VCC_IO_B35; for details, please refer to the Mercury ZX5 SoC Module Known Issues and
Changes document [6].
Tables 7 and 8 list the valid voltage supplies combinations for the level shifters, correlated with the revision
number.
D-0000-404-002 20 / 53 Version 06, 16.02.2021