
Page 2 Pentek Model 7642 Installation Manual
Warranty
Pentek warrants that all produ ts manufa tured by Pentek onform to published Pentek spe ifi ations and are free from defe ts in mate−
rials and workmanship for a period of one year from the date of delivery when used under normal operating onditions and within the
servi e onditions for whi h they were furnished. The obligation of Pentek arising from a warranty laim shall be limited to repairing or
at its option, repla ing without harge, any produ t that in Pentek’s sole opinion proves to be defe tive within the s ope of the warranty.
Pentek must be notified in writing of the defe t or non onformity within the warranty period and the affe ted produ t returned to Pentek
within thirty days after dis overy of su h defe t or non onformity. Buyer shall prepay shipping harges, taxes, duties and insuran e for
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another ountry.
Pentek shall have no responsibility for any defe t or damage aused by improper installation, unauthorized modifi ation, misuse, negle t,
inadequate maintenan e, or a ident, or for any produ t that has been repaired or altered by anyone other than Pentek or its authorized
representatives.
The warranty des ribed above is buyer’s sole and ex lusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek spe ifi ally dis laims fitness for a parti ular purpose. Under no ir umstan es shall Pentek be liable for any dire t, indi−
re t, spe ial, in idental, or onsequential damages, expenses, losses or delays (in luding loss of profits) based on ontra t, tort, or any
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Manual Revision History
Date Revision Comments
10/19/06 Preliminary Initial release.
2/5/07
to
9/30/08
Se t 1.15, updated Power Spe ifi ations.
or Rev C boards: Se t 2.2, added jumper blo k JB2, PCI Bus Mode. Se t 2.2.1 orre ted jumper JB1 fa tory
default settings. New Se t 7.4, added des ription of ADC to DDR Memory data pa king. Se t 1.15, orre ted
Analog Signal oupling to AC per KBCase 1320. Table 2−7 reversed differential P/N for ea h signal pair per
KBCase 1321. Se t 4.7, added Figure 4−5 timing delays. Se t 1.6, 1.15, 4.3, 6.12 added Option 101, DAC5687.
Se t 1.15, orre ted input lo k spe to ‘1 to 300 MHz’. Se t 4.4, orre ted DAC FIFO size.
or 7142 boards with PCI7142 revision date of 10/01/07 or greater:
Se t 4.5.5, 5.7.3, 5.21, 5.22, 5.23, added FPGA Load DMA des ription & registers. Se t 1.4, introdu ed new
FPGA terms: PCI FPGA (XC4VFX60) & Signal FPGA (XC4VSX55). Se t 1.12, updated baseline FPGA usage
per entages. Moved Vendor Data Sheets to separate do ument, 809.7x420. Se t 6.14.2, reversed BAR2
addresses of User In/Out FIFOs. Added Option 100, XC4VFX100 (PCI) FPGA, & Option 110, XC4VLX100 (Sig−
nal) FPGA. Se t 2.3, orre ted Pentek part # for JTAG PCB to 004.71402. Se t 2.6.1, orre ted full s ale input to
+10 dBm. Se t 1.15, hanged size spe s to PCI ard size. Se t 5.4, orre ted register BAR addresses.
11/19/08 A Manual released, Revision A
2/6/09 B Changed to Installation Manual, refer to 800.71420 for Operating Manual.
7/2/09 B.1 Se t 2.5.3, orre ted GND pins, should be B31 not B32.
Printed in the United States of Ameri a.