PerkinElmer M47-104 User manual

This is a reproduction of a library book that was digitized
by Google as part of an ongoing eort to preserve the
information in books and make it universally accessible.
https://books.google.com

Publication Number H29-650R 19
DOC
.
D
301.6
/5:
51
M91
METRIC
2 - LINE AND 8 - LINE
COMMUNICATIONS
MULTIPLEXORS
MAINTENANCE MANUAL
DEPOSITORY
DEC
17
1984
UNIVERSITY
OF
ILLINOIS
AT
URBAN
PERKIN - ELMER
Computer
Systems
Division
2 Crescent
Place
Oceanport
. N.
J. 07757
Copyright 1978 by Perkin - Elmer Corporation Printed in U.S.A. August 1981

UNIVERSITY OF
ILLINOIS LIBRARY
AT URBANA - CHAMPAIGN
BOOKSTACKS

PREFACE
This manual provides the necessary information for the user to
insta 11 and maintain
the
Perkin - Elmer 2 - Line and 8 - Line
Communications Multiplexors ( COMM MUX ) . The COMM MUX interfaces
the multiplexor bus of a Perkin - Elmer processor system with a
variety of
half
-
duplex
( HDX ) or
full
-
duplex
(
FDX
) a
synchronous
data sets or local terminals . The system conforms to the RS - 232C
transmitters / receivers interface and can be programmed
for
a
variety of baud rates and character formats .
a
2
Chapter 1 contains general description of the COMM MUX .
Chapter
contains the installation of the COMM MUX . Chapter 3
contains the COMM MUX operations
and
maintenance
information
,
including
block diagram analysis and a functional schematic
analysis .
a
The following manual provides programming information on the COMM
MUX
:
2 - Line and 8 - line communications Multiplexors Programming
Manual , Publication Number 29-654
Revision 19 provides circuit modifications and associated drawing
changes to allow odd address interleaving .
29-650 R 19 8/81
i / ii

TABLE
OF
CONTENTS
DOC
.
1201
Leo
CES
PREFACE
i/
ii
CHAPTER 1 GENERAL DESCRIPTION
1-1
1.1
INTRODUCTION .
1-1
1.2
SCOPE
1-1
1.3
SIMPLIFIED
BLOCK
DIAGRAM
.
1-1
CHAPTER 2
INSTALLATION
2-1
2.1 INTRODUCTION
2-1
2.2
178 MM ( 7 " ) BOARD CONFIGURATION
2-1
2.3
2.3.1
2.3.2
2.3.3
2.3.4
INSTALLATION
Unpacking
Location .
Interrupt Priority Back Panel Wiring
Cable Connections
2-1
2-1
2-2
2-2
2-4
O
2.4
ADJUSTMENT
2-4
.
2.5
2.5.1
? .5.2
OPTIONS
2 - Line Communications Multiplexor Options
8 - Line Communications Multiplexor Options
2-5
2-5
2-6
CHAPTER 3
OPERATION AND MAINTENANCE
3-1
3.1
INTRODUCTION
•
3-1
3.2
SCOPE
•
3-1
3.3
COMMUNICATIONS MULTIPLEXOR STATUS AND COMMAND
BYTES
3-2
3.4 BLOCK
DIAGRAM
ANALYSIS
3-7
29-650 ROO 7/78
iii

TABLE OF CONTENTS ( Continued )
3.5
3.5.1
3.5,2
3.5.3
3-11
3-11
3-12
C
2 - LINE INTERFACE FUNCTIONAL SCHEMATIC
DESCRIPTION
2 - Line Multiplexor Bus Interface
Commands
Universal Asynchronous Receiver / Transmitter
( UART ) Operation
Interrupt Circuit
Status
RS - 232C Interface (2- Line or 8 - Line )
.
3.5.4
3.5.5
3.5.6
3-15
3-17
3-18
3-18
3.6
3.6.1
3.6.2
3.6.3
3-20
3-20
3-21
.
8 - LINE INTERFACE FUNCTIONAL SCHEMATIC
DESCRIPTION
8 - Line Mulitplexor Bus Interface
Commands
Universal Asynchronous Receiver / Transmitter
( UART ) Operation
Interrupt
Circuit
Status
...
RS - 232C Interface ( 2 - Line or 8 - Line )
3.6.4
3.6.5
3.6.6
3-22
3-23
3-26
3-26
.
3.7
MNEMONICS
3-26
INDEX
INDEX
- 1
FIGURES
0
Figure
1-1
Figure
2-1
Figure
2-2
Figure
2-3
Figure
2-4
Figure
2-5
Figure
3-1
Figure
3-2
Figure
3-3
Figure 3-4
Figure
3-5
Figure 3-6
Figure
3-7
Figure
3-8
Communications Multiplexor Block Diagram
16-398
Half
Board
Adapter
.
Standard Interrupt Priority
8 Line COMM MUX Board , Top View , Front
Cable Routing Via Flat Cable Clamp
COMM MUX Switch Positions
Write / Read Line Turnaround
UART
Transmitter
Timing
UART
Receiver
Timing
2 - Line Interrupt Block Diagram
RS - 232C Interface Lines .
RS - 232C Voltage Specification
8 - Line Interrupt Block Diagram
8-
Line
Timing
Diagr.am
.
1-2
2-2
2-3
2-4
2-4
2-5
3-11
3-15
3-16
3-18
3-19
3-19
3-24
3-25
TABLES
TABLE
3-1
TABLE
3-2
TABLE 3-3
COMMUNICATIONS MULTIPLEXOR STATUS AND COMMAND
BYTES
3-2
CHARACTER
FORMAT
3-13
BAUD
RATE
SELECTICN
• 3-14
iv
29-650 RO6 5/79

TABLE OF CONTENTS ( Continued )
DRAWINGS
Functional Schematic e - Line
Assembly Drawing 8 - Line
Functional Schematic 2 - Line ( M01 )
Assembly Drawing 2 - Line ( M01 )
Cable Assembly , Common MUX
Cable Assembly , Line Common MUX Test
35-702R 12D03
35-702R 11 EO 3
35-701 MO1ROS
DOS
35-701 MOIROS
DO 3
17-46 3 MO 1R02CO3
17-514RO 1C03
.
.
29-650 R19 8/81
v / vi

CHAPTER
1
GENERAL
DESCRIPTION
1.1
INTRODUCTION
The
Perkin
-
Elmer
Communication
Multiplexors
(
COMM
MUX
)
are
available
in
two
formats
:
The
2 -
line
COMM
MUX
(
Product
Number
M47-104
)
and
the
8 -
line
COMM
MUX
(
Product
Number
M47-105
) .
The
COMM
MUX
interface
the
multiplexor
bus
of
a
Perkin
-
Elmer
processor
system
with
half
-
duplex
(
HDX
)
or
full
-
duplex
(
FDX
)
a
synchronous
da
ta
sets
or
lccal
terminals
.
The
system
conforms
to
the
RS
-
232C
interface
and
can
be
programmed
for
a
variety
of
baud
rates
and
character
formats
.
1.2
.
SCOPE
This document describes the installation and functional operation
of the COMM MUX and provides useful maintenance information for
digital
technicians who maintain these devices . A block diagram
analysis and a functional analysis of major areas
of each
COMM
MUX ( 2 - line and 8 - line ) are included .
1.3
SIMPLIFIED BLOCK DIAGRAM
Figure 1-1 shows simplified block diagram of the COMM MUX .
This figure covers the 2 - line and 8 - line COMM MUX .
29-650 RO6 5/79
1-1

2032
UART
(
19-081
)
UNIVERSAL
ASYNCHRONOUS
RECEIVER /
TRANSMITTER
ASYNCHRONOUS
DATA SET
BAUD
20 MA
( MILLIAMPERE )
CURRENT
LOOP
*
RS
-
232C
DRIVERS
/
RECEIVERS
OR
RATE
TERMINAL
GENERATOR
MULTIPLEXOR
BUS
INTERRUPT
AND
STATUS
GENERATOR
MULTIPLEXOR
BUS
ADDRESS
DECODE
AND
CONTROL
LOGIC
MODEM
COMMAND
REGISTER
*
2 -
LINE
ONLY
Figure 1-1
Communications
Multiplexor
Block
Diagram
1-2
29-600
ROO
7/78

CHAPTER
2
INSTALLATION
2.1
INTRODUCTION
a
This chapter provides the
necessary
information
for the
installation
of
two Perkin - Elmer Communications Multiplexors
( COMM MUX ) . The 2 - line COMM
MUX
(
Product
Number M47-104 )
is
contained on
178
mm
(7")
half
board
.
The
8-
line
COMM
MUX
(
Product
Number
M47-105
)
is
contained
on
a
38
1mm
x
38.1
mm
(
15
"
x
15
")
board
.
The
COMM
MUX
(2-
line
or
8-
line
)
interfaces
a
Perkin
-
Elmer
processor
system
,
via
a
multiplexor
bus
,
to
various
device
controllers
.
These
include
half
-
duplex
(
HDX
)
or
full
-
duplex
(
FDX
)
asynchronous
data sets
or
local
terminals
.
-
2.2
178 MM ( 7 " ) BOARD CONFIGURATION
and
two
178
mm
The chassis accepts the 3810 m ( 15 " ) single board
( 7 " ) half boards per chassis slot .
Two 178 mm ( 7 " ) boards ( half boards )
can be
inserted
into the
U
designated chassis slot via the 16-398 Half Board Adapter Kit .
Refer to Figure 2-1 . Depending on requirements , the half board
adapter kit can strap two active 178 mm ( 7 " ) boards or one active
and one blank 178mm ( 7 " ) board .
Wiring
does not
take
place
between
the
boards
and the
adapter
. Due to the adapter's design ,
the connectors on the board plug directly into the chassis slot
connector .
The 2 - line COMM MUX 178 mm ( 7 " ) half board may be
in
either the
1
right half or the left half position , as required . Refer to
Figure 2-1 .
be
installed
The 8 - line COMM MUX 381 mm ( 15 " ) full board may
any 1/0 slot .
in
|
2.3
INSTALLATION
2.3.1
Unpacking
no
When the COMM MUX is shipped with a system , it is installed at
the
factory
. Therefore special unpacking procedure is
required .
It
is
only
necessary
to ensure that the module is
properly seated
in
its
connector . If the module assembly is
purchased separately ,
it
should
be
unpacked carefully and
inspected for damage prior to installation .
29-650
R06
5/79
2-1

0012
200
O
HALF BOARD
HALF
BOARD
178MM
X
381
MM
( 7 " X
15
'').
178MM
X 381
MM
( 7 " X 15 '').
CABLE EXIT PATH
( TO 1/0 PANEL OR
DEVICE ) ON RIGHT
SIDE OF CHASSIS
Figure 2-1 16-398
Half
Board
Adapter
2.3.2
Location
The COM MUX , 2 - line or 8 - line , may be installed in any 1/0
slot
.
After installing
the module , remove the applicable RACKO / TACKO
strap
, as explained in the following paragraphs .
2.3.3
Interrupt Priority Back Panel Wiring
The acknowledge control
line from
the processor carries
the
interrupt
acknowledge ( ACK )
signal
. This line breaks into a
series of short lines forming the
daisy
-
chain
priority System .
The ACK
signal must pass through every controller equipped with
interrupt control circuits . Refer to figure 2-2 for the priority
order
.
2-2
29-650
RO6
5/79

Back panel wiring route for interrupt control at a given slot is :
the received acknowledge ( RACKO ) signal is input at pin 122-0 and
pin 122-1 and the transmitted acknowledge ( TACKO ) signal is
output
at
pin
222-0
and
pin
222-1
.
The
daisy
-
chain
bus
is
a
series
of
isolated
lines
which
connect
pin
222-0
and
pin
222-1
of
a
given
slot to
pin
122-0
and
pine
122-1
of
the
next
lower
slot
(
lower
priority
).
On
unequipped
interrupt
slots
,
jumpers
short
pin
122-1
to
pin
222-1
and
pin
122-0
to pin
222-0
of
the
slot
to
complete
the
bus
.
Back
panels
are
wired
with
jumpers
on
all
slots
.
Whenever
a
chassis
slot
is equipped
with
a
controller
that
has
an
interrupt
capability
,
the
jumper betwen
pin 122-9
and
pin
222-9
or
pin
122-0
and
pin
222-0
of
that
slot
must
be
removed
from
the
back
panel
.
same
As the 2 - line COMM MUX may be installed in either the Oor 1 side
of a chassis
slot
, the location determines which jumper
is
removed from the
selected
chassis slot ( i.e. , jumper 122-0 to
222-0 for the zero side or jumper 122-1 to 222-1
for
the one
side ) .
1
The 8 - line COMM MUX connects to both
the
O and side of a
chassis slot
. The jumper between pin 122-1 and pin 222-1 must be
removed from the selected chassis slot .
0302
CONNECTOR O
PROCESSOR BACK
PANEL
CONNECTOR
1
7
PROCESSOR
AND
MEMORY
222-0
6
122.1
TRACKO ) 1220
ITACKO ) 222-0
TRACKO
)
ITACKO
)
5
222-1
$
4
3
2
2220
122-1
134.0
122-0
222-0
0
2221
134-0
122.0
2220
122-1
222-1
7
5
4
de
wie
3
2
1
134.0
122
0
2220
122-1
222-1
0
EXPANSION BACK PANEL
TO NEXT
EXPANSION
Figure
2-2
Standard
Interrupt
Priority
29-650 ROO 7/78
2-3

2.3.4
Cable Connections
A 2 - line , half board ,
COMM
MUX
has
one 17-463 ribbon cable
connected between the connector at the edge of the board and the
cable entry
panel .
An 8 - line , full board , COMM MUX can have up to four 17-463 ribbon
cables connected between the four connectors at the edge
of
the
board and the cable entry panel
.
Refer
to
Figure 2-3 .
2034
8 LINE COMM . MUX BOARD , TOP VIEW , FRONT
0 CONN 5 CONN 4 CONN 3
CONN
20
v
v
v v
vv
v
v
LINE
6
7 4
52
3
01
Figure 2-3 8
Line
CCMM
MUX
Board ,
Top
View ,
Front
The
cables
are
routed
from
the
board
connectors
through
a
flat
cable
clamp
,
secured
to
a
bracket
(
14-531
)
on
the
left
side
of
the
mounted
chassis
(
looking
from
the
front
),
to
the
cable
entry
panel
.
Refer
to
Figure
2-4
.
2033
BRACKET
14-531
FLAT
CABLE
CLAMP
TO
CABLE
ENTRY
PANEL
Figure
2-4
Cable
Routing
via
Flat
Cable
Clamp
2.4
ADJUSTMENT
An
oscillator
and
a
strap
option
select
the
baud
rate
.
This
procedure
is described
in
Section
2.5
.
This
adjustment
is
preset
at
the
factory
.
The
COMM
MUX
is
normally
strapped
for 300
/
1200
/
7,200
/
19,200
baud
rate
,
FDX
Operation
.
the
preferred
address
for the
2
line
COMM
MIX
is
X'10
' -
X'13
'(
the
least
significant
address
switch
must
be
set
to
one
of
the
following
boundaries
:
X'0
' ,
X'4
' ,
X'8
' ,
X'C
' ) ,
and
preferred
address
for
the
8
line
COMM
MUX
is
X'10
' -
X'1F
' .
Refer
to
Figure
2-5
.
2-4
29-650
R18
3/81

2035
2 LINE
8
LINE
LSB
(
LOC
A22
)
MSB
(
LOC
A75
)
MSB
E
10/2
E2
Ella
C
4.
с
4.
с
4
6
6
A
6
8
8 8
x'10 ' - x'13 '
FOUR CONTIGUOUS ADDRESSES
X'10
' - x ' 1F '
SIXTEEN
CONTIGUOUS
ADDRESSES
Figure
2-5
COMM MUX Switch Positions
2.5 OPTIONS
2.5.1
2 - Line communications Multiplexor Options
straps
Baud
Rate To
select
a
group
of
four
baud
rates
, connect
as
indicated
( i.e.
,
strap
J6
to
J9
and
J8
to
J9
) .
Baud
Rates
50
,
110
,
1800
,
2400
Channel
75
,
134.5
2000
,
3600
150
,
600
4800
,
9600
300 , 1200
7200 , 19200
1
J6
to
J9
J8
to
J9
J6
open
J8
to J9
J6 to J9
J8
open
J6
open
J8
open
0
J5 to 19
37 to J9
J5
open
J7
to
19
J5 to J9
J7
open
J5
open
J7
open
Half
/
Full
Duplex
as
required
,
to select half of full duplex
connect
straps
Channel
Full
Duplex
In
to
I3
I2
to
13
Half Duplex
I1
open
12
open
o
Address
Interleaving -
If
both
channels
are
strapped
for
half
duplex
,
the
board
can
be
strapped
to
respond
to
only
even
addresses
or
only odd
addresses
.
Το
strap
for
even
addresses
connect
K3
to
K2
.
To
strap
for
odd
addresses
connect
K3
to
K1
.
No
strap
is
required
if
address
interleaving
is
not
desired
.
29-650
RO3
5/79
2-5

To select RS - 232C
Channel
Function
o
1
TRANSMIT DATA
RQ2S
RING
RING
DATA SET READY
RECEIVE DATA
A3
to
4
A5
to
A7
C6
to
08
D4
to D5
E4
to
E5
F 2
to
F3
E2
E 3
E7
E8
E9
E6
OPEN
C5
07
06
F1
A6
A 2
A1
E7
to
E9
E8
to
E9
E2
to
E3
C5
to
C6
07
CS
OPEN
B3 to B4
B5 to B7
C2 to 04
D1 to D2
G1 to G3
F5 to F6
E 1
E3
H1
H2
D3
G2
CPEN
D3
F4
C1
C3
B6
B1
B2
H1 to H3
H2 to H3
E1 to E3
C1 to C2
C3
C4 OPEN
DSR
CAR
CTS
RNG
To select
20
ma
current
loop
Channel
Function
0
ہے
A6 to A7
A2 to A3
A 1 to A4
07 to D5
c7 to CO
F1 to F2
F2 to F3
E6 to F3
A 5
E5
OPEN
CS
D4
E7 to E9
E8 to E9
E2 to E3
04 to 56
TRANSMIT DATA ( + )
TRANSMIT DATA ( - )
TRANSMIT DATA ( - )
DUO
DUO
RECEIVE DATA
(+)
RECEIVE DATA ( + )
RECEIVE DATA ( + )
B6 to B7
B2 to B3
B1 to B4
DO
to D2
C3 to C2
F4 to F5
F5 to G1
F6 to
G2
B5
G3 OPEN
C4
D1
H1
to
H3
H2 to H3
E1 to E3
01 to D3
Disable DSR
Disable CAR
Di sable CTS
BAFL1
( if
required
)
2.5.2
8 - Line Communications
Multiplexor
Options
of four baud
Baud Rate - To select a group
applicable switches as follows :
rates ,
set
the
2-6 29-650
R18 3/81

Baud
Rates
50
,
110
,
1800
,
2400
75 , 134.5 ,
2000 , 3600
150 , 500 ,
4800 , 9600
300
,
1200
,
7200
,
19200
Channel
Switch
0
هه
2 .
3
A37-5
A97-7
A97-6
A97-8
A97-1
A97-3
A97-2
A97-4
A 16 4-5
A 164-7
A 164-6
A 164-8
A 154-1
A
164-3
A
164-2
A 164-4
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
OFE
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
4
5
6
7
Half / full duplex - To select half
duplex
( H 2x )
channel
, set the appropriate switch to the
follows :
on
ON
a specific
position
as
ܚ
Channel
0
2
4
567
Switch
A 67
7
5
3
2
4
6
8
set
status
,
set
the
indicated
To disable the following
data
switch to the ON position .
ES - 2320
STATUS
ܚ
o
12
4
5
6
7
DSR
A
160-3
A
150-5
A 122-1 A 122-2 A8 2-2
A8
2-5
A
25-1
A 25-6
CAR
A
160-1
A 160-6 A
122-5
A
122-6
A82-1
A 82-6
A 25-4 A 25-5
CTS
A
160-4
A
160-8
A 122-3
A 122-4 A8 2-3
A
82-7
A
25-2
A 25-8
ANG
A
160-2
A 160-7 A 122-7
A 122-8
A 82-4
A
82-8
A 25-3
A 25-7
Address
Interleaving
To
conserve
address
space
,
the
COMM
MUX
may
be
strapped
for
address
interleaving
.
If
all
8
channels
are
strapped
for
half
duplex
,
the
board
can
be
strapped
to
respond
to
only
even
addresses
or
only
odd
addresses
.
To
strap
for
even
addresses
coniect
1
to
B
and
X
to
Y.
To
strap for
odd
addresses
connect
9
to
A
and
X
to
Z.
No
strap
is
required
on
1 ,
A
or
strar
X
to
Y
if
address
interleaving
is
not
desired
.
B,
29-650
R19
8/81
2-772-8

CHAPTER
3
OPERATIONS
AND
MAINTENANCE
3.1
INTRODUCTICN
a
OI
The
COMM MUX
interfaces
the
multiplexor
bus
of
a
Perkin
- Elmer
processor
system
with
variety
of half
- duplex
( HDX
)
full
- duplex
( FDX
)
asynchronous
data
sets
or
local
terminals
.
The
system
conforms
to
the
RS
- 232C
inte
face
and
can
be
programmed
for
a
variety
of
baud
rates
and
character
formats
.
It
can
also
operate
in
a
20
milliampere
current
loop
( 2 - line
only
) .
Data transfers between the data set and COMM MUX are bit serial
at
a baud
rate
selected under program control . The COMM MUX
contain circuits to generate and
detect
the control signals
required to set up , take down , supervise the data communications
channel , and provide proper status and interrupt information to
the
processor
.
х
The 2 - line COMM MUX is contained on a 178mm x 381 mm ( 7 "
15
")
board
.
The
8-
line
COMM
MUX
is
contained
on
a
381mm
x
381
mm
(
15
"
x
15
")
board
.
The interface operation of the 2 - line and the 8 - line COMM MUX are
similar ; therefore , the block
diagram
and
its
explanation
references both multiplexors .
The logical functions of the 2 - line and the 8 - line COMM MUX
are
different
.
Therefore
,
their
functional
schematics
are
explained
in
sefarate
sections
of
this
chapter
.
3.2
SCOPE
This chapter covers the
normal
a synchronous operation of the
system . specific communication techniques are not described
because
the
system
is
transparent
ot valid
characters
passing
through it .
29-65C R06 5/79
3-1