Philips SA7016 User manual



SA7016
1.3GHz low voltage fractional-N
synthesizer
Product specification
Supersedes data of 1999 Apr 20 1999 Nov 04
INTEGRATED CIRCUITS

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
2
1999 Nov 04 853–2160 22634
GENERAL DESCRIPTION
The SA7016 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 1.3 GHz.
The synthesizer has fully programmable main and reference
dividers. All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. VDDCP must be greater than or equal toVDD.
The charge pump current (gain) is set by an external resistance at
the RSET pin. Only passive loop filters could be used; the charge
pump operates within a wide voltage compliance range to provide a
wider tuning range.
FEATURES
•Low phase noise
•Low power
•Fully programmable main divider
•Internal fractional spurious compensation
•Hardware and software power down
•Split supply for VDD and VDDCP
SR01505
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
LOCK
TEST
VDD
GND
RFin+
RFin–
GNDCP
PHP
PON
STROBE
DATA
CLOCK
REFin+
REFin–
RSET
VDDCP
Figure 1. Pin Configuration
APPLICATIONS
•350–1300 MHz wireless equipment
•Cellular phones
•Portable battery-powered radio equipment.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDD Supply voltage 2.7 – 5.5 V
VDDCP Analog supply voltage VDDCP ≥VDD 2.7 – 5.5 V
IDDCP+IDD Total supply current – 6.2 7.3 mA
IDDCP+IDD Total supply current in power-down mode – 1 – µA
fVCO Input frequency 350 – 1300 MHz
fREF Crystal reference input frequency 5 – 40 MHz
fPC Maximum phase comparator frequency – 4 MHz
Tamb Operating ambient temperature –40 – +85 °C
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TYPE
NUMBER
NAME DESCRIPTION VERSION
SA7016DH TSSOP16 Plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403–1

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 3
SR01506
CLOCK
DATA
STROBE
RFin+
RFin–
REFin+
REFin–
TEST
LOAD SIGNALS
ADDRESS DECODER
2–BIT SHIFT
REGISTER 22–BIT SHIFT
REGISTER
CONTROL
LATCH
LATCH
MAIN DIVIDER
REFERENCE
DIVIDER
LATCH
AMP
11
12
6
5
15
14
13
2
PHASE
DETECTOR
COMP
PUMP
BIAS
PUMP
CURRENT
SETTING
GND
4
7
3
GNDCP
VDD
RSET
VDDCP
PHP
LOCK
10
9
8
1
PON
16
Figure 2. Block Diagram
PINNING
SYMBOL PIN DESCRIPTION
LOCK 1Lock detect output
TEST 2Test (should be either grounded or
connected to VDD)
VDD 3Digital supply
GND 4Digital ground
RFin+ 5RF input to main divider
RFin– 6RF input to main divider
GNDCP 7Charge pump ground
PHP 8Main normal chargepump
VDDCP 9Charge pump supply voltage
RSET 10 External resistor from this pin to ground
sets the chargepump current
REFin– 11 Reference input
REFin+ 12 Reference input
CLOCK 13 Programming bus clock input
DATA 14 Programming bus data input
STROBE 15 Programming bus enable input
PON 16 Power down control

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 4
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD Digital supply voltage –0.3 +5.5 V
VDDCP Analog supply voltage –0.3 +5.5 V
∆VDDCP–VDD Difference in voltage between VDDCP and VDD (VDDCP ≥VDD) –0.3 +2.8 V
VnVoltage at pins 1, 2, 5, 6, 11 to 16 –0.3 VDD + 0.3 V
V1Voltage at pin 8, 9 –0.3 VDDCP+ 0.3 V
∆VGND Difference in voltage between GNDCP and GND (these pins should
be connected together) –0.3 +0.3 V
Tstg Storage temperature –55 +125 _C
Tamb Operating ambient temperature –40 +85 _C
TjMaximum junction temperature 150 _C
Handling
Inputs and outputs are protected against electrostatic discharge in
normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
Rth j–a Thermal resistance from junction to ambient in free air 120 K/W

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 5
CHARACTERISTICS
VDDCP = VDD = +3.0V,Tamb = +25°C;unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply; pins 3, 9
VDD Digital supply voltage 2.7 – 5.5 V
VDDCP Analog supply voltage VDDCP = VDD 2.7 – 5.5 V
IDDTotal Synthesizer operational total supply current VDD = +3.0V – 6.2 7.3 mA
IStandby Total supply current in power-down mode logic levels 0 or VDD – 1 TBD µA
RFin main divider input; pins 5, 6
fVCO VCO input frequency 350 – 1300 MHz
VRFin(rms) AC-coupled input signal level Rin (external) = Rs= 50Ω;
single-ended drive;
max. limit is indicative
@ 500 to 1300 MHz
–18 – 0 dBm
ZIRFin Input impedance (real part) fVCO = 1.2 GHz – 625 – Ω
CIRFin Typical pin input capacitance fVCO = 1.2 GHz – 1.0 – pF
Nmain Main divider ratio 512 – 65535
fPCmax Maximum loop comparison frequency indicative, not tested – – 4 MHz
Reference divider input; pins 11, 12
fREFin Input frequency range from TCXO 5 – 40 MHz
VRFin AC-coupled input signal level single-ended drive;
max. limit is indicative 360 – 1300 mVPP
ZREFin Input impedance (real part) fREF = 20 MHz – 10 – kΩ
CREFin Typical pin input capacitance fREF = 20 MHz – 1.0 – pF
RREF Reference division ratio 4 – 1023
Charge pump current setting resistor input; pin 10
RSET External resistor from pin to ground 6 7.5 15 kΩ
VSET Regulated voltage at pin RSET=7.5 kΩ– 1.25 – V
Charge pump outputs (including fractional compensation pump); pin 8; RSET =7.5kΩ, FC=80
ICP Charge pump current ratio to ISET1Current gain IPH/ISET –15 +15 %
IMATCH Sink-to-source current matching VPH=1/2 VDDCP. –10 +10 %
IZOUT Output current variation versus VPH2VPH in compliance range –10 +10 %
ILPH Charge pump off leakage current VPH=1/2 VCC –10 +10 nA
VPH Charge pump voltage compliance 0.7 – VDDCP–0.8 V

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 6
SYMBOL UNITMAX.TYP.MIN.CONDITIONSPARAMETER
Phase noise (RSET = 7.5 kΩ, CP=00)
L
Synthesizer’s contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset. GSM
fREF = 13MHz, TCXO,
fCOMP = 1MHz
indicative, not tested
– –90 – dBc/Hz
L
(f) Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset. TDMA
fREF = 19.44MHz, TCXO,
fCOMP = 240kHz
indicative, not tested
– –85 – dBc/Hz
Interface logic input signal levels; pins 13, 14, 15, 16
VIH HIGH level input voltage 0.7*VDD – VDD+0.3 V
VIL LOW level input voltage –0.3 – 0.3*VDD V
ILEAK Input leakage current logic 1 or logic 0 –0.5 – +0.5 µA
Lock detect output signal (in push/pull mode); pin 1
VOL LOW level output voltage Isink=2mA – – 0.4 V
VOH HIGH level output voltage Isource=–2mA VDD–0.4 – – V
NOTES:
1. ISET = VSET
RSET bias current for charge pumps.
2. The relative output current variation is defined as:
DIOUT
IOUT
+2.(I2–I1)
I(I2)I1)I ; with V1+0.7V, V2+VDDCP –0.8V (See Figure 3.)
I2
I1
I2
I1
V1V2
CURRENT
VPH
SR00602
IZOUT
Figure 3. Relative Output Current Variation

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 7
FUNCTIONAL DESCRIPTION
Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18 dBm to
0 dBm, and at frequencies as high as 1.3 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65536.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo Q set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1 to N + 1, the average division ratio over Q main divider cycles
(either 5 or 8) will be
Nfrac +N)NF
Q
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 4) determines which of the 5
output pulses are selected as the main (auxiliary) phase detector
input.
Phase detector (see Figure 5)
The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Charge Pump table). The dead
zone (caused by finite time taken to switch the current sources on or
off) is cancelled by forcing the pumps ON for a minimum time at
every cycle (backlash time) providing improved linearity.
SR01415
DIVIDE BY R /2 /2 /2 /2
REFERENCE
INPUT
SM=”000”
SM=”001”
SM=”010”
SM=”011”
SM=”100”
SA=”100”
SA=”011”
SA=”010”
SA=”001”
SA=”000”
TO
MAIN
PHASE
DETECTOR
TO
AUXILIARY
PHASE
DETECTOR
Figure 4. Reference Divider

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 8
SR02103
R
X
P
N
REF DIVIDER
AUX/MAIN
DIVIDER
DQ
CLK
“1”
R
DR
CLK
“1”
XQN
P
τ
VCC
IPH
GND
P–TYPE
CHARGE PUMP
N–TYPE
CHARGE PUMP
R
fREF
fREF
IPH
τ
τ
Figure 5. Phase Detector Structure with Timing

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 9
Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin RSET in conjunction with bits CP0,
CP1 in the B-word (see table of charge pump ratios). The fractional
compensation is derived from the current at RSET, the contents of
the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.
Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If ICOMP is the
compensation current and IPUMP is the pump current, then for each
charge pump:
IPUMP_TOTAL = IPUMP + ICOMP.
The compensation is done by sourcing a small current, ICOMP, see
Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, RSET, programming or speed-up operation.
For a given charge pump,
ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD
FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and
80 for FMOD = 0 (modulo 8).
SR01416
REFERENCE R
MAIN M
DIVIDE RATIO
DETECTOR
OUTPUT
ACCUMULATOR
FRACTIONAL
COMPENSATION
CURRENT
OUTPUT ON
PUMP
N N N+1 N N+1
241
30
PULSE
WIDTH
MODULATION
PULSE LEVEL
MODULATION
mA
µA
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 6. Waveforms for NF = 2 Modulo 5 →fraction = 2/5
SR01682
fRF
1930.140 MHz MAIN DIVIDER N = 8042 FRACTIONAL ACCUMULATOR
fREF
240 kHz
240.016 kHz ICOMP
IPUMP LOOP FILTER
& VCO
FMOD
NF
Figure 7. Current Injection Concept

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 10
Charge pump currents
CP0 IPHP IPHP–SU
0 3xISET 15xlSET
1 1xlSET 5xlSET
NOTES:
1. ISET=VSET/RSET: bias current for charge pumps.
2. IPHP–SU is the total current at pin PHP during speed up condition.
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than 1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
‘0’) is indicated when both counters are powered down.
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 11
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified.
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Serial programming clock; CLK
trInput rise time – 10 40 ns
tfInput fall time – 10 40 ns
Tcy Clock period 100 – – ns
Enable programming; STROBE
tSTART Delay to rising clock edge 40 – – ns
tWMinimum inactive pulse width 1/fCOMP – – ns
tSU;E Enable set-up time to next clock edge 20 – – ns
Register serial input data; DATA
tSU;DAT Input data to clock set-up time 20 – – ns
tHD;DAT Input data to clock hold time 20 – – ns
Application information
SR01417
CLK
DATA
STROBE
ADDRESS LSB
tSU;DAT tHD;DAT tr
tw
tftSU;E
tSTART
Tcy
MSB
Figure 8. Serial Bus Timing Diagram

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 12
Data format
Table 1. Format of programmed data
LAST IN MSB SERIAL PROGRAMMING FORMAT FIRST IN LSB
p23 p22 p21 p20 ../.. ../.. p1 p0
Table 2. A word, length 24 bits
LAST IN MSB LSB FIRST IN
Address fmod Fractional-N Main Divider ratio Spare
0 0 FM NF2 NF1 NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 SP1 SP2
Default: 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
A word select Fixed to 00.
Fractional Modulus select FM 0 = modulo 8, 1 = modulo 5.
Fractional-N Increment NF2..0 Fractional N Increment values 000 to 111.
N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Table 3. B word, length 24 bits
Address REFERENCE DIVIDER LOCK PD CP FRACTIONAL COMPENSATION DAC SPARE
0 1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LO MAIN CP0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 SP3
Default: 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0
B word select Fixed to 01
R-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration.
Charge pump current
Ratio CP0: Charge pump current ratio, see table of charge pump currents.
Lock detect output L0
0 Main lock detect signal present at the LOCK pin (push/pull).
1 Main lock detect signal present at the LOCK pin (open drain).
When main loop is in power down mode, the lock indicator is low.
Power down Main = 1: power to main divider, reference divider, main charge pumps, Main = 0 to power down.
Fractional Compensation FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 4. D word, length 24 bits
Address SYNTHESIZER TEST
BITS SYNTHESIZER TEST BITS
1 1 0 – – – – – Tspu – – – – – – – – – – – – – – –
Default: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Tspu: Speed up = 1 Forces the main charge pumps in speed-up mode all the time.
NOTE: All test bits must be set to 0 for normal operation.

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 13
SR01911
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
800
600
400
200
0
–200
–400
–600
–800
Icp (uA)
COMPLIANCE VOLTAGE (V)
ISET = 206.67 mA
ISET = 165.33 mA
ISET = 103.33 mA
ISET = 51.67 mA
ISET = 51.67 mA
ISET = 103.33 mA
ISET = 165.33 mA
ISET = 206.67 mA
Figure 9. Php Charge Pump Output vs. ISET
(CP = 0, TEMP = 25_C)
SR01912
600
400
200
0
–200
–400
–6000 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
COMPLIANCE VOLTAGE (V)
Icp (uA)
TEMP = 85°C
TEMP = 25°C
TEMP = –40°C
Vdd = 3.0 V
ISET = 165.33 µA
Figure 10. Php Charge Pump Output vs. Temperature
(CP = 0; VDD = 3.0 V; ISET = 165.33 mA)
SR01913
Icp (uA)
–250
250
200
150
100
50
0
–50
–100
–150
–200
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
COMPLIANCE VOLTAGE (V)
ISET = 206.67 mA
ISET = 165.33 mA
ISET = 103.33 mA
ISET = 51.67 mA
ISET = 51.67 mA
ISET = 103.33 mA
ISET = 165.33 mA
ISET = 206.67 mA
Figure 11. Php Charge Pump Output vs. ISET
(CP = 1; TEMP = 25_C)
SR01914
–200
Icp (uA)
200
150
100
50
0
–50
–100
–150
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
COMPLIANCE VOLTAGE (V)
TEMP = 85°C
TEMP = 25°C
TEMP = –40°C
Vdd = 3.0 V
ISET = 165.33 µA
Figure 12. Php Charge Pump Output vs. Temperature
(CP = 1; VDD = 3.0 V; ISET = 165.33 mA)
SR01915
–3500
Icp (uA)
–2500
–1500
–500
0
500
1500
2500
3500
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
COMPLIANCE VOLTAGE (V)
ISET = 206.67 mA
ISET = 165.33 mA
ISET = 103.33 mA
ISET = 51.67 mA
ISET = 51.67 mA
ISET = 103.33 mA
ISET = 165.33 mA
ISET = 206.67 mA
Figure 13. Php–su Charge Pump Output vs. ISET
(CP = 0; TEMP = 25_C)
SR01916
3000
Icp (uA)
2000
1000
0
–1000
–2000
–3000 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
COMPLIANCE VOLTAGE (V)
TEMP = 85_C
TEMP = 25_C
TEMP = –40_C
Figure 14. Php–su Charge Pump Output vs. Temperature
(CP = 0; VDD = 3.0 V; ISET = 165.33 mA)

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 14
ISET = 165.33 mA
ISET = 206.67 mA
SR01917
Icp (uA)
ISET = 206.67 mA
ISET = 165.33 mA
ISET = 103.33 mA
ISET = 51.67 mA
ISET = 51.67 mA
ISET = 103.33 mA
1500
1000
500
0
–500
–1000
–1500 0 0.25 0.5 0.75 1 1.51.25 1.75 2 2.25 2.5 2.75 3
COMPLIANCE VOLTAGE (V)
Figure 15. Php–su Charge Pump Output vs. ISET
(CP = 1; TEMP = 25_C)
SR01918
–1000
Icp (uA)
1000
800
600
400
200
0
–200
–400
–600
–800
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
COMPLIANCE VOLTAGE (V)
TEMP = 85_C
TEMP = 25_C
TEMP = –40_C
Figure 16. Php–su Charge Pump Output vs. Temperature
(CP = 1; VDD = 3.0 V; ISET = 165.33 mA)
SR01929
–40
MINIMUM SIGNAL INPUT LEVEL (dBm)
VDD = 5.50 V
VDD = 3.75 V
VDD = 3.00 V
VDD = 2.70 V
–35
–30
–25
–20
–15
–10
–5
0
0 200 400 600 800 1000 1200 1400 1600
FREQUENCY (MHz)
–45
–50
–55
–60 1800 2000
Figure 17. Main Divider Input Sensitivity vs. Frequency and
Supply Voltage (TEMP = 25_C)
SR01930
–45
MINIMUM SIGNAL INPUT LEVEL (dBm)
+85_C
+25_C
–40_C
–40
–35
–30
–25
–20
–15
–10
0
–5
0 200 400 600 800 1000 1200 1400 1600 1800
FREQUENCY (MHz)
–50 2000
Figure 18. Main Divider Input Sensitivity vs. Frequency and
Temperature (VDD = 3.00 V)
SR01921
MINIMUM SIGNAL POWER LEVEL (dBm)
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (MHz)
VDD = 5.00 V
VDD = 3.75 V
VDD = 3.00 V
VDD = 2.70 V
Figure 19. Reference Divider Input Sensitivity vs. Frequency
and Supply Voltage (TEMP = 25_C)
SR01922
–55
MINIMUM SIGNAL POWER LEVEL (dBm)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (MHz)
TEMP = +85_C
TEMP = +25_C
TEMP = –40_C
Figure 20. Reference Divider Input Sensitivity vs. Frequency
and Temperature (VDD = 3.00 V)

Philips Semiconductors Product specification
SA70161.3GHz low voltage fractional-N synthesizer
1999 Nov 04 15
SR01931
8
I TOTAL (mA)
8.5
7.5
7
6.5
6
5.52.5 3 3.5 4 4.5 5 5.5 6
TEMP = +85_C
TEMP = +25_C
TEMP = –40_C
SUPPLY VOLTAGE (V)
Figure 21. Current Supply Over VDD

1.3GHz low voltage fractional-N frequency
synthesizer
Philips Semiconductors Product specification
SA7016
1999 Nov 04 16
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

1.3GHz low voltage fractional-N frequency
synthesizer
Philips Semiconductors Product specification
SA7016
1999 Nov 04 17
NOTES

1.3GHz low voltage fractional-N frequency
synthesizer
Philips Semiconductors Product specification
SA7016
1999 Nov 04 18
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
atanyotherconditionsabovethosegivenintheCharacteristicssectionsofthespecificationisnotimplied.Exposuretolimitingvaluesforextended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonablybe expectedtoresultin personal injury.Philips Semiconductors customers using orsellingtheseproducts for use insuchapplications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges,withoutnotice,intheproducts,includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products,andmakesno representationsorwarranties thattheseproducts arefreefrom patent,copyright,or maskworkrightinfringement,unless
otherwise specified.
Philips Semiconductors
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Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 11-99
Document order number: 9397 750 06565
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Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.