Photon Focus MV-D752-28 User manual

MV-D752-28
CMOS area scan camera
Camera User’s Manual
REV: 1.0

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MV-D752-28 User’s Manual
REVISION 1.0 2003 PHOTONFOCUS.
Important Note: Photonfocus reserves the right to make changes to its products without
notice. Photonfocus products are neither intended nor certified for use in life support
systems or in other critical systems. The use of Photonfocus products in such applications
is forbidden. Photonfocus, LinLog, LinLog2 and CameraLink are registered trademarks in
Switzerland and in other countries.
PHOTONFOCUS
The Swiss company Photonfocus specializes in the development of CMOS image
sensors and corresponding industrial cameras for the Machine Vision, High-End
Surveillance and Automotive markets.
Photonfocus, formed as a Spin-off from the Swiss Research Center for Electronics and
Microtechnology (CSEM) in April 2001, is dedicated to making the latest generation of
CMOS technology commercially available. Active Pixel Sensor (APS) and global shutter
technologies enable high speed applications and applications with high picture contrast
(120 dB) to be realized, while avoiding the disadvantages, e.g. image lag, of
conventional logarithmic CMOS sensors. LinLogTM Technology was recognized with the
Stuttgart Vision 2000 prize for innovation and, more recently, the Photonics Award of
Excellence. With these technologies, blooming and smear belong to the past.
With the digital MV-D1024, MV-D752 and MV-D640 camera series, Photonfocus has
proven that the image quality of modern CMOS sensors is now appropriate for
demanding measurement and automotive applications. The MV-D1024 camera attains full
frame rates of up to 150 fps with megapixel resolution; by using the Region Of Interest
(ROI) feature, the frame rate can be increased to well over 1000 frames per second. The
cameras can be supplied with either an LVDS (RS644) or a CameraLink digital interface.
The product range of Photonfocus is complemented by custom design solutions in the
area of camera electronics and CMOS image sensors. Customer specific requirements,
such as number of pixels, noise performance, dynamic range or sensitivity, can be
implemented and optimized.
PHOTONFOCUS is ISO 9001 certified. All products are produced with the latest
techniques in order to ensure the highest degree of quality
PHOTONFOCUS has a worldwide network of distributors available in Europe, the USA and
Asia.
For further information about PHOTONFOCUS and its products, please visit our
homepage:
http://www.photonfocus.com

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Index
1 Introduction................................................................................................... 5
2 Mechanical Dimensions.................................................................................... 7
3 Interface pin assignments ................................................................................ 8
3.1 CameraLink Interface................................................................................. 8
3.2 LVDS Interface ......................................................................................... 9
4 Status indicator .............................................................................................. 9
5 Timing Diagrams ............................................................................................ 9
5.1 Free running mode .................................................................................... 9
5.2 Trigger mode............................................................................................ 9
5.3 Trigger mode with external edge triggered exposure control............................ 9
5.4 Sync-exposure mode ................................................................................. 9
5.5 Overview of the trigger modes .................................................................... 9
6 Variation of the sensor characteristics................................................................ 9
7 Variation of the amplification ............................................................................ 9
8 Change of resolution ....................................................................................... 9
8.1 Flip Image................................................................................................ 9
8.2 Correction of manufacturing allowances........................................................ 9
9 Camera function test....................................................................................... 9
10 Description of the camera sensor registers....................................................... 9
10.1 Register assignment - sensor control group ................................................ 9
10.2 Register description - sensor control group................................................. 9
10.2.1 Register address 00H – 03H (EEPROM control) ..................................... 9
10.2.2 Register Addresses 1, 2, 4 and 5: status registers 0, 1, 3 and 4............... 9
10.2.3 Register Addresses 6 and 7: Mode registers 0 and 1............................... 9
10.2.4 Register Addresses 8 and 9: DAC interface ........................................... 9
10.2.5 Register Addresses 12-14: Mode register extended functions................... 9
10.2.6 Registers 15-17: Exposure time .......................................................... 9
10.2.7 Registers 18-20: for LinLog2............................................................... 9
10.2.8 Registers 21-23: Frame time .............................................................. 9
10.2.9 Registers 24-31: ROI......................................................................... 9
10.2.10 Register 32: Line pause................................................................... 9
10.2.11 Calculation of Frame time ................................................................ 9
10.2.12 Register 33: Line jump (and pixel jump) ............................................ 9
10.2.13 Register 47: RAM-Bank selection ...................................................... 9
10.2.14 Registers 48-63: Data for 16x8 RAM-Banks........................................ 9
10.3 Instructions for control of the Sensor Module.............................................. 9
10.4 Summary of the most important operation modes and their significance......... 9
11 Register assignment and instruction set of the ADC-Module................................ 9
11.1 Instructions for control of the ADC-Module ................................................. 9
11.1.1 Register Addresses 0 – 3: EEPROM control............................................ 9
11.1.2 Register Address 4: Status information of the ADC-Module...................... 9
11.1.3 Register Address 6: Basic modes and ADC-condition .............................. 9
11.2 Instructions for control of the ADC-Module ................................................. 9
12 Cleaning the sensor...................................................................................... 9
13 Appendix A – Configuration Settings of the EEPROM Sensor Module..................... 9
14 Appendix B - The configuration EEPROM ADC Module and its functions................. 9
15 Appendix C - RS232 Interface ........................................................................ 9
15.1 Definition of the transfer protocol.............................................................. 9
15.2 Example of access to camera registers....................................................... 9
16 Appendix D – Accessing the EEPROM .............................................................. 9
16.1 Example of EEPROM access...................................................................... 9
17 Appendix E – How to handle the DAC? ............................................................ 9
18 Appendix F – Pseudo random number generator............................................... 9
19 Appendix G - CE-Test Compliance................................................................... 9

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20 Literature.................................................................................................... 9
20.1 Books ................................................................................................... 9
20.2 Files on the web server www.photonfocus.com ........................................... 9
21 Tables ........................................................................................................ 9
22 Figures ....................................................................................................... 9
23 Revisions and State of Product development .................................................... 9
23.1 Revisions............................................................................................... 9
23.2 State of Product development................................................................... 9
24 Service information ...................................................................................... 9
24.1 Contact for product enquiries and quotations.............................................. 9
24.2 Product information, documentation and software updates ........................... 9
24.3 Storage and Transport ............................................................................ 9
24.4 Preparing for use.................................................................................... 9
24.5 Mounting the lens ................................................................................... 9
25 Guarantee conditions.................................................................................... 9

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1Introduction
The CMOS mega-pixel Camera series MV-D752 from Photonfocus is aimed at demanding
applications in industrial image processing and measurement. It offers an exceptionally
high dynamic range of up to 120 dB with a resolution of 752 x 582 pixels and a full frame
rate of up to 340 frames per second (MV-D752-160).
The CMOS camera series MV-D752, based on a CMOS sensor from Photonfocus, with 4
analog outputs, thus sets new standards in industrial image processing. The camera
profits from the advantages of CMOS sensor technology over the more conventional CCD
technology in the areas of e.g. blooming resistance, adjustable characteristics, selectable
read-out window (Region Of Interest, ROI) and low energy consumption at high data
rates. The global shutter permits high-speed applications in industrial image processing.
In order to attain a higher dynamic range, the characteristics can be arbitrarily adjusted
by the user between linear and logarithmic operation. Thus the LinLogTM technology is
ideally suited to applications with high contrast.
The Photonfocus mega-pixel camera MV-D752-28 is available with LVDS (RS644) and
CameraLink digital interfaces. The part codes of the various camera versions are shown
in Table 1. Table 2 summarizes the camera properties.
To acquire images, the camera can be operated in master configuration, slave
configuration or in trigger mode. In free-running mode, the camera (in master
configuration) needs no external control signals to acquire images. The integration time
and the read-out window (ROI) are pre-programmed in the camera via the configuration
interface and can be changed by the user by means of the RS232 interface.
The slave configuration allows the user to control the camera externally with an external
trigger signal, an external exposure signal or an external clock.
In trigger mode, the camera expects an external trigger signal defining the start of the
exposure time, which is defined in the camera register.
With its mega-pixel resolution, its high data rate as well as its high dynamic range and
compact construction of only 55 mm x 55 mm x 50 mm (B x H x L), the MV-D752-28 is
the perfect solution for applications with space restrictions, such as inspection stations or
"Pick and Place" Machines, where, additionally, low energy consumption is beneficial. The
versatility of the Photonfocus mega-pixel camera MV-D752-28 allows the optimization of
the camera parameters for a given image processing application by the user. The camera
parameters are continuously stored in an EEPROM and are loaded automatically at boot-
up. The camera parameters can be set and stored in the EEPROM by using the API
function library [SOFT] or the “PFRemote.exe” software [PFREMOTE], which are delivered
with the camera and employ the RS232 protocol. Low level programming of the
module hardware independently of the API function library will not be
supported by Photonfocus.
Table 1 : Part codes and order numbers for MV-D752-28 cameras
Interface Part codes Order numbers
CameraLink 10 bit MV-D752-28-CL-10 60 20 50.001
LVDS (RS644) 10 bit MV-D752-28-LV-10 60 20 50.002

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Table 2: Technical Data for the Photonfocus MV-D752-28 CMOS camera
Technical Data for the Photonfocus MV-D752-28 CMOS camera
Number of pixels 752 x 582
Pixel size 10.6 µm x 10.6 µm
Optically active area 8.0 mm x 6.2 mm
Optical diagonal 10.12 mm Î2/3” optic
Objective mount C-mount
Characteristic Linear or LinLogTM adjustable
Full well capacity 200 ke-
Sensitivity 10 µJ/m2/LSB @ 630 nm, 8 bit
Noise < 0.5 Grey level standard deviation @ 8 bit
Fixed Pattern Noise < 3 Grey level standard deviation @ 8 bit
Dynamic range in Linear Mode > 48 dB @ 8 bit
Dynamic range in LinLogTM Mode > 120 dB
Analog amplification 1 or 4
Spectral range 400 nm – 900 nm (see Fig. 1)
Optical Fill factor 35%
Data interface LVDS and CameraLink
Data resolution 10 bit, 8 bit or 10 to 8 bit LUT
Internal Pixel clock 28.375 MHz
External clock rate CameraLink Interface 20.0 MHz to 28.4 MHz
External clock rate LVDS Interface 10.0 MHz to 28.4 MHz
Maximum frame rate 60 fps @ Tint = 10 µs
Shutter Type global shutter
Exposure time 1 µs – 0.5 s in steps of 35 ns
Configuration interface RS232 Standard, 9600 baud, 1 Start bit, 1
Stop bit, no Parity bit
Voltage supply +5V DC +/-10%
Power consumption 2 W
Dimensions 55 mm (B) x 55 mm (H) x 50 mm (L)
Weight 200g
CE Test (see Appendix G) EN 61000-6-3 : 2001
EN 61000-6-2 : 2001
Fig. 1: Quantum efficiency as function of wavelength

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2Mechanical Dimensions
The Front plate is compatible with the Microbench System of LINOS AG (www.linos.de)
[MB2002].
Inte rfa c e C a m e ra Link
46
Inte rfa c e LVDS

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3Interface pin assignments
The CMOS camera series MV-D752 is available with a CameraLink interface in the base
configuration or an LVDS (RS644) interface. The signal definitions, the bit allocations and
the signal level of the CameraLink standard are described in [CLO2000]. Detailed
information about the LVDS (RS644) standard is given in [LOM2000].
3.1 CameraLink Interface
The CameraLink Interface has a socket with signals for data transfer and control of the
camera functions as well as a socket for the voltage supply. The socket pin assignments
for data and control signals are defined in the CameraLink Standard [CLO2000]. The
socket assignment is shown in Table 3, the assignment of the data bits in the 8-bit
configuration is shown in Table 5. Table 6 contains the assignment of the 10-bit
configuration. The subminiature connector Binder Series 712 is used for current supply.
The order number for the camera socket is 09-0408-90-03 (see Table 4 und Fig. 2). A
plug (order number 99-0405-00-03) is necessary to connect the camera.
Table 3: Pin assignments for the MDR26 socket of the CameraLink Interface
PIN I/O Name Description
1 PW SHIELD Shield
2 O N_XD0 Negative LVDS Output, CameraLink DataD0
3 O N_XD1 Negative LVDS Output, CameraLink DataD1
4 O N_XD2 Negative LVDS Output, CameraLink DataD2
5 O N_XCLK Negative LVDS Output, CameraLink Clock
6 O N_XD3 Negative LVDS Output, CameraLink DataD3
7 I P_SERTOCAM Positive LVDS Input, Serial Communication to the camera
8 O N_SERTOFG Negative LVDS Output, Serial Communication from the camera
9 I N_CC1 Negative LVDS Input, External Trigger signal EXSYNC
10 I P_CC2 Positive LVDS Input, External clock for Slave mode MCLK
11 I N_CC3 Negative LVDS Input, Exposure control EXPOSURE
12 I P_CC4 Positive LVDS Input, Control signal CONTROL <not used>
13 PW SHIELD Shield
14 PW SHIELD Shield
15 O P_XD0 Positive LVDS Output, CameraLink DataD0
16 O P_XD1 Positive LVDS Output, CameraLink DataD1
17 O P_XD2 Positive LVDS Output, CameraLink DataD2
18 O P_XCLK Positive LVDS Output, CameraLink clock
19 O P_XD3 Positive LVDS Output, CameraLink DataD3
20 I N_SERTOCAM Negative LVDS Input, Serial Communication to the camera
21 O P_SERTOFG Positive LVDS Output, Serial Communication from the camera
22 I P_CC1 Positive LVDS Input, external Trigger signal EXSYNC
23 I N_CC2 Negative LVDS Input, external clock for Slave mode MCLK
24 I P_CC3 Positive LVDS Input, Exposure control EXPOSURE
25 I N_CC4 Negative LVDS Input, Control signal CONTROL <not used>
26 PW SHIELD Shield
S PW SHIELD Shield

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Table 4: Pin assignments for the socket of the voltage supply connector
PIN I/O Name Description
1 PW VDD + 5 V voltage supply
2 PW GND Ground
3 PW VDD2 Reserved
Fig. 2: Connector socket Nr. 09-0408-90-03 for the voltage supply
Table 5: Data bit assignments for the 8-bit configuration
Data bit CameraLink Port and bit
LSB A0
LSB +1 A1
LSB +2 A2
LSB +3 A3
LSB +4 A4
LSB +5 A5
LSB +6 A6
MSB A7
Table 6: Data bit assignments for the 10-bit configuration
Data bit CameraLink Port and bit
LSB A0
LSB +1 A1
LSB +2 A2
LSB +3 A3
LSB +4 A4
LSB +5 A5
LSB +6 A6
LSB +7 A7
LSB +8 B0
MSB B1
2
3 1

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3.2 LVDS Interface
To implement the LVDS (RS644) interface, the Molex 60 pole Low Force Helix (LFH60)
plug system was used. This very compact plug system possess the property that the
insertion force at the start of the insertion is very low and increases steadily as the plug
is introduced. Due to the use of two contact points for each plug contact, the safety of
the connection is substantially higher than that of other conventional systems. The
Photonfocus LVDS Interface combines data and control signals as well as current supply
on one socket. This has the advantage for the user that only one cable is needed
between camera and frame grabber. The contact pin sequence of the LFH60 system
was altered from that used by the manufacturer (Molex). Only the position of
contact 1 is identical in the two systems. In contrast to the Molex system, in which the
contacts are numbered in a meandering fashion, Photonfocus begins the count a new at
the top of each column. The Photonfocus definitions are made clear in Table 7 and Fig. 3.
Fig. 3 illustrate the pin assignments for the LVDS interface of the Photonfocus camera
series. The interface definition contains the following: 16 data signals, 8 handshake
signals for camera control by the frame grabber, an RS232 interface for camera set-up,
as well as voltage supply. The 16 data signals can be used in different ways, depending
on the camera type. The MV-D752-28LV-10 uses only the lower 10 bits (DATA0 ...
DATA9). In the 8 bit camera mode, the top 2 bits (DATA 9 und DATA 8) are set LOW
internally and thus deactivated. The 8 handshake lines are divided between 4 input
signals and 4 output signals. Input signals comprise the external trigger EXSYNC, the
external exposure control EXPOSURE, the external clock signal for the slave mode
(master clock) MCLK and an external camera control signal CONTROL. The camera output
signals FRAME_VALID, LINE_VALID and PIXEL_CLK are modeled on the AIA interface
[AIA]. FRAME_VALID high indicates an active image transfer. LINE_VALID high denotes
an active line. The digital data for the individual pixels are output on the rising edge of
PIXEL_CLK. In addition to these signals, the signal SHUTTER is defined to be high during
the integration phase of the sensor. This signal permits the synchronization of external
light sources e.g. a flash light (see section Timing Diagram).

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Table 7: LFH60 Socket pin assignment Molex Order number 70928-0002
PIN I/O Name Description
1 O PDATA0 Positive LVDS Output, Data bit 0
2 O PDATA2 Positive LVDS Output, Data bit 2
3 O PDATA4 Positive LVDS Output, Data bit 4
4 O PDATA6 Positive LVDS Output, Data bit 6
5 O PDATA8 Positive LVDS Output, Data bit 8
6 O PDATA10 Positive LVDS Output, Data bit 10, not used
7 O PDATA12 Positive LVDS Output, Data bit 12, not used
8 O PDATA14 Positive LVDS Output, Data bit 14, not used
9 O PFRAME_VALID Positive LVDS Output, FRAME_VALID
10 O PLINE_VALID Positive LVDS Output, LINE_VALID
11 I PEXSYNC Positive LVDS Input, external trigger signal EXSYNC
12 I PEXPOSURE Positive LVDS Input, external exposure control EXPOSURE
14 PW GND Ground
15 PW GND Ground
16 O NDATA0 Negative LVDS Output, Data bit 0
17 O NDATA2 Negative LVDS Output, Data bit 2
18 O NDATA4 Negative LVDS Output, Data bit 4
19 O NDATA6 Negative LVDS Output, Data bit 6
20 O NDATA8 Negative LVDS Output, Data bit 8
21 O NDATA10 Negative LVDS Output, Data bit 10, not used
22 O NDATA12 Negative LVDS Output, Data bit 12, not used
23 O NDATA14 Negative LVDS Output, Data bit 14, not used
24 O NFRAME_VALID Negative LVDS Output, FRAME_VALID
25 O NLINE_VALID Negative LVDS Output, LINE_VALID
26 I NEXSYNC Negative LVDS Input, external trigger signal EXSYNC
27 I NEXPOSURE Negative LVDS Input, external exposure control EXPOSURE
29 PW GND Ground
30 PW GND Ground
31 O NDATA1 Negative LVDS Output, Data bit 1
32 O NDATA3 Negative LVDS Output, Data bit 3
33 O NDATA5 Negative LVDS Output, Data bit 5
34 O NDATA7 Negative LVDS Output, Data bit 7
35 O NDATA9 Negative LVDS Output, Data bit 9
36 O NDATA11 Negative LVDS Output, Data bit 11, not used
37 O NDATA13 Negative LVDS Output, Data bit 13, not used
38 O NDATA15 Negative LVDS Output, Data bit 15, not used
39 O NSHUTTER Negative LVDS Output, active integration SHUTTER / FLASH
40 O NPIXEL_CLK Negative LVDS Output, PIXEL_CLOCK
41 I NCONTROL Negative LVDS Input, Control signal CONTROL <not used>
42 I NMCLK Negative LVDS Input, External clock for Slave mode MCLK
43 I RX_RS232 RX, RS232 Camera Interface, RS232 Signal level
44 PW VDD + 5 V Voltage supply
45 PW VDD + 5 V Voltage supply
46 O PDATA1 Positive LVDS Output, Data bit 1
47 O PDATA3 Positive LVDS Output, Data bit 3
48 O PDATA5 Positive LVDS Output, Data bit 5
49 O PDATA7 Positive LVDS Output, Data bit 7
50 O PDATA9 Positive LVDS Output, Data bit 9
51 O PDATA11 Positive LVDS Output, Data bit 11, not used
52 O PDATA13 Positive LVDS Output, Data bit 13, not used
53 O PDATA15 Positive LVDS Output, Data bit 15, not used
54 O PSHUTTER Positive LVDS Output, active integration SHUTTER / FLASH
55 O PPIXEL_CLK Positive LVDS Output, PIXEL_CLOCK
56 I PCONTROL Positive LVDS Input, Control signal CONTROL <not used>
57 I PMCLK Positive LVDS Input, External clock for Slave mode MCLK
58 O TX_RS232 TX, RS232 Camera Interface, RS232 Signal level
59 PW VDD + 5 V Voltage supply
60 PW VDD + 5 V Voltage supply
S PW SHIELD Shield
13, 28 PW -- Reserved
PW: Voltage supply
I: Input
O: Output

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Table 8: Contact pin sequence for the LFH60 plug system of the MV-D752
camera series
Column Pin numbers
1 Start at Molex mark 1 Î1 ... 15
2 Count continuation below Pin 1 16 ...30
3 Count continuation below Pin 16 31 ...45
4 Count continuation below Pin 31 46 ...60
PMCLK
NMCLK
NEXSYNC
PEXPOSURE
NEXPOSURE
PCONTROL
NCONTROL
PEXSYNC
PDATA0
NDATA0
PDATA1
NDATA1
PDATA2
NDATA2
PDATA3
NDATA3
PDATA4
NDATA4
PDATA5
NDATA5
PDATA6
NDATA6
PDATA7
NDATA7
PDATA8
NDATA8
PDATA9
NDATA9
PDATA10
NDATA10
PDATA11
NDATA11
PPIXEL_CLK
NPIXEL_CLK
PFRAME_VALID
NFRAME_VALID
PLINE_VALID
NLINE_VALID
PSHUTTER
NSHUTTER
PDATA12
NDATA12
PDATA14
NDATA14
PDATA13
NDATA13
PDATA15
NDATA15
GROUND
GROUND
VDD
VDD
RX_RS232
TX_RS232
GROUND
GROUND
VDD
VDD
VDD2
VDD2
12
11
10
9
8
7
57
56
55
40
54
39
53
38
52
37
51
36
50
35
49
34
48
33
47
32
46
31
6
5
4
3
2
1
15
14
13
59
58
60
45
44
43
42
41
17
19
18
20
21
22
23
30
29
28
27
24
25
26
16
CON
LFH60
Fig. 3: View of LFH60 socket on rear of camera with signal allocations
4Status indicator
A two color LED on the rear of the camera indicates the camera status to the user. In
normal operation the LED lights green when an image is being produced. At low frame
rates a flickering can be observed that changes to a continuous light at high frame rates.
Since the light intensity is dependent on the relation between exposure time and read-
out time, the light from the LED can practically disappear when using small ROI and long
exposure times.
A red LED indicates that serial communication is active.

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5Timing Diagrams
The parameter constant image data rate bit 1 register 12 has several functions. In free
running mode it enables the acquisition of images with constant image data rate. If this
parameter is deactivated, the data rate is determined directly by the exposure time and
the readout time. In trigger mode, re-triggering during the frame time by an external
trigger signal is suppressed. If deactivated, readout can be interrupted by a new trigger.
In this mode the user should ensure that the trigger rate and the frame rate correspond.
Fig. 4 illustrates the function of the parameter constant image data rate.
External trigger mode constant image data rate
External trigger mode variable image data rate
Free running mode constant image data rate
Free running mode variable image data rate
Fig. 4: Function of the parameter constant image data rate
Integration Readout
Re-trigger blocked
EXSYNC EXSYNC ignored
Integration
Reset
Frame timer
Integration Readout Integration
Reset
Integration Readout Integration Readout
Integration Readout
EXSYNC EXSYNC
IntegrationReset

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5.1 Free running mode
The pre-installed free running mode allows images to be acquired without external
control signals. The sensor will be read out after the set integration time; then the sensor
will be reset. Following this, integration starts again and the readout of the image
information begins afresh. The data are output on the rising edge of the pixel clock. The
signals FRAME_VALID (FVAL) and LINE_VALID (LVAL) mask valid image information. The
signal SHUTTER indicates the active integration phase of the sensor. The number of clock
pulses after exposure CPRE is defined by the calculation of the frame time (see 9).
Fig. 5: Timing Diagram Free Running Mode
PCLK
SHUTTE
R
FVA
L
DATA
EXSYNC
LVA
L
line pause first line line pause last line
CPRE
Integration
Frametime
line pause
EXPOSURE

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5.2 Trigger mode
In trigger mode image acquisition begins with the rising edge of an external trigger pulse
(POLARITY_SYNC_EXPOSURE = ‘1’). The image will be read out after the preset exposure
time. After readout, the sensor returns to the reset state and the camera waits for a new
trigger pulse. If necessary, the polarity of the EXSYNC signal can be matched to that of
the frame grabber by means of the flag POLARITY_SYNC_EXPOSURE bit 3 mode register
3.
The data are output on the rising edge of the pixel clock. The signals FRAME_VALID
(FVAL) and LINE_VALID (LVAL) mask valid image information. The signal SHUTTER
indicates the active integration phase of the sensor. The number of clock pulses after
exposure CPRE is defined by the calculation of the frame time (see 9).
Fig. 6: Timing Diagram Trigger Mode
EXSYNC is ignored in mode constant image data rate
PCLK
SHUTTE
R
FVA
L
EXPOSURE
DATA
EXSYNC
LVA
L
line pause first line line pause last line
CPRE
Integration
line
p
ause

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5.3 Trigger mode with external edge triggered exposure control
In trigger mode with external edge triggered exposure control, sensor control is reset
with the rising edge of an external trigger pulse (POLARITY_SYNC_EXPOSURE = ‘1’) and
the exposure of the image begins. The integration ends with the rising edge of the
external signal EXPOSURE (POLARITY_SYNC_EXPOSURE = ‘1’). The signals EXSYNC and
EXPOSURE are clocked in the sensor control in such a way that the internal exposure
control becomes active one clock (35 ns in case of internal clock) later (see SHUTTER
signal). If necessary, the polarity of the EXSYNC signal can be matched to that of the
frame grabber by means of the flag POLARITY_SYNC_EXPOSURE bit 3 mode register 3.
The image is read out after the exposure time has elapsed. After readout, the sensor
returns to the reset state and the camera waits for a new trigger pulse.
The data are output on the rising edge of the pixel clock. The signals FRAME_VALID
(FVAL) and LINE_VALID (LVAL) mask valid image information. The signal SHUTTER
indicates the active integration phase of the sensor. The number of clock pulses after
exposure CPRE is defined by the calculation of the frame time (see 9).
Fig. 7: Timing Diagram Trigger Mode with external edge triggered exposure
control
EXPOSURE
EXSYNC is ignored in mode constant image data rate
PCLK
SHUTTE
R
FVA
L
DATA
EXSYNC
LVA
L
line pause first line line pause last line
CPRE
Integration
line
p
ause

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5.4 Sync-exposure mode
In Sync-Exposure mode, sensor control is reset with the rising edge of an external trigger
pulse EXSYNC and the exposure of the image begins. The integration ends with the
falling edge of the external signal EXSYNC. The signal EXSYNC is clocked in the sensor
control in such a way that the internal exposure control becomes active one clock (35 ns
in case of internal clock) later (see SHUTTER signal). If necessary, the polarity of the
EXSYNC signal can be matched to that of the frame grabber by means of the flag
POLARITY_SYNC_EXPOSURE bit 3 mode register 3.
The image is read out after the exposure time has elapsed. After readout, the sensor
returns to the reset state and the camera waits for a new trigger pulse.
The data are output on the rising edge of the pixel clock. The signals FRAME_VALID
(FVAL) and LINE_VALID (LVAL) mask valid image information. The signal SHUTTER
indicates the active integration phase of the sensor. The number of clock pulses after
exposure CPRE is defined by the calculation of the frame time (see 9).
Fig. 8: Timing Diagram Sync-Exposure Mode
EXPOSURE
EXSYNC is ignored in mode constant image data rate
PCLK
SHUTTE
R
FVA
L
DATA
EXSYNC
LVA
L
line pause first line line pause last line
CPRE
Integration
line
p
ause

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5.5 Overview of the trigger modes
The following overview summarizes the functions of the various trigger modes.
RE_xxxx: Rising Edge of signal
FE_xxxx: Falling Edge of signal
Polarity TRIGGER START EXPOSURE START EXPOSURE STOP
EXSYNC Mode internal exposure time via Register
- 1 FE_EXSYNC FE_EXSYNC EXPOSURE_END
+1 RE_EXSYNC RE_EXSYNC EXPOSURE_END
EXSYNC – EXPOSURE Start/Stop Trigger for exposure time
- 1 FE_EXSYNC FE_EXSYNC FE_EXPOSURE
+1 RE_EXSYNC RE_EXSYNC RE_EXPOSURE
EXSYNC-EXPOSURE
- 1 FE_EXSYNC FE_EXSYNC RE_EXSYNC
+1 RE_EXSYNC RE_EXSYNC FE_EXSYNC

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6Variation of the sensor characteristics
The LinLogTM CMOS image sensors from Photonfocus afford the user the possibility to
adapt the characteristics of the sensor to the requirements of the application.
For normal applications that do not require high contrast, the sensor can be operated in
linear mode. For applications having short exposure times and low illumination intensity,
it is advisable to activate skim mode, in which a non-linear amplification, similar to a
gamma correction, occurs in the pixel so that small signals are amplified significantly
more than large signals (see Variation of the amplification).
In situations involving high intrascene contrast, compression of the upper grey level
region can be achieved with the LinLogTM Technology. At low intensities, each pixel
shows a linear response. At high intensities, the response changes to logarithmic
compression. The transition region between linear and logarithmic response can be
smoothly adjusted and is continuously differentiable. This setting is achieved via DAC
channel 4 in the voltage range 0 – 4V (see Appendix E).
For many applications the logarithmic compression of the LinLogTM mode is too large. For
this reason the LinLog2TM technique was developed by Photonfocus to allow a significantly
more moderate transition between the two response regions. In addition, two further
parameters (lower LinLog value and LinLog2 time) were introduced to control the
transition. At the beginning of the exposure time, high intensities are integrated with the
upper LinLog value, i.e. strong logarithmic compression. After time LinLog2, the lower
LinLog value is activated and lower intensities are integrated with almost linear response.
By varying these three parameters the response can be adjusted to the needs of the
application over a wide range. A detailed description of the LinLog2TM technique is
explained in Photonfocus Application note [AS001].
Fig. 9: Response of the various camera modes
0
2
4
6
8
10
12
14
16
18
20
0 5 10 15 20 25
Light intensity
Output signal
LinLog
T
M
response
logarithmic
response
linear
response
LinLog transition
point, adjustable

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7Variation of the amplification
The MV-D752-28 camera contains several possibilities for amplifying the video signal. On
the one hand the CMOS sensor can be operated in skim mode, corresponding to a non-
linear amplification. In this mode low intensities are amplified more strongly than high
intensities (small signal amplification). The resulting response is similar to a gamma
correction. Fig. 10 shows an example of sensor response for a fixed skim voltage in
comparison with the linear response of the sensor. The right hand figure represents a
zoom of the lower intensity region. The small signal amplification is the relation between
the sensor output voltages of both modes at constant low illumination. The skim voltage
can be varied via DAC channel 3 in the voltage range 0 – 4V (see Appendix E). An
unsuitable choice of parameters can lead to image lag with high contrast scenes,
resulting in smearing of the image and reduced image quality. A skim voltage of 1.4V,
corresponding to a small signal amplification of about 2, turns out to be a reasonable
value in practice.
In Skim mode, please note: Exposure time <10ms; LinLog voltage < 1V. To
increase the shutter efficiency a LinLog value of 25 should be used! Furthermore,
when using this mode constant frame time the frame time should be set to a value that
allows the sensor a reset time of at least 10 µs.
Fig. 10: Sensor response in Skim mode compared with linear response
On the other hand, it is possible to switch the amplification of the video amplifier of the
sensor module between amplification factors 1 and 4 by activating bit 7 register 7. The
offset correction for the amplifier must then be adjusted. If option EN_TOGGLE bit 4
register 6 is activated, the switch occurs automatically. In this case switching occurs
between two preset offset values. If the automatic offset correction is deactivated, the
user is responsible for suitably adjusting the correction. This is achieved for every
operating mode by adjusting the video signal offset via DAC channel 5 (see Appendix E).
Moreover, in the 8-bit output mode of the camera, digital amplification factors 2 and 4
can be set using bit shift operations. For this purpose, the two LUTs have been factory
pre-programmed (see Appendix B). It is important to note that, when using these LUTs
with a maximum gray level value of 255, the LinLogTM modes perform a compression of
the upper gray level values and the contrast improvement cannot be attained with the
pre-programmed LUTs. By suitably adjusting the LUTs, non-linear responses can be
realized, allowing the gray level range of interest to be spread to suit the application.
Moreover, response ranges of the LinLogTM modes can also be transferred to the 8-bit
output resolution.