Phytec phyCORE-AM62 Series User manual

A product of a PHYTEC Technology Holding company
phyCORE®-AM62xx
Hardware Manual
Document No.:
L-1038e.A0
SOM Prod. No.:
PCM-071
SOM PCB. No.:
1573.1
CB Prod. No.:
PBA-C-24
CB PCB. No.:
1576.1
Edition:
Sep 2022

PCM-071/phyCORE-AM62xx System on Module
L-1038e.A0
© PHYTEC America L.L.C. 2022 2
1Table of Contents
1Table of Contents ..........................................................................................................................................2
1.1 List of Figures.........................................................................................................................................6
1.2 List of Tables ..........................................................................................................................................7
2SOM Features ...............................................................................................................................................9
3Conventions, Abbreviations and Acronyms.................................................................................................10
3.1 Conventions .........................................................................................................................................10
3.2 Abbreviations and Acronyms................................................................................................................10
3.3 Types of Signals...................................................................................................................................11
4Introduction..................................................................................................................................................13
4.1 Block Diagram ......................................................................................................................................14
4.2 Physical Dimensions ............................................................................................................................15
4.3 Connector Alignment for Mating to Carrier Boards ..............................................................................18
4.4 Component Placement Diagram ..........................................................................................................20
4.5 Technical and Electrical Specifications ................................................................................................22
4.6 Minimum Requirements for Operation .................................................................................................22
4.7 Solder Jumpers ....................................................................................................................................23
4.8 Pin Descriptions ...................................................................................................................................27
4.9 Pinout Table .........................................................................................................................................28
4.10 Thermal Management ..........................................................................................................................34
4.11 Layout Guidelines.................................................................................................................................35
4.11.1 High-Speed Differential Signal Routing Guidelines.......................................................................35
4.11.2 General Signal Routing Guidelines ...............................................................................................36
5Power ..........................................................................................................................................................37
5.1 Primary System Power (VIN) ...............................................................................................................37
5.1.1 Primary Power Reference Circuit..................................................................................................37
5.2 Backup Power (VBAT) .........................................................................................................................39
5.3 Reset ....................................................................................................................................................39

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5.4 Power Sequencing ...............................................................................................................................40
5.5 Safe Shutdown and Sudden Power Loss.............................................................................................41
6System Memory...........................................................................................................................................41
6.1 SOM Memory .......................................................................................................................................42
6.1.1 DDR4 RAM ...................................................................................................................................42
6.1.2 EEPROM.......................................................................................................................................42
6.1.3 eMMC Flash..................................................................................................................................42
6.1.4 OSPI..............................................................................................................................................42
6.2 External Memory Bus ...........................................................................................................................42
6.2.1 GPMC ...........................................................................................................................................42
6.2.2 SD/MMC/SDIO..............................................................................................................................44
6.3 System Boot Configuration...................................................................................................................49
7Serial Interfaces...........................................................................................................................................51
7.1 CAN......................................................................................................................................................51
7.1.1 CAN Pinout ...................................................................................................................................51
7.1.2 CAN Reference Circuit..................................................................................................................51
7.2 Ethernet................................................................................................................................................52
7.2.1 Ethernet Pinout .............................................................................................................................52
7.2.2 Ethernet Design In Guide..............................................................................................................54
7.2.3 Ethernet Reference Circuits ..........................................................................................................56
7.3 I2C.........................................................................................................................................................58
7.3.1 I2C Pinout ......................................................................................................................................59
7.4 SPI........................................................................................................................................................59
7.4.1 SPI Pinout .....................................................................................................................................59
7.5 UART....................................................................................................................................................60
7.5.1 UART Pinout .................................................................................................................................60
7.6 USB ......................................................................................................................................................63
7.6.1 USB Pinout....................................................................................................................................63
7.6.2 USB Design In Considerations......................................................................................................63

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7.6.3 USB Reference Circuits ................................................................................................................63
7.7 MCASP.................................................................................................................................................65
7.7.1 MCASP Pinout ..............................................................................................................................65
8Display and Camera Interfaces ...................................................................................................................67
8.1 VOUT ...................................................................................................................................................67
8.1.1 VOUT Pinout .................................................................................................................................68
8.2 OLDI/LVDS...........................................................................................................................................69
8.2.1 OLDI/LVDS Pinout ........................................................................................................................69
8.2.2 OLDI/LVDS Design In Considerations ..........................................................................................69
8.2.3 OLDI/LVDS Reference Circuits.....................................................................................................70
8.3 CSI .......................................................................................................................................................71
8.3.1 CSI Pinout .....................................................................................................................................71
8.3.2 CSI Design In Considerations .......................................................................................................72
8.3.3 CSI Reference Circuits..................................................................................................................73
9Control Interfaces ........................................................................................................................................74
9.1 Enhanced Capture ...............................................................................................................................74
9.1.1 ECAP Pinout .................................................................................................................................75
9.2 Enhanced Pulse-Width Modulation ......................................................................................................75
9.2.1 EPWM Pinout................................................................................................................................76
9.3 Enhanced Quadrature Encoder Pulse..................................................................................................76
9.3.1 EQEP Pinout .................................................................................................................................76
10 Peripheral Interfaces ...................................................................................................................................77
10.1 CPTS....................................................................................................................................................77
10.1.1 CPTS Pinout .................................................................................................................................77
10.2 GPIO ....................................................................................................................................................77
10.2.1 GPIO Pinout ..................................................................................................................................78
10.3 TIMER ..................................................................................................................................................85
10.3.1 Timer Pinout..................................................................................................................................85
11 Debug Interfaces ........................................................................................................................................85

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11.1 JTAG ....................................................................................................................................................85
11.1.1 JTAG Pinout..................................................................................................................................86
11.1.2 JTAG Reference Circuit ................................................................................................................86
11.2 TRACE (TRC) ......................................................................................................................................87
11.2.1 TRC Pinout....................................................................................................................................87
11.3 UART0..................................................................................................................................................88
11.3.1 UART0 Pinout ...............................................................................................................................88
11.3.2 UART0 Reference Circuits............................................................................................................88
12 System Interfaces........................................................................................................................................92
12.1 MAIN Pinout .........................................................................................................................................92
12.2 MCU Pinout ..........................................................................................................................................92
12.3 WKUP Pinout .......................................................................................................................................93
12.4 RTC Pinout...........................................................................................................................................93
13 Integrating and Updating the phyCORE-AM62xx........................................................................................94
13.1 Integration ............................................................................................................................................94
13.2 Modification ..........................................................................................................................................94
13.3 In-Field Updates ...................................................................................................................................94
13.4 Product Change Management .............................................................................................................95
14 Additional Information..................................................................................................................................96
15 Revision History...........................................................................................................................................98

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1.1 List of Figures
Figure 1. phyCORE-AM62xx SOM ..................................................................................................................13
Figure 2. phyCORE-AM62xx Block Diagram .................................................................................................14
Figure 3. phyCORE-AM62xx Dimensions Top View .....................................................................................15
Figure 4. phyCORE-AM62xx Dimensions Bottom View ...............................................................................16
Figure 5. phyCORE-AM62xx Dimensions End View.....................................................................................17
Figure 6. Top Down View of Mating Connectors ..........................................................................................18
Figure 7. Carrier Board Alignment Hole Placement .....................................................................................19
Figure 8. phyCORE-AM62xx Component Placement (processor side) ......................................................20
Figure 9. phyCORE-AM62xx Component Placement (connector side) .......................................................21
Figure 10. 3-Position Solder Jumper Pad Numbering Scheme....................................................................23
Figure 11. Jumper Locations (Processor side)..............................................................................................25
Figure 12. Jumper Locations (Connector side) .............................................................................................26
Figure 12. Pinout of the phyCORE-Connector..............................................................................................27
Figure 13. Fan design reference circuit..........................................................................................................35
Figure 14. Primary Power VIN(VCC_5V0_MAIN) reference circuit ...............................................................38
Figure 15. SOM current reader reference circuit ...........................................................................................38
Figure 16. Phoenix connector power input with overload protection reference circuit ............................39
Figure 17. Carrier board power reference circuit ..........................................................................................41
Figure 18. MMC1 SD-card Reader Reference Schematic..............................................................................46
Figure 19. MMC1 Load Switch Reference Schematic....................................................................................47
Figure 20. M.2 WIFI MMC2 Connector Reference Schematic .......................................................................47
Figure 21. M.2 WIFI MMC2 Level Translators Reference Schematic ...........................................................48
Figure 22. Reference Schematic for BOOTMODE configuration .................................................................50
Figure 23. MCAN0 Reference Schematic........................................................................................................51
Figure 24. RJ45 Reference Schematic............................................................................................................56
Figure 25. RGMII PHY RJ45 Reference Schematic ........................................................................................57
Figure 26. RGMII PHY Strapping Resistors Reference Schematic ..............................................................57
Figure 27. RGMII PHY Reference Schematic..................................................................................................58
Figure 28. USB-HUB Reference Schematic....................................................................................................64
Figure 29. USB 2.0 Connector Reference Schematic....................................................................................64
Figure 30. USB-C Connector Reference Schematic ......................................................................................65
Figure 31. OLDI Connector Reference Schematic.........................................................................................70
Figure 32. OLDI Level Translator Reference Schematic ...............................................................................71
Figure 33. CSI Power Toggle Reference Schematic......................................................................................73
Figure 34. CSI Connector Reference Schematic ...........................................................................................74

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Figure 35. JTAG Reference Schematic...........................................................................................................86
Figure 36. UART0 to USB Bridge Reference Schematic ...............................................................................89
Figure 36. UART0 to USB Buffers and Regulator Reference Schematic.....................................................90
Figure 37. Simple UART0 Reference Schematic............................................................................................91
1.2 List of Tables
Table 1 Abbreviations and Acronyms used in this Manual ..........................................................................10
Table 2 Signal Types Used in this Manual .....................................................................................................12
Table 3 Technical Specifications ....................................................................................................................22
Table 4 Recommended Operating Conditions for the Input and Output Power Domains.........................22
Table 5 Solder Jumper Settings ......................................................................................................................23
Table 6 Voltage Domain Configurations.........................................................................................................24
Table 7 phyCORE-AM62xx Connector X1, Column A Pinout .......................................................................28
Table 8 phyCORE-AM62xx Connector X1, Column B Pinout .......................................................................30
Table 9 phyCORE-AM62xx Connector X1, Column C Pinout .......................................................................31
Table 10 phyCORE-AM62xx Connector X1, Column D Pinout .....................................................................33
Table 11 Thermal Management Parts .............................................................................................................34
Table 12 External Supply Voltages .................................................................................................................37
Table 13 Reset Pin Description .......................................................................................................................40
Table 14 GPMC Signal Connections at the phyCORE-Connector................................................................43
Table 15 MMC Connections at the phyCORE-Connector .............................................................................45
Table 16 phyCORE-AM62xx MMC1 Layout Characteristics .........................................................................45
Table 17 BOOTMODE Description ..................................................................................................................49
Table 18 MCAN Connections at the phyCORE-Connector ...........................................................................51
Table 19 Ethernet PHY Default Strapping Configuration..............................................................................52
Table 20 Ethernet Connections at the phyCORE-Connector .......................................................................52
Table 21 IEP Connections at the phyCORE-Connector ................................................................................53
Table 22 phyCORE-AM62xx CPSW_ETH0 Layout Characteristics ..............................................................54
Table 23 phyCORE-AM62xx RGMII Timing Requirements............................................................................55
Table 24 phyCORE-AM62xx RMGII2 Trace Length Characteristics.............................................................55
Table 25 I2C Connections at the phyCORE-Connector .................................................................................59
Table 26 SPI Connections at the phyCORE-Connector ................................................................................59
Table 27 UART Connections at the phyCORE-Connector ............................................................................60
Table 28 USB Connections at the phyCORE-Connector ..............................................................................63
Table 29 phyCORE-AM62xx USB0 Layout Characteristics ..........................................................................63
Table 30 MCASP Connections at the phyCORE-Connector .........................................................................65

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Table 31 VOUT Connections at the phyCORE-Connector ............................................................................68
Table 32 OLDI/LVDS Connections at the phyCORE-Connector...................................................................69
Table 33 phyCORE-AM62xx USB0 Layout Characteristics ..........................................................................69
Table 34 CSI Connections at the phyCORE-Connector ................................................................................71
Table 35 phyCORE-AM62xx USB0 Layout Characteristics ..........................................................................72
Table 36 ECAP Connections at the phyCORE-Connector ............................................................................75
Table 37 EPWM Connections at the phyCORE-Connector...........................................................................76
Table 38 EQEP Connections at the phyCORE-Connector ............................................................................76
Table 39 CPTS Connections at the phyCORE-Connector ............................................................................77
Table 40 Total Available GPIO .........................................................................................................................78
Table 41 GPIO0 Accessibility at phyCORE-Connector .................................................................................78
Table 42 GPIO1 Accessibility at phyCORE-Connector .................................................................................80
Table 43 MCU_GPIO0 Accessibility at phyCORE-Connector .......................................................................81
Table 44 PR0_PRU0_GPIO Accessibility at phyCORE-Connector...............................................................82
Table 45 PR0_PRU1_GPIO Accessibility at phyCORE-Connector...............................................................83
Table 46 Timer Signals.....................................................................................................................................85
Table 47 JTAG Connections at the phyCORE-Connector ............................................................................86
Table 48 TRC Connections at the phyCORE-Connector...............................................................................87
Table 49 UART0 Connections at the phyCORE-Connector ..........................................................................88
Table 50 MAIN Connections at the phyCORE-Connector.............................................................................92
Table 51 MCU Connections at the phyCORE-Connector..............................................................................92
Table 52 WKUP Connections at the phyCORE-Connector ...........................................................................93
Table 53 RTC Connections at the phyCORE-Connector...............................................................................93
Table 54 Document Revision History .............................................................................................................98

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2SOM Features
The phyCORE-AM62xx offers the following features:
•Insert-ready, small (43 mm x 32 mm) System on Module (SOM) subassembly in low EMI design, achieved through
advanced SMD technology
•Populated with the Texas Instruments AM62xx microprocessor (13 x 13 mm, 0.5 mm pitch BGA)
•Single supply voltage of 5V with on-board power management IC
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
•Up to 2GB DDR4 RAM
•Up to 128GB on-board eMMC
•1x Octal or Quad SPI Flash Subsystem
•1x Gigabit Ethernet PHY (signals brought out to connector as diff pairs)
•1x 32KB I2C EEPROM
•1x On-board RTC
•2x 0.5mm pitch 2x60 pin Samtec connectors that expose the following interfaces:
•2x MMC/SDIO modules
•2x USB 2.0 Ports
•1x 10/100/1000 Mbit Ethernet (signals brought out as RGMII)
•3x MCAN with CAN-FD support
•10x UART
•6x I2C
•1x JTAG debug port
•4x SPI
•3.3V/1.8V GPIOs
•4x EPWM (Enhanced Pulse Width Modulator) modules
•4x ECAP (Enhanced Capture) modules
•3x EQEP (Enhanced Quadrature Encoder Pulse) modules
•1x GPMC (General Purpose Memory Controller) module
•1x TRC (Trace) module
•1x CPTS (Common Platform Time Sync) module
•12x Timer modules
•1x CSI (Camera Serial Interface) module
•3x McASP (Multichannel Audio Serial ports) modules
•1x OLDI/LVDS (2 lanes) display module
•1x 24-bit RGB parallel display module
NOTE:
Some of the features listed are not available simultaneously due to the multiplexing options of the various
processor pins. Refer to the sections 5 – 12 of the manual for further information on available multiplexing
options and the pinout of signals.

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3Conventions, Abbreviations and Acronyms
This hardware manual describes the PCM-071 System on Module, henceforth referred to as phyCORE-AM62xx. The
manual specifies the phyCORE-AM62xx's design and function. Precise specifications for the Texas Instruments AM62xx
microprocessor can be found in the AM62xx Technical Reference Manual.
We refrain from providing detailed part specific information within this manual which can be subject to changes. This is
due to the continuous maintenance of our products. Please read 13.4 Product Change Management for more information.
The BSP delivered with the phyCORE-AM62xx includes drivers and/or software for controlling all components such as
interfaces, memory, etc. Therefore, programming close to the hardware (at the register level) is not necessary in most
cases. For this reason, this manual contains no detailed description of the processor's registers, or information relevant
for software development. Please refer to the AM62xx Technical Reference Manual if such information is needed.
3.1 Conventions
The conventions used in this manual are as follows:
•Signals that are preceded by an "n" or end in z (e.g.: nRD or RDz), are designated as active low signals. That is,
their active state is when they are driven low, or are driving low.
•A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
•The hex-numbers given for addresses of I2C devices always represent the 7 most-significant bits (MSB) of the
address byte. The correct value of the least-significant bit (LSB) will depend on the desired command (read (1) or
write (0)) and must be added to get the complete address byte. E.g. given the address in this manual 0x41 => the
complete address byte = 0x83 reads from the device and 0x82 to writes to the device
•Text in blue italics indicate a cross-reference to an internal section of this Document. Click these links to quickly
jump to the applicable part, chapter, table, or figure.
•Text in underlined in blue indicate an external link. Click these links to quickly jump to the applicable URL.
•References made to the phyCORE-Connector always refer to the high density Samtec connectors on the
undersides of the phyCORE-AM62xx System on Module.
3.2 Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms
used in this document.
Table 1 Abbreviations and Acronyms used in this Manual
Abbreviation Definition
BSP Board Support Package (Software delivered with the Development Kit including an operating system
(Linux) preinstalled on the module and Development Tools)