Qorvo Pac5527 User manual

Power Application Controller®

Rev 1.2 –Jan 17, 2019

PAC5527 Device User Guide

Power Application Controller®

Multi-Mode Power ManagerTM

Configurable Analog Front EndTM

Application Specific Power DriversTM

Arm®Cortex®-M4F Controller Core

 
 
Power Application Controller®
 
 -2- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
TABLE OF CONTENTS 
 
1OVERVIEW .......................................................................................................................11 
2STYLE AND FORMATTING CONVENTIONS....................................................................12 
2.1 Number Representation..............................................................................................12 
2.2 Formatting Styles........................................................................................................12 
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................13 
4ANALOG REGISTER ACCESS.........................................................................................14 
4.1 Overview.....................................................................................................................14 
4.2 Functional Description ................................................................................................14 
4.3 USART Configuration .................................................................................................15 
4.4 Protocol ......................................................................................................................15 
4.5 Write Register Example ..............................................................................................15 
4.6 Read Register Example..............................................................................................17 
5PAC5527 IO.......................................................................................................................18 
5.1 Overview.....................................................................................................................18 
5.2 ADC Channels............................................................................................................19 
5.3 Digital Peripheral Pins.................................................................................................20 
5.4 Analog Interrupts ........................................................................................................21 
6PAC5527 ADC MUXes ......................................................................................................22 
6.1 System Block Diagram................................................................................................22 
6.2 ADC MUX...................................................................................................................23 
6.3 AFE MUX....................................................................................................................24 
6.4 PWRMON MUX..........................................................................................................26 
7EMUX................................................................................................................................27 
8POWER MANAGER..........................................................................................................29 
8.1 Overview.....................................................................................................................29 
8.2 Features .....................................................................................................................29 
8.3 System Block Diagram................................................................................................30 
8.4 Functional Description ................................................................................................30 
8.5 VP Low Warning.........................................................................................................30 

 
 
Power Application Controller®
 
 -3- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
6 Power Manager Faults................................................................................................31 
7 Temperature Warnings and Faults..............................................................................31 
8 Register Summary......................................................................................................33 
9 Register Detail............................................................................................................34 
9.1 SOC.FAULT.........................................................................................................34 
9.2 SOC.STATUS......................................................................................................34 
9.3 SOC.MISC...........................................................................................................36 
9.4 SOC.PWRCTL.....................................................................................................37 
9.5 SOC.FAULTINTEN..............................................................................................38 
9.6 SOC.WATCHDOG...............................................................................................39 
9.7 SOC.SYSCONF...................................................................................................40 
9CONFIGURABLE ANALOG FRONT-END.........................................................................41 
1 Overview.....................................................................................................................41 
2 Features .....................................................................................................................41 
3 System Block Diagram................................................................................................42 
4 Enabling the CAFE .....................................................................................................43 
5 Entering Hibernate Mode............................................................................................43 
6 Hibernate wake-up using Wake-Up Timer...................................................................43 
7 Hibernate wake-up using Push-Button........................................................................43 
8 DAC output.................................................................................................................44 
9 VREF Output ..............................................................................................................44 
10 Hard Reset .................................................................................................................44 
11 General-Purpose Register ..........................................................................................44 
12 AIO10 .........................................................................................................................45 
12.1 System Block Diagram.........................................................................................45 
12.2 AIO1, AIO0 Digital I/O Mode................................................................................46 
12.3 AIO1, AIO0 Differential Amplifier Mode................................................................46 
12.4 AIO1, AIO0 ADC Sampling..................................................................................46 
12.5 AIO1, AIO0 Protection .........................................................................................47 
13 AIO32 .........................................................................................................................49 
13.1 System Block Diagram.........................................................................................49 
13.2 AIO3, AIO2 Digital I/O Mode................................................................................50 

 
 
Power Application Controller®
 
 -4- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
13.3 AIO3, AIO2 Differential Amplifier Mode................................................................50 
13.4 AIO3, AIO2 ADC Sampling..................................................................................50 
13.5 AIO3, AIO2 Protection .........................................................................................51 
13.6 AIO2/AIO7 Buffer.................................................................................................52 
14 AIO54 .........................................................................................................................53 
14.1 System Block Diagram.........................................................................................53 
14.2 AIO5, AIO4 Digital I/O Mode................................................................................54 
14.3 AIO4, AIO5 Differential Amplifier Mode................................................................54 
14.4 AIO5, AIO4 ADC Sampling..................................................................................54 
14.5 AIO5, AIO4 Protection .........................................................................................55 
15 AIO6...........................................................................................................................57 
15.1 System Block Diagram.........................................................................................58 
15.2 AIO6 Digital I/O Mode..........................................................................................59 
15.3 AIO6 Amplifier Mode............................................................................................59 
15.4 AIO6 Comparator Mode.......................................................................................59 
15.5 AIO6 Special Mode..............................................................................................60 
16 AIO7...........................................................................................................................61 
16.1 System Block Diagram.........................................................................................62 
16.2 AIO7 Digital I/O Mode..........................................................................................63 
16.3 AIO7 Amplifier Mode............................................................................................63 
16.4 AIO7 Comparator Mode.......................................................................................63 
16.5 AIO7 Special Mode..............................................................................................64 
16.6 AIO2/AIO7 Buffer.................................................................................................66 
17 AIO8...........................................................................................................................67 
17.1 System Block Diagram.........................................................................................68 
17.2 AIO8 Digital I/O Mode..........................................................................................69 
17.3 AIO8 Amplifier Mode............................................................................................69 
17.4 AIO8 Comparator Mode.......................................................................................69 
17.5 AIO8 Special Mode..............................................................................................70 
18 AIO9...........................................................................................................................72 
18.1 System Block Diagram.........................................................................................73 
18.2 AIO9 Digital I/O Mode..........................................................................................74 

 
 
Power Application Controller®
 
 -5- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
18.3 AIO9 Amplifier Mode............................................................................................74 
18.4 AIO9 Comparator Mode.......................................................................................74 
18.5 AIO9 Special Mode..............................................................................................75 
19 Register Summary......................................................................................................77 
20 Register Detail............................................................................................................79 
20.1 SOC.CFGAIO0....................................................................................................79 
20.2 SOC.CFGAIO1....................................................................................................80 
20.3 SOC.CFGAIO2....................................................................................................81 
20.4 SOC.CFGAIO3....................................................................................................82 
20.5 SOC.CFGAIO4....................................................................................................83 
20.6 SOC.CFGAIO5....................................................................................................84 
20.7 SOC.CFGAIO6....................................................................................................85 
20.8 SOC.CFGAIO7....................................................................................................86 
20.9 SOC.CFGAIO8....................................................................................................87 
20.10 SOC.CFGAIO9.................................................................................................88 
20.11 SOC.SIGSET...................................................................................................89 
20.12 SOC.HPDACH.................................................................................................90 
20.13 SOC.HPDACL..................................................................................................90 
20.14 SOC.LPDACH..................................................................................................90 
20.15 SOC.LPDACL ..................................................................................................90 
20.16 SOC.SHCFG1..................................................................................................91 
20.17 SOC.SHCFG2..................................................................................................92 
20.18 SOC.PROTINTEN............................................................................................93 
20.19 SOC.PROTSTAT .............................................................................................94 
20.20 SOC.DOUTSIG0..............................................................................................95 
20.21 SOC.DOUTSIG1..............................................................................................96 
20.22 SOC.DINSIG0..................................................................................................97 
20.23 SOC.DINSIG1..................................................................................................97 
20.24 SOC.CFGIO1...................................................................................................98 
20.25 SOC.SIGINTEN ...............................................................................................99 
20.26 SOC.SIGINTF................................................................................................100 
20.27 SOC.BLANKING ............................................................................................101 

 
 
Power Application Controller®
 
 -6- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
20.29 SOC.SPECCFG0...........................................................................................102 
20.30 SOC.SPECCFG1...........................................................................................103 
20.31 SOC.SPECCFG2...........................................................................................105 
20.32 SOC.SPECCFG3...........................................................................................105 
20.33 SOC.GP0.......................................................................................................106 
APPLICATION SPECIFIC POWER DRIVER................................................................107 
1 Features ...................................................................................................................107 
2 System Block Diagram..............................................................................................108 
3 Functional Description ..............................................................................................109 
4 High-Side Gate Drivers.............................................................................................109 
5 Low-Side Gate Drivers..............................................................................................110 
6 Enabling the ASPD...................................................................................................111 
7 Gate Driver Safe State..............................................................................................111 
8 Driver Protection.......................................................................................................111 
9 Cycle by Cycle Current Limit.....................................................................................112 
10 Gate Driver Short Protection..................................................................................114 
11 VP UVLO Configuration.........................................................................................114 
12 Break-before-make Configuration..........................................................................114 
13 Gate Driver Programmable Current.......................................................................115 
14 Register Summary.................................................................................................119 
15 Register Detail.......................................................................................................120 
15.1 SOC.CFGDRV1.............................................................................................120 
15.2 SOC.CFGDRV2.............................................................................................121 
15.3 SOC.CFGDRV3.............................................................................................122 
15.4 SOC.STATDRV..............................................................................................123 
15.5 SOC.DRVILIMLS............................................................................................124 
15.6 SOC.DRVILIMHS...........................................................................................125 
15.7 SOC.CFGDRV4.............................................................................................126 
15.8 SOC.DRV_FLT ..............................................................................................126 
15.9 SOC.ENDRV..................................................................................................127 
15.10 SOC.WDTPASS.............................................................................................127 
LEGAL INFORMATION................................................................................................128 

Power Application Controller®

Rev 1.2 –Jan 17, 2019

 
 
Power Application Controller®
 
 -8- Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
LIST OF FIGURES 
Figure 3-1 PAC5527 Architectural Block Diagram.....................................................................13 
Figure 4-1 PAC5527 Register Access.......................................................................................14 
Figure 4-2 Analog Peripheral Register Write Timing .................................................................16 
Figure 4-3 Analog Peripheral Register Read Timing .................................................................17 
Figure 5-1 GPIO and DPM Block Diagram................................................................................18 
Figure 6-1 PAC5527 ADC MUX inputs......................................................................................22 
Figure 7-1 EMUX Timing Diagram ............................................................................................28 
Figure 8-1 Power Manager System Block Diagram...................................................................30 
Figure 9-1 CAFE System Block Diagram ..................................................................................42 
Figure 9-2 AIO10 Block Diagram...............................................................................................45 
Figure 9-3 AIO32 Block Diagram...............................................................................................49 
Figure 9-4 AIO54 Block Diagram...............................................................................................53 
Figure 9-5 AIO6 System Block Diagram....................................................................................58 
Figure 9-6 AIO7 System Block Diagram....................................................................................62 
Figure 9-7 AIO8 System Block Diagram....................................................................................68 
Figure 9-8 AIO9 System Block Diagram....................................................................................73 
Figure 10-1 ASPD System Block Diagram..............................................................................108 
Figure 10-2 High-Side Gate Driver Block Diagram..................................................................109 
Figure 10-3 Low-Side Gate Driver Block Diagram...................................................................110 
Figure 10-4 Cycle by Cycle Current Limit................................................................................112 
Figure 10-5 High-side Gate Driver Waveforms........................................................................115 
Figure 10-6 Low-side Gate Driver Waveforms.........................................................................116 
 
 

Power Application Controller®

Rev 1.2 –Jan 17, 2019

LIST OF TABLES

Table 5-1 PAC5527 ADC Input Pins .........................................................................................19

Table 5-2 PAC5527 Digital Peripheral Pins...............................................................................20

Table 6-1 PAC5527 ADC MUX channels..................................................................................23

Table 6-2 PAC5527 ADC MUX channels..................................................................................25

Table 6-3 PAC5527 ADC MUX channels..................................................................................26

Table 8-1 Power Manager Fault Handling.................................................................................31

Table 8-2 Power Manager Register Summary...........................................................................33

Table 9-1 Hibernate Wake-Up Timer Options ...........................................................................43

Table 9-2 AIO2/AIO7 Buffer Input Select...................................................................................52

Table 9-3 AIO2/AIO7 Buffer Input Select...................................................................................66

Table 9-4 CAFE Register Summary..........................................................................................77

Table 10-1 ASPD Controlled-Current Time Configuration.......................................................117

Table 10-2 ASPD Controlled-Current Time Configuration.......................................................118

Table 10-3 ASPD Register Summary......................................................................................119

 
 
Power Application Controller®
 
 -10-Copyright 2020 © Qorvo, Inc. 
 Rev 1.2 –Jan 17, 2019 
 
LIST OF REGISTERS 
Register 8-1 SOC.FAULT (Fault Condition, 00h).......................................................................34 
Register 8-2 SOC.STATUS (System Status, 01h).....................................................................34 
Register 8-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................36 
Register 8-4 SOC.PWRCTL (Power Control, 03h)....................................................................37 
Register 8-5 SOC.FAULTINTEN (Fault interrupt enable, 04h) ..................................................38 
Register 8-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h)......................................39 
Register 8-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................40 
Register 9-1 SOC.CFGAIO0 (AIO0 Configuration, 06h)............................................................79 
Register 9-2 SOC.CFGAIO1 (AIO1 Configuration, 07h)............................................................80 
Register 9-3 SOC.CFGAIO2 (AIO2 Configuration, 08h)............................................................81 
Register 9-4 SOC.CFGAIO3 (AIO3 Configuration, 09h)............................................................82 
Register 9-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)............................................................83 
Register 9-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)............................................................84 
Register 9-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch) ...........................................................85 
Register 9-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh) ...........................................................86 
Register 9-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)............................................................87 
Register 9-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)..........................................................88 
Register 9-11 SOC.SIGSET (Signal Manager Configuration, 10h)............................................89 
Register 9-12 SOC.HPDACH (HPDAC High Setting, 11h)........................................................90 
Register 9-13 SOC.HPDACL (HPDAC Low Setting, 12h) .........................................................90 
Register 9-14 SOC.LPDACH (LPDAC High Setting, 13h).........................................................90 
Register 9-15 SOC.LPDAC1 (LPDAC Low Setting, 14h)...........................................................90 
Register 9-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)........................................91 
Register 9-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16h) .....................................92 
Register 9-18 SOC.PROTINTEN (Protection Interrupt Enable, 17h).........................................93 
Register 9-19 SOC.PROTSTAT (Protection Interrupt Status, 18h)............................................94 
Register 9-20 SOC.DOUTSIG0 (Digital Output 0, 19h).............................................................95 
Register 9-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)..............................................................96 
Register 9-22 SOC.DINSIG0 (Digital Input 0, 1Bh) ...................................................................97 
Register 9-23 SOC.DINSIG1 (Digital Input 1, 1Ch)...................................................................97 
Register 9-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)............................................98 
Register 9-25 SOC.SIGINTEN (AIO Interrupt Enable, 1Fh).......................................................99 
Register 9-26 SOC.SIGINTF (AIO Interrupt Flag, 20h)............................................................100 
Register 9-27 SOC.BLANKING (Comparator Blanking Configuration, 21h).............................101 
Register 9-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22h) ...............102 
Register 9-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23h).............103 
Register 9-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24h) ............105 
Register 9-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) ...............105 
Register 9-32 SOC.GP0 (General-Purpose Register Space, 26h)...........................................106 
Register 10-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..................................................120 