Qorvo PAC5527 User manual

Power Application Controller®
-1- Copyright 2020 © Qorvo, Inc.
Rev 1.2 –Jan 17, 2019
PAC5527 Device User Guide
Power Application Controller®
Multi-Mode Power ManagerTM
Configurable Analog Front EndTM
Application Specific Power DriversTM
Arm®Cortex®-M4F Controller Core

Power Application Controller®
-2- Copyright 2020 © Qorvo, Inc.
Rev 1.2 –Jan 17, 2019
TABLE OF CONTENTS
1OVERVIEW .......................................................................................................................11
2STYLE AND FORMATTING CONVENTIONS....................................................................12
2.1 Number Representation..............................................................................................12
2.2 Formatting Styles........................................................................................................12
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................13
4ANALOG REGISTER ACCESS.........................................................................................14
4.1 Overview.....................................................................................................................14
4.2 Functional Description ................................................................................................14
4.3 USART Configuration .................................................................................................15
4.4 Protocol ......................................................................................................................15
4.5 Write Register Example ..............................................................................................15
4.6 Read Register Example..............................................................................................17
5PAC5527 IO.......................................................................................................................18
5.1 Overview.....................................................................................................................18
5.2 ADC Channels............................................................................................................19
5.3 Digital Peripheral Pins.................................................................................................20
5.4 Analog Interrupts ........................................................................................................21
6PAC5527 ADC MUXes ......................................................................................................22
6.1 System Block Diagram................................................................................................22
6.2 ADC MUX...................................................................................................................23
6.3 AFE MUX....................................................................................................................24
6.4 PWRMON MUX..........................................................................................................26
7EMUX................................................................................................................................27
8POWER MANAGER..........................................................................................................29
8.1 Overview.....................................................................................................................29
8.2 Features .....................................................................................................................29
8.3 System Block Diagram................................................................................................30
8.4 Functional Description ................................................................................................30
8.5 VP Low Warning.........................................................................................................30

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Rev 1.2 –Jan 17, 2019
8.6 Power Manager Faults................................................................................................31
8.7 Temperature Warnings and Faults..............................................................................31
8.8 Register Summary......................................................................................................33
8.9 Register Detail............................................................................................................34
8.9.1 SOC.FAULT.........................................................................................................34
8.9.2 SOC.STATUS......................................................................................................34
8.9.3 SOC.MISC...........................................................................................................36
8.9.4 SOC.PWRCTL.....................................................................................................37
8.9.5 SOC.FAULTINTEN..............................................................................................38
8.9.6 SOC.WATCHDOG...............................................................................................39
8.9.7 SOC.SYSCONF...................................................................................................40
9CONFIGURABLE ANALOG FRONT-END.........................................................................41
9.1 Overview.....................................................................................................................41
9.2 Features .....................................................................................................................41
9.3 System Block Diagram................................................................................................42
9.4 Enabling the CAFE .....................................................................................................43
9.5 Entering Hibernate Mode............................................................................................43
9.6 Hibernate wake-up using Wake-Up Timer...................................................................43
9.7 Hibernate wake-up using Push-Button........................................................................43
9.8 DAC output.................................................................................................................44
9.9 VREF Output ..............................................................................................................44
9.10 Hard Reset .................................................................................................................44
9.11 General-Purpose Register ..........................................................................................44
9.12 AIO10 .........................................................................................................................45
9.12.1 System Block Diagram.........................................................................................45
9.12.2 AIO1, AIO0 Digital I/O Mode................................................................................46
9.12.3 AIO1, AIO0 Differential Amplifier Mode................................................................46
9.12.4 AIO1, AIO0 ADC Sampling..................................................................................46
9.12.5 AIO1, AIO0 Protection .........................................................................................47
9.13 AIO32 .........................................................................................................................49
9.13.1 System Block Diagram.........................................................................................49
9.13.2 AIO3, AIO2 Digital I/O Mode................................................................................50

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9.13.3 AIO3, AIO2 Differential Amplifier Mode................................................................50
9.13.4 AIO3, AIO2 ADC Sampling..................................................................................50
9.13.5 AIO3, AIO2 Protection .........................................................................................51
9.13.6 AIO2/AIO7 Buffer.................................................................................................52
9.14 AIO54 .........................................................................................................................53
9.14.1 System Block Diagram.........................................................................................53
9.14.2 AIO5, AIO4 Digital I/O Mode................................................................................54
9.14.3 AIO4, AIO5 Differential Amplifier Mode................................................................54
9.14.4 AIO5, AIO4 ADC Sampling..................................................................................54
9.14.5 AIO5, AIO4 Protection .........................................................................................55
9.15 AIO6...........................................................................................................................57
9.15.1 System Block Diagram.........................................................................................58
9.15.2 AIO6 Digital I/O Mode..........................................................................................59
9.15.3 AIO6 Amplifier Mode............................................................................................59
9.15.4 AIO6 Comparator Mode.......................................................................................59
9.15.5 AIO6 Special Mode..............................................................................................60
9.16 AIO7...........................................................................................................................61
9.16.1 System Block Diagram.........................................................................................62
9.16.2 AIO7 Digital I/O Mode..........................................................................................63
9.16.3 AIO7 Amplifier Mode............................................................................................63
9.16.4 AIO7 Comparator Mode.......................................................................................63
9.16.5 AIO7 Special Mode..............................................................................................64
9.16.6 AIO2/AIO7 Buffer.................................................................................................66
9.17 AIO8...........................................................................................................................67
9.17.1 System Block Diagram.........................................................................................68
9.17.2 AIO8 Digital I/O Mode..........................................................................................69
9.17.3 AIO8 Amplifier Mode............................................................................................69
9.17.4 AIO8 Comparator Mode.......................................................................................69
9.17.5 AIO8 Special Mode..............................................................................................70
9.18 AIO9...........................................................................................................................72
9.18.1 System Block Diagram.........................................................................................73
9.18.2 AIO9 Digital I/O Mode..........................................................................................74

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
9.18.3 AIO9 Amplifier Mode............................................................................................74
9.18.4 AIO9 Comparator Mode.......................................................................................74
9.18.5 AIO9 Special Mode..............................................................................................75
9.19 Register Summary......................................................................................................77
9.20 Register Detail............................................................................................................79
9.20.1 SOC.CFGAIO0....................................................................................................79
9.20.2 SOC.CFGAIO1....................................................................................................80
9.20.3 SOC.CFGAIO2....................................................................................................81
9.20.4 SOC.CFGAIO3....................................................................................................82
9.20.5 SOC.CFGAIO4....................................................................................................83
9.20.6 SOC.CFGAIO5....................................................................................................84
9.20.7 SOC.CFGAIO6....................................................................................................85
9.20.8 SOC.CFGAIO7....................................................................................................86
9.20.9 SOC.CFGAIO8....................................................................................................87
9.20.10 SOC.CFGAIO9.................................................................................................88
9.20.11 SOC.SIGSET...................................................................................................89
9.20.12 SOC.HPDACH.................................................................................................90
9.20.13 SOC.HPDACL..................................................................................................90
9.20.14 SOC.LPDACH..................................................................................................90
9.20.15 SOC.LPDACL ..................................................................................................90
9.20.16 SOC.SHCFG1..................................................................................................91
9.20.17 SOC.SHCFG2..................................................................................................92
9.20.18 SOC.PROTINTEN............................................................................................93
9.20.19 SOC.PROTSTAT .............................................................................................94
9.20.20 SOC.DOUTSIG0..............................................................................................95
9.20.21 SOC.DOUTSIG1..............................................................................................96
9.20.22 SOC.DINSIG0..................................................................................................97
9.20.23 SOC.DINSIG1..................................................................................................97
9.20.24 SOC.CFGIO1...................................................................................................98
9.20.25 SOC.SIGINTEN ...............................................................................................99
9.20.26 SOC.SIGINTF................................................................................................100
9.20.27 SOC.BLANKING ............................................................................................101

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
9.20.29 SOC.SPECCFG0...........................................................................................102
9.20.30 SOC.SPECCFG1...........................................................................................103
9.20.31 SOC.SPECCFG2...........................................................................................105
9.20.32 SOC.SPECCFG3...........................................................................................105
9.20.33 SOC.GP0.......................................................................................................106
10 APPLICATION SPECIFIC POWER DRIVER................................................................107
10.1 Features ...................................................................................................................107
10.2 System Block Diagram..............................................................................................108
10.3 Functional Description ..............................................................................................109
10.4 High-Side Gate Drivers.............................................................................................109
10.5 Low-Side Gate Drivers..............................................................................................110
10.6 Enabling the ASPD...................................................................................................111
10.7 Gate Driver Safe State..............................................................................................111
10.8 Driver Protection.......................................................................................................111
10.9 Cycle by Cycle Current Limit.....................................................................................112
10.10 Gate Driver Short Protection..................................................................................114
10.11 VP UVLO Configuration.........................................................................................114
10.12 Break-before-make Configuration..........................................................................114
10.13 Gate Driver Programmable Current.......................................................................115
10.14 Register Summary.................................................................................................119
10.15 Register Detail.......................................................................................................120
10.15.1 SOC.CFGDRV1.............................................................................................120
10.15.2 SOC.CFGDRV2.............................................................................................121
10.15.3 SOC.CFGDRV3.............................................................................................122
10.15.4 SOC.STATDRV..............................................................................................123
10.15.5 SOC.DRVILIMLS............................................................................................124
10.15.6 SOC.DRVILIMHS...........................................................................................125
10.15.7 SOC.CFGDRV4.............................................................................................126
10.15.8 SOC.DRV_FLT ..............................................................................................126
10.15.9 SOC.ENDRV..................................................................................................127
10.15.10 SOC.WDTPASS.............................................................................................127
11 LEGAL INFORMATION................................................................................................128

Power Application Controller®
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Rev 1.2 –Jan 17, 2019

Power Application Controller®
-8- Copyright 2020 © Qorvo, Inc.
Rev 1.2 –Jan 17, 2019
LIST OF FIGURES
Figure 3-1 PAC5527 Architectural Block Diagram.....................................................................13
Figure 4-1 PAC5527 Register Access.......................................................................................14
Figure 4-2 Analog Peripheral Register Write Timing .................................................................16
Figure 4-3 Analog Peripheral Register Read Timing .................................................................17
Figure 5-1 GPIO and DPM Block Diagram................................................................................18
Figure 6-1 PAC5527 ADC MUX inputs......................................................................................22
Figure 7-1 EMUX Timing Diagram ............................................................................................28
Figure 8-1 Power Manager System Block Diagram...................................................................30
Figure 9-1 CAFE System Block Diagram ..................................................................................42
Figure 9-2 AIO10 Block Diagram...............................................................................................45
Figure 9-3 AIO32 Block Diagram...............................................................................................49
Figure 9-4 AIO54 Block Diagram...............................................................................................53
Figure 9-5 AIO6 System Block Diagram....................................................................................58
Figure 9-6 AIO7 System Block Diagram....................................................................................62
Figure 9-7 AIO8 System Block Diagram....................................................................................68
Figure 9-8 AIO9 System Block Diagram....................................................................................73
Figure 10-1 ASPD System Block Diagram..............................................................................108
Figure 10-2 High-Side Gate Driver Block Diagram..................................................................109
Figure 10-3 Low-Side Gate Driver Block Diagram...................................................................110
Figure 10-4 Cycle by Cycle Current Limit................................................................................112
Figure 10-5 High-side Gate Driver Waveforms........................................................................115
Figure 10-6 Low-side Gate Driver Waveforms.........................................................................116

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
LIST OF TABLES
Table 5-1 PAC5527 ADC Input Pins .........................................................................................19
Table 5-2 PAC5527 Digital Peripheral Pins...............................................................................20
Table 6-1 PAC5527 ADC MUX channels..................................................................................23
Table 6-2 PAC5527 ADC MUX channels..................................................................................25
Table 6-3 PAC5527 ADC MUX channels..................................................................................26
Table 8-1 Power Manager Fault Handling.................................................................................31
Table 8-2 Power Manager Register Summary...........................................................................33
Table 9-1 Hibernate Wake-Up Timer Options ...........................................................................43
Table 9-2 AIO2/AIO7 Buffer Input Select...................................................................................52
Table 9-3 AIO2/AIO7 Buffer Input Select...................................................................................66
Table 9-4 CAFE Register Summary..........................................................................................77
Table 10-1 ASPD Controlled-Current Time Configuration.......................................................117
Table 10-2 ASPD Controlled-Current Time Configuration.......................................................118
Table 10-3 ASPD Register Summary......................................................................................119

Power Application Controller®
-10-Copyright 2020 © Qorvo, Inc.
Rev 1.2 –Jan 17, 2019
LIST OF REGISTERS
Register 8-1 SOC.FAULT (Fault Condition, 00h).......................................................................34
Register 8-2 SOC.STATUS (System Status, 01h).....................................................................34
Register 8-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................36
Register 8-4 SOC.PWRCTL (Power Control, 03h)....................................................................37
Register 8-5 SOC.FAULTINTEN (Fault interrupt enable, 04h) ..................................................38
Register 8-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h)......................................39
Register 8-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................40
Register 9-1 SOC.CFGAIO0 (AIO0 Configuration, 06h)............................................................79
Register 9-2 SOC.CFGAIO1 (AIO1 Configuration, 07h)............................................................80
Register 9-3 SOC.CFGAIO2 (AIO2 Configuration, 08h)............................................................81
Register 9-4 SOC.CFGAIO3 (AIO3 Configuration, 09h)............................................................82
Register 9-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)............................................................83
Register 9-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)............................................................84
Register 9-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch) ...........................................................85
Register 9-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh) ...........................................................86
Register 9-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)............................................................87
Register 9-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)..........................................................88
Register 9-11 SOC.SIGSET (Signal Manager Configuration, 10h)............................................89
Register 9-12 SOC.HPDACH (HPDAC High Setting, 11h)........................................................90
Register 9-13 SOC.HPDACL (HPDAC Low Setting, 12h) .........................................................90
Register 9-14 SOC.LPDACH (LPDAC High Setting, 13h).........................................................90
Register 9-15 SOC.LPDAC1 (LPDAC Low Setting, 14h)...........................................................90
Register 9-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)........................................91
Register 9-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16h) .....................................92
Register 9-18 SOC.PROTINTEN (Protection Interrupt Enable, 17h).........................................93
Register 9-19 SOC.PROTSTAT (Protection Interrupt Status, 18h)............................................94
Register 9-20 SOC.DOUTSIG0 (Digital Output 0, 19h).............................................................95
Register 9-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)..............................................................96
Register 9-22 SOC.DINSIG0 (Digital Input 0, 1Bh) ...................................................................97
Register 9-23 SOC.DINSIG1 (Digital Input 1, 1Ch)...................................................................97
Register 9-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)............................................98
Register 9-25 SOC.SIGINTEN (AIO Interrupt Enable, 1Fh).......................................................99
Register 9-26 SOC.SIGINTF (AIO Interrupt Flag, 20h)............................................................100
Register 9-27 SOC.BLANKING (Comparator Blanking Configuration, 21h).............................101
Register 9-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22h) ...............102
Register 9-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23h).............103
Register 9-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24h) ............105
Register 9-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) ...............105
Register 9-32 SOC.GP0 (General-Purpose Register Space, 26h)...........................................106
Register 10-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..................................................120

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
Register 10-2 SOC.CFGDRV2 (Driver Configuration 2, 28h) ..................................................121
Register 10-3 SOC.CFGDRV3 (Driver Configuration 3, 29h) ..................................................122
Register 10-4 SOC.STATDRV (Driver Status, 2Ah) ................................................................123
Register 10-5 SOC.DRVILIMLS (Low-side Driver Current Limit Configuration, 79h) ...............124
Register 10-6 SOC.DRVILIMHS (High-side Driver Current Limit Configuration, 7Ah) .............125
Register 10-7 SOC.CFGDRV4 (Driver Configuration 4, 7Bh)..................................................126
Register 10-8 SOC.DRV_FLT (Driver Fault Flat, 7Ch)............................................................126
Register 10-9 SOC.ENDRV (Driver Manager Enable, 7Dh) ....................................................127
Register 10-10 SOC.WDTPASS (WDT Password, 7Eh).........................................................127
1 OVERVIEW
This document is the PAC5527 Device User Guide. It details the operation of the analog
peripherals in the PAC5527.
For detailed information on the MCU and Digital Peripherals in the PAC5527, see the PAC55XX
Family User Guide.

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
2 STYLE AND FORMATTING CONVENTIONS
This chapter describes the formatting and styles used throughout this document.
2.1 Number Representation
Numbers other than decimal will have a postfix indicator. All numbers use little endian
formatting, with the most significant bit/digit to the left. Digits for binary and hexadecimal
representation are grouped with a single space every four digits to improve readability. Binary
numbers use “b” as a postfix and hexadecimal numbers use “h” as a postfix.
For example, 1011b binary = Bh hexadecimal = 11 decimal.
2.2 Formatting Styles
TYPE
EXAMPLE
DESCRIPTION
Register Name
RTCCTL
Register names use a capital letter and boldface type.
Register Bit(s)
RTCCTL.RTCCLKDIV
Register bits are always represented with the register name
separated with a period.
Function selected by
register bit(s)
[RTCCTL.RTCCLKDIV]
Within text blocks, functions selected with a register bit setting are
set in brackets. For example [RTCCTL.RTCCLKDIV] means divider
settings /2 to /65536.
Pin Function
PA5
Pin functions use capital letters
Internal signals
PWMA3
Internal signals use italicized font.
Formulas
CLK = FCLK / DIV
Formulas use monospaced text.
Links
Link
Hyperlinks are underlined and blue.
CPU Mnemonic
MRS
CPU Mnemonic uses monospaced text.
Operands
{Rd, }, Rn, Rm
Operands use monospaced italic text.
Code examples
b loopA
Code examples use monospaced text.

Power Application Controller®
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3 ARCHITECTURAL BLOCK DIAGRAM
For Below is an architecture block diagram of the PAC5527 device.
Figure 3-1 PAC5527 Architectural Block Diagram
PAC SOC BUS
POWER
MANAGER
HVCP
LINEAR
REGULATORS
VM
VCP
CPL
VP
SW1
VCCIO
VCORE
VCC33
DRHx
DRSx
HSGD (3)
DRLx
LSGD (3)
APPLICATION
SPECIFIC
POWER
DRIVERS
CONFIGURABLE
ANALOG
FRONT-END
AIO
CONTROL
(10)
DAC (2)
PGA/
CMP (7 )
DIFF-PGA
PCMP (3)
AMPx/
CMPx/
PHCx
DAxP/
PCMPx
DAxN
ADx
AIOx
BUF6
PBTN
CPH
VSS
PAC5527
Power Application Controller
VSYS
MVBB SW2
128kB FLASH
32kB SRAM
CLOCK
CONTROL
RTC/Calendar
GPIO
USART (3)
I2C
CAN
SYSTEM
CONTROL
APB/AHB
PX.Y
DEBUG/
ETM
ARM
CORTEX-M4F
CORE
TIMERS (4)
DEAD TIME
(16)
PWM/CC (32)
PWM ENGINE
BRIDGE
WWDT
DTSE
DATA ACQUISITION
AND SEQUENCER
12-BIT
ADC
MUX
3 x 1kB FLASH
PX.Y
PX.Y
PX.Y
PX.Y
PX.Y
VCC18
GP TIMER (2)

Power Application Controller®
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4 ANALOG REGISTER ACCESS
4.1 Overview
All analog registers in the PAC5527 are accessible through a SOC bus in the device. Unlike
registers in the MCU (SRAM and digital peripheral registers), these analog registers are not
memory mapped.
The block diagram below shows the different system busses that the MCU uses to access the
different system registers.
Figure 4-1 PAC5527 Register Access
SWD
Cortex-M4F
MCU
PAC5527
Debug
Port AHB/APB
Bridge Analog
Peripherals
GPIOAUSARTA
Memory
Controller
JTAG
AHB APB
Other
Digital
Peripherals
DPM
GPIO[A..G]
The PAC5527 contains two register buses: the AHB bus and the APB bus.
The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory
Controller. To access other digital peripheral connected to the APB bus, there is a bridge from
the AHB to the APB bus so that the MCU or Debug Port can perform memory-mapped register
access to all digital peripherals. Some digital peripherals such as timers are flexibly connected
to IO using the DPM bus.
To access the Analog peripherals, the USARTA SPI peripheral is used to generate read and
write transactions to the Analog registers using the DPM and GPIOA.
4.2 Functional Description
External programming interfaces such as JTAG and SWD or the Arm®Cortex®-M4F MCU may
perform memory-mapped accesses to USART A through the AHB and APB busses on the
device.

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
USART A is a serial communication peripheral that supports a SPI-like protocol that can be
used to communicate to the Analog Peripherals for read and write transactions. The Digital
Peripheral MUX (DPM) may be configured to connect the USART A SPI signals to GPIO A,
where they are connected to the Analog peripherals.
4.3 USART Configuration
USART A acts as a SPI bus master to communicate with the Analog Peripherals. The USART A
signals that are used for this communication are:
▪USASCLK –USART A SPI Clock
▪USAMOSI –USART A Master-Out/Slave-In
▪USAMISO –USART A Master-In/Slave-Out
▪USASS –USART A Slave Select
In order to communicate with the Analog Peripherals, the USART A should have the following
configuration:
▪8-bit mode
▪SCLK active high
▪CPH is sample/setup
▪SS active low
When communicating with the Analog Peripherals, the maximum SCLK frequency is 25MHz.
4.4 Protocol
The protocol for communicating with the Analog Peripherals is a simple two-byte protocol.
The first byte is always the address, which includes a 7-bit address [7:1] and a write bit [0]. For
write operations, the write bit [0] is set to 1b. For read operations, the write bit [0] is set to 0b.
For write operations, the 2nd byte will be the 8-bit data to write to the given address.
For read operations, the 2nd byte is ignored and MISO will contain the 8-bit data read from the
given address.
4.5 Write Register Example
To write the HPDAC register (address 2Bh) with the value 28h, issue the following transactions
to USART A:
▪Write SSPADAT with the value 57h (2Bh << 1 | 1b for write transaction)
▪Write SSPADAT with the value 28h
The timing diagram from a write operation is shown below.

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
Figure 4-2 Analog Peripheral Register Write Timing

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
4.6 Read Register Example
To read the contents of the HPDAC register, issue the following transactions to USART A:
▪Write SSPADAT with the value 56h (2Bh << 1 | 0b for read transaction)
▪Write SSPADAT with a dummy character
▪Read last data from MISO from SSPADAT, this is the register value
The timing diagram from a read operation is shown below.
Figure 4-3 Analog Peripheral Register Read Timing
For more information on how to configure the DPM to support the USART A peripheral for
communicating with the Analog Registers, see the PAC55XX Family User Guide.

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
5 PAC5527 IO
5.1 Overview
The Digital Peripheral MUX (DPM) on the PAC55XX family allows flexible assignment of
peripheral functions to IO pins.
Each member of the family has a different set of IO pins that are available. It is important during
application design that the designer consider the available IO pins to make sure the necessary
peripherals will be available.
Below is a diagram of the GPIO and MUX structure.
Figure 5-1 GPIO and DPM Block Diagram
Each IO can be configured to select 1 of up to 8 digital peripheral signals. Some IOs also may
be used as an ADC input. For information on how to configure the IO for each of these
situations, see the PAC55XX Family User Guide.
The PAC5527 has the following IO pins available for application use:
▪PA[7:0] –Reserved for MMPM, ASPD, CAFE
▪PB[7:0] –Reserved for ASPD
▪PD[7:4]
▪PE[3:0]
▪PF[7:0]

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
5.2 ADC Channels
The ADC channels that are available on the PAC5527 are shown in the table below.
Table 5-1 PAC5527 ADC Input Pins
ADC Channel
IO PIN
ADC0
PG71
ADC4
PF4
ADC5
PF5
ADC6
PF6
ADC7
PF7
1
Available for sampling channels in the CAFE only

Power Application Controller®
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Rev 1.2 –Jan 17, 2019
5.3 Digital Peripheral Pins
The digital peripheral functions that are available in the PAC5527 are shown below.
Table 5-2 PAC5527 Digital Peripheral Pins
PORT
Pin
GPIOxMUXS.Py
000b
001b
010b
011b
100b
101b
110b
111b
GPIOA
P0
GPIOA0
P1
GPIOA1
EMUXD
P2
GPIOA2
EMUXC
P3
GPIOA3
USASCLK
USBSCLK
P4
GPIOA4
USAMOSI
USBMOSI
P5
GPIOA5
USAMISO
USBMISO
P6
GPIOA6
USASS
USBSS
P7
GPIOA7
GPIOB
P0
GPIOB0
TAPWM0
TBPWM0
TCPWM0
TDPWM0
P1
GPIOB1
TAPWM1
TBPWM1
TCPWM1
TDPWM1
P2
GPIOB2
TAPWM2
TBPWM2
TCPWM2
TDPWM2
P4
GPIOB4
TAPWM4
TBPWM4
TCPWM4
TDPWM4
P5
GPIOB5
TAPWM5
TBPWM5
TCPWM5
TDPWM5
P6
GPIOB6
TAPWM6
TBPWM6
TCPWM6
TDPWM6
GPIOD
P4
GPIOD4
TBPWM4
TCPWM4
TDQEPIDX
TBQEPIDX
USDSCLK
TRACED3
USDMOSI
P5
GPIOD5
TBPWM5
TCPWM5
TDQEPPHA
TBQEPPHA
USDSS
CANRXD
USDMISO
P6
GPIOD6
TBPWM6
TCPWM6
TDQEPPHB
TBQEPPHB
USDMOSI
CANTXD
I2CSDA
P7
GPIOD7
TBPWM7
TCPWM7
USDMISO
CANRXD
GPIOE
P0
GPIOE0
TCPWM4
TDPWM0
TAIDX
TBIDX
USCSCLK
I2CSCL
EMUXC
P1
GPIOE1
TCPWM5
TDPWM1
TAPHA
TBPHA
USCSS
I2CSDA
EMUXD
P2
GPIOE2
TCPWM6
TDPWM2
TAPHB
TBPHB
USCMOSI
CANRXD
EXTCLK
P3
GPIOE3
TCPWM7
TDPWM3
FRCLK
USCMISO
CANTXD
GPIOF
P0
GPIOF0
TCPWM0
TDPWM0
TMS/SWDCLK
TBIDX
USBSCLK
TRACECLK
P1
GPIOF1
TCPWM1
TDPWM1
TMS/SWDIO
TBPHA
USBSS
TRACED0
P2
GPIOF2
TCPWM2
TDPWM2
TDI
TBPHB
USBMOSI
TRACED1
P3
GPIOF3
TCPWM3
TDPWM3
TDO
FRCLK
USBMISO
TRACED2
P4
GPIOF4
TCPWM4
TDPWM4
TCIDX
USDSCLK
TRACED3
EMUXC
P5
GPIOF5
TCPWM5
TDPWM5
TCPHA
USDSS
EMUXD
P6
GPIOF6
TCPWM6
TDPWM6
TCPHB
USDMOSI
CANRXD
I2CSCL