Quasonix QSX-RDMS Series User manual

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Installation and Operation Manual
QSX-RDMS-x-xxxx
Multi-Mode Trellis Receiver / Demodulator / Bit
Synchronizer
Rev. 1.2
18 August 2008
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TABLE OF CONTENTS
1.0 INTRODUCTION ...................................................................................................... 3
1.1 DESCRIPTION ............................................................................................................................................................................ 3
1.2 NOMENCLATURE ......................................................................................................................................................................4
2.0 INSTALLATION INSTRUCTIONS............................................................................ 5
2.1 MECHANICAL............................................................................................................................................................................. 5
2.2 THERMAL ...................................................................................................................................................................................7
2.3 ELECTRICAL ..............................................................................................................................................................................7
3.0 OPERATING INSTRUCTIONS................................................................................. 9
3.1 POWER-ON OPERATION..........................................................................................................................................................9
3.2 RDMS SERIAL CONTROL PROTOCOL................................................................................................................................... 9
3.2.1 Tier 0 (PCM/FM), Tier I (SOQPSK-TG), and Tier II (Multi-h CPM) Commands ..................... 10
3.2.2 PSK Commands .......................................................................................................................... 12
4.0 PERFORMANCE SPECIFICATIONS..................................................................... 14
4.1 RF INPUT ..................................................................................................................................................................................14
4.2 DC INPUT ..................................................................................................................................................................................14
4.3 RF FREQUENCY ERROR........................................................................................................................................................14
4.4 BIT ERROR RATE .................................................................................................................................................................... 14
4.5 SYNCHRONIZATION ...............................................................................................................................................................15
5.0 MAINTENANCE INSTRUCTIONS.......................................................................... 17
6.0 IF MODULE............................................................................................................ 18
7.0 TECHNICAL SUPPORT & RMA REQUESTS ....................................................... 21
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1.0 INTRODUCTION
1.1 Description
This document describes the installation and operation of the Quasonix QSX-RDMS-x-
xxxx multi-mode trellis receiver / demodulator / bit synchronizer (referred to throughout this
document as the “RDMS”). The RDMS is designed to demodulate RF signals in several
formats:
•PCM/FM (ARTM Tier 0)
•SOQPSK-TG (ARTM Tier I)
•Multi-h CPM (ARTM Tier II or ARTM CPM)
•Legacy (PSK) suite, including
oBPSK
oQPSK
oOffset QPSK (OQPSK)
oAsymmetric QPSK (AQPSK)
oUnbalanced QPSK (UQPSK)
oAsymmetric Unbalanced QPSK (AUQPSK)
oDigital PM
The RDMS provides true trellis demodulation in ARTM Tier 0, Tier I, and Tier II modes,
delivering BER performance within 0.2 dB of theory. It also provides a clock signal (two
clock signals in the AQPSK and AUQPSK modes), obviating the need for any outboard bit
synchronizer.
The RDMS is manufactured by:
Quasonix, LLC
5493 Union Centre Drive
West Chester, OH 45069
CAGE code: 3CJA9
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1.2 Nomenclature
The RDMS is available in a number of variations, depending on the options specified at the
time of order. The features and modes installed in each unit are identified in the model
number, as depicted in Figure 1 below.
Figure 1. Receiver Types and Options.
The available options include:
•AB Airborne package (4.00” x 3.00” x 1.00”)
•NV Non-volatile memory
•RM 19-inch rack-mount (blank front panel)
•FP Keypad & display on front panel (requires RM package)
•DUAL Two receivers in one rack mount chassis (requires RM)
For example, a model QSX-RDMS-L-1101-AB is configured as follows:
QSX Quasonix product
RDMS Receiver / Demodulator / Bit Synchronizer
L L-band operation
1101 Tier 0 present, Tier I present, Tier II absent, Legacy (PSK) present
AB Airborne package
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2.0 INSTALLATION INSTRUCTIONS
2.1 Mechanical
Unless the RM (rack-mount) option is specified, the RDMS is designed to be mounted by
eight (8) 6-32 screws through the holes along the front and back edges, as depicted in
Figure 2 on the following page.
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Figure 2. RDMS in 4.00” x 3.00” x 1.00” Airborne Housing.
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2.2 Thermal
It is important that the RDMS be kept within its specified operating range of -40°C to
+70°C. At maximum bit rates, the unit dissipates approximately 12 watts. At normal
ambient room temperatures, a small fan blowing across the top cover is adequate. Higher
ambient temperatures will require more airflow and/or a finned heat sink on the cover.
2.3 Electrical
The RDMS has three external connectors, an MDM-15 male for all baseband interfaces, a
female SMA connector for the RF input, and a second female SMA connector for an IF
output. Note that initial shipments of the RDMS did not include the IF output. The pin
numbering and wiring for the MDM-15 male connector is shown in Figure 3. MDM-15 Pin
Numbers.
Figure 3. MDM-15 Pin Numbers.
Pin
Signal
Description
1
Disconnected
Pin disconnected.
2
GND
Primary power return, 2 amps maximum. Internally tied to pins 3, 6, and 10.
3
Signal GND
Ground return for TTL clock and data signals. Internally tied to pins 2, 6, and
10.
4
Data Out
Primary 3.3 volt TTL data output for all modes.
5
Clock Out
Primary 3.3 volt TTL clock output for all modes.
6
232 Ground
Ground return for RS-232 control lines. Internally tied to pins 2, 3, and 10.
7
Demod Lock
Out
3.3 volt TTL lock detector output for all modes.
8
232 Tx Output
RS-232 responses to host controller
9
+28VDC
Primary 28 VDC power to module, 0.7 amps maximum current drain.
10
GND
Secondary power return, 2 amps maximum. Internally tied to pins 2, 3, and 6.
11
Power ON
Power on reset pin. Temporarily grounding this pin is equivalent to power
cycling the module.
12
Data 2 Out
Secondary 3.3 volt TTL data output for all modes. This pin carries identical
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data to pin 4 in all modes except QPSK, UQPSK, AQPSK and AUQPSK, where
it carries the second channel data.
13
Clock 2 Out /
Ones Detector
Out
Secondary 3.3 volt TTL clock output for all modes. This pin carries identical
clock to pin 4 in all modes except QPSK, UQPSK, AQPSK and AUQPSK,
where it carries the second channel clock.
In sync test mode, this pin carries the ones detector output (see section xxx).
14
SDI Out
Signal degradation indicator, for interface to RF Networks model 2241 Diversity
Branch Selector.
15
232 Rx Input
RS-232 commands from host controller.
Table 1. Pin Assignments.
By default, the output data is valid on the falling edge of the clock, as shown in Figure 4.
The polarity of the output clock may be inverted by use of the “CP 1” command (see
below).
Bit period
(360 deg)
User asserts data on rising edge
of TTL clock, rising edge of
ECL clock+ signal, or rizing
edge of TIA/EIA422 "A" clock
generator terminal
Clock jitter and data to clock
skew reference point
Tx samples DATA on
falling edge of TTL clock,
falling edge of ECLclock(+)
signal, or falling edge of
TIA/EIA422 "A" clock
terminal.
data=1 (MARK)
data=0 (SPACE)
CLOCK
NRZL
DATA
Baseband Signal Timing - 0 degree clock
data=1 (MARK)
Figure 4. Baseband Signal Timing.
The RF input to the receiver module is a 50 Ohm interface, with VSWR less than 1.4:1.
The RDMS also provides a 70 MHz IF output through an SMA connector for
troubleshooting purposes. The IF is resistively coupled from the input of the demodulator.
Therefore, the signal level on the IF output should be within 2 dB of the demodulator’s
input.
The IF output must have a 50-ohm load at all times. Therefore, if it is not connected to
external test equipment, then the 50-ohm terminator that comes installed on the port must
remain attached.
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3.0 OPERATING INSTRUCTIONS
3.1 Power-on Operation
When the RDMS is powered up it defaults to a modulation based on what mode(s) are
installed. For units with more than one modulation present, the default is determined by the
following table.
Startup Order
Modulation
1
Legacy PSK
2
PCM/FM (Tier 0)
3
SOQPSK (Tier I)
4
Multi-h CPM (Tier II)
Table 2. Default Modulation Startup.
For units with the non-volatile memory option (NV) present, the RDMS will only default to
the modulation according to the preceding table when a modulation is not saved in the
Flash memory by the user.
3.2 RDMS Serial Control Protocol
The RDMS is controlled via a simple three-wire serial interface (transmit, receive, and
ground). Configure your controller’s serial port to the following settings:
•Baud rate of 115,200
•8 bits
•No parity
•1 stop bit
For setup and configuration via a standard Windows-based PC, Quasonix recommends
the use of Terminal, a flexible, full-featured control interface that is included in the RDMS
Product CD. Otherwise, one can use HyperTerminal, included with the standard Windows
installation (Start -> All Programs -> Accessories -> Communications -> HyperTerminal).
If you have your terminal program active when you apply power to the RDMS, you will see
a welcome message as shown in Figure 5 below.
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Initializing...
downconverter init...
Quasonix Demod/Receiver Interface
IRIG-106 Release 07
5493 Union Centre Drive
West Chester, Oh 45069
[phone]
www.Quasonix.com <http://www.Quasonix.com>
CAGE CODE: 3CJA9
FPGA Revision: 0x3132 0x0000
PSK FW Revision: 2.0.043 7/29/2008
PSK>
Figure 5. RDMS Welcome Message.
All commands are one or two alphabetic characters, followed by 0, 1, or 2 arguments. If the
command is issued with arguments, there must be a space after the alphabetic characters.
The commands are not case sensitive.
All commands generate a response of one or more lines. The length of the response
depends on the verbosity level (set by the VL command). The last response line is always
the currently selected mode (PCMFM, SOQPSK, CPM, or PSK), followed by the character “+”
or “>”, depending on the version of the firmware. This prompt signifies that the RDMS is
ready to accept new characters.
3.2.1 Tier 0 (PCM/FM), Tier I (SOQPSK-TG), and Tier II (Multi-h CPM) Commands
Mnemonic
Name
Description
?
Help Message
Displays abbreviated list of available commands
FR
Frequency
Report or set receiver center frequency.
Examples:
FR Report the frequency setting
FR 2200.5 Set modulation to 2200.5 MHz
MO
Modulation
Report or set modulation setting.
Examples:
MO Report the modulation setting
MO 0 Set modulation to PCM/FM
MO 1 Set modulation to SOQPSK-TG
MO 2 Set modulation to Multi-h CPM
MO 3 Set modulation to PSK
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BR
Bit Rate
Report or set baseband bit rate
Examples:
BR Report the bit rate setting
BR 20 Set bit rate to 5 Mbps
BR 0.6 Set bit rate to 600 Kbps
DP
Data Polarity
Report or set data polarity inversion state
Examples:
DP Report the polarity inversion state
DP 0 Set data inversion off
DP 1 Set data inversion on
CP
Clock Polarity
Report or set clock polarity inversion state
Examples:
CP Report the clock source state
CP 0 Set clock inversion off
CP 1 Set clock inversion on
GO
Start/Restart
Initiate demodulation with current parameters. This
command is required when setting both the
modulation and the bit rate.
SV
Save Parameters
(Requires NV
option)
Saves the current parameters in non-volatile
memory, including frequency, modulation, bit rate,
data polarity, clock polarity, AGC state, verbosity
level, etc.
RE
Restart
Demodulator
Restart Demodulator without reconfiguration
SC
Saturation Count
Report the saturation count
PL
Input Power Level
Report current input power level
VL
Verbosity Level
Report or set verbosity level, on a scale of 0 – 9.
Examples:
VL Report the verbosity level
VL 0 Set the verbosity level to 0
VL 5 Set the verbosity level to 5
BM
Bit Rate
Measurement
Report bit rate measurement
RV
FPGA & Firmware
Revision
Report the revision numbers for both the FPGA load
and the Firmware load
RN
Derandomizer
State
Report or set the derandomizer state.
Examples:
RN Report the derandomizer state
RN 0 Set the derandomizer off
RN 1 Set the derandomizer on
SQ
Signal Quality
Report the signal quality information
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DS
SDI Status
Report the SDI (System Degradation Indication)
status required for the RF Networks 2241 Diversity
Branch Selector
TH
TRL High Mark
Report or set the TRL high mark, on a scale from
0.0 – 5.0.
Examples:
TH Report the TRL high mark level
TH 0.2 Set the TRL high mark to 0.2
TH 4.9 Set the TRL high mark to 4.9
TL
TRL Low Mark
Report or set the TRL low mark, on a scale from 0.0
– 5.0.
Examples:
TL Report the TRL low mark level
TL 0.1 Set the TRL low mark to 0.1
TL 3.7 Set the TRL low mark to 3.7
VF
Viterbi Forget
Factor
Report or set the Viterbi forget factor, on a scale
from 0.01 – 0.99.
Examples:
VF Report the Viterbi forget factor
VF 0.04 Set the Viterbi forget factor to 0.04
VF 0.62 Set the Viterbi forget factor to 0.62
VS
Viterbi Status
Report the Viterbi lock status and strength
PS
Show Parameters
Displays all parameters
AA
AGC State
Report or set the receiver’s automatic gain control
(AGC).
Examples:
AA Report the AGC state
AA 0 Set AGC off
AA 2 Set AGC on
Table 3. Tiers 0 / I / II Basic Serial Commands.
3.2.2 PSK Commands
Mnemonic
Name
Description
?
Help Message
Displays abbreviated list of available commands
FR
Frequency
Report or set receiver center frequency.
Examples:
FR Report the frequency setting
FR 2200.5 Set modulation to 2200.5 MHz
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MO
Modulation
Report or set modulation setting.
Examples:
MO Report the modulation setting
MO 0 Set modulation to PCM/FM
MO 1 Set modulation to SOQPSK-TG
MO 2 Set modulation to Multi-h CPM
MO 3 Set modulation to PSK
BR
Bit Rate
Report or set baseband bit rate
Examples:
BR Report the bit rate setting
BR 20 Set bit rate to 5 Mbps
BR 0.6 Set bit rate to 600 Kbps
DP
Data Polarity
Report or set data polarity inversion state
Examples:
DP Report the polarity inversion state
DP 0 Set data inversion off
DP 1 Set data inversion on
CP
Clock Polarity
Report or set clock polarity inversion state
Examples:
CP Report the clock source state
CP 0 Set clock inversion off
CP 1 Set clock inversion on
GO
Start/Restart
Initiate demodulation with current parameters
RE
Restart
Demodulator
Restart Demodulator without reconfiguration
SC
Saturation Count
Report the saturation count
PL
Input Power Level
Report current input power level
VL
Verbosity Level
Report or set verbosity level, on a scale of 0 – 9.
Examples:
VL Report the verbosity level
VL 0 Set the verbosity level to 0
VL 5 Set the verbosity level to 5
BM
Bit rate
Measurement
Report bit rate measurement
SV
Save Parameters
(Requires NV
option)
Saves the current parameters in non-volatile
memory, including frequency, modulation, bit rate,
data polarity, clock polarity, AGC state, verbosity
level, etc.
RV
FPGA &
Firmware
Revision
Report the revision numbers for both the FPGA
load and the Firmware load
Table 4. Legacy PSK Basic Serial Commands.
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4.0 PERFORMANCE SPECIFICATIONS
4.1 RF Input
The RDMS is available in three bands:
Lower L-band models: 1435.5 to 1534.5 MHz
Upper L-band models: 1750.0 to 1855.0 MHz
S-band models: 2200.5 to 2394.5 MHz
The input impedance is 50 ohms, with a VSWR of less than 1.5:1.
4.2 DC Input
In its airborne configuration, the RDMS operates from 28 VDC, with a current consumption
of no more than 0.7 amps. The rack mount models are powered from standard 120 VAC
power.
4.3 RF Frequency Error
By default, the RDMS is capable of acquiring a signal with a frequency error of up to ±100
kHz.
4.4 Bit Error Rate
The RDMS meets the following BER limits, when tested with a signal source which
complies with IRIG 106-05.
Maximum Eb/N0 (dB)
BER
PCM/FM, Tier 0
SOQPSK-TG, Tier I
Multi-h CPM, Tier II
10-3
7.5
9.5
11.0
10-4
9.0
11.5
12.5
10-5
10.0
13.0
13.5
10-6
11.0
14.5
14.5
Table 5. RDMS BER Specifications.
Typical BER performance, plotted in Figure 6, is significantly superior to that tabulated
above.
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Figure 6. BER Performance for Tier 0, I, and II.
4.5 Synchronization
The RDMS offers very fast, reliable acquisition, even at very low signal to noise ratio.
Synchronization time is function of modulation type and IF frequency error. Typical
SOQPSK results (from 10,000 synchronization trials) are shown below.
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Figure 7. Synchronization Time at Various Signal-to-Noise Ratios.
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5.0 MAINTENANCE INSTRUCTIONS
The RDMS requires no regular maintenance, and there are no user-serviceable parts
inside. Please consult the factory for any maintenance, upgrade, or repair requirements.
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6.0 IF MODULE
The built-in IF filter module, shown in Figure 8, has 8 SAW filters, ranging in bandwidth
from 250 kHz to 40 MHz in approximately one-octave steps. These filters serve as anti-
aliasing filters ahead of the A/D converter in the demod itself. In addition, they can provide
an added measure of adjacent channel interference rejection. The measured responses of
the 8 filters are shown in Figure 9 and Figure 10 (note the change of horizontal scale
between the two Figures).
Figure 8. 70 MHz IF Module in 2” x 3” Chassis.
The IF module attaches directly to the demod modules.
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Figure 9. SAW Filter Responses, Narrow Group (Plotted on 10 MHz Span).
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