Radio Shack TRS-80 Product manual

•
ltadl8IhaeK
TECHNICAl REFERENCE
MANUAl
TRs-ao®
MODEl Il
Catalog Number 26-4921
Revised Floppy Disk Controller
~~
,-.-
CUSTOM MANUFACTUREO IN U.S.A. SV RAOIO SHACK A DIVISION OF TANDV CORPORATION

•IMPORTANT NOTICE
This Technical Reference Manual is written for owners of the TAS-BO
Modelll Microcomputer who have athorough understanding of electronics
and computer circuitry.
It is not written to the beginner's level of
comprehension.
Radio Shack will
not be fiable for aoy damage caused, or alleged to be
caused. by the customer or aoy other persan using this technical maoual to
repair, modify. or alter the TRS-aD Model Il Computer in aoy manner.
Many parts of the com"puter eleetronics are very sensitive and can be easily
damaged b:v improper servicing. We strongly suggest that for proper
servicïng, the computer be returned to Radio Shack.
While this technical maoual has been carefully preparee!. Radio Shack will
not be responsible for aoy BfTOrs or omissions and will not be fiable for
damages resulting from the use of information contained herein.
Because of the sensitivity of computer equipment, and the potential
problems which can result from improper servicing, the following limitations
apply to services offered by Radio Shack:
1. If any of the warranty seals on any Radio Shack computer products are
broken, Radio Shack reserves the rîght to refuse to service the equipment
or to void any remaîning warrant y on the equipment.
2. If any Radio Shack corTlputer equipment has been modified 50 that it is
not within manufaeturer's specifications, including, but not limited to,
the installation of any non-Radio Shack parts, components, or replace-
ment boards, then Radio Shack reserves the right to refuse to service the
equipment. void any remaining warranty. remove and replace any
non-Radio Shack part found in the equipment, and perform whatever
modificatio~s are necessary to return the equipment to original factory
manufacturer's specifications.
3. The cost for the labor and parts required to return the Radio Shack
computer equipment to its original manufacturer's specifications will be
charged to the customer in addition to the normal repaîr charges.
Floppy Disk Controller Technical Reference Manual:
©1981 Tandy Corporation. Fort Worth. Texas 76102 U.S.A.
Ali Righcs Reserved.
Reproduction or use. without express wrilten permiSSIon
from
Tandy Corporation, of any portion of this manual is
prohibited. While reasonable efforts have been ta ken in the
preparation of this manual to assure its accuracy. Tandy
Corportition assumes no liability resulting from any errors
or omissions in this manual, or from the use of the infonna-
tion obtained herein.
•
•
•

A. FUNcnONAL SPECIFICATIONS
The Model Il Fleppy Disk Controller (FOC) Board has baen
redesigned
ta take advanlage of anew chip set. the W01691
and W02143. This chip set provides more flexible write
precompensation (conlinuously adjustable from
1;\ ns la 350 ns)
and asimpler adjustment procedure lor Ihe dalalcJock recovery
circuit.
The new design provides
two independent drive inlerlaces.
one lor
the internai drive and an additianal interface for up ta
Ihree exlernal drives. This aHaws the system ta slarl·up
properly without damage to
the system diskette even if the
external drives are
not turned on.
There is also
no need for the disk terminaler adaptor. currently
required for single-drive systems. Aprovision to generate a
software master
resello the W01791 was also added (an OUT
inslruction to port
EBH). This allows recovery Irom hang-up
conditions which rarelyoccur ln
the W0179X family parts.
The redesigned FOC board Is fully soltware campalible wilh
the previous design. wilh Ihe exception Ihat an additianal port
is provided lar Ihe saltware master resel funclion. Aredesign
of lhe inlernal disk cable syslem is reqUired. sînce Ihers are
naw Iwo Independent
Elrive interfaces. Field upgrades with
redesigned FOC boards will also require the new cable syslem
ta be installed.
B. THEORY OF OPERA noN
Decodlng loglc
The FOC-PAINTEA INTERFACEBOARDis an 110 (inpul-oul,t ut)
port map device wnich ulilizes ports E0H. El H, E2H. E3H. EuH.
E5H, E6H. E7H, E8H and EFH.
Table 1summarizes Ihe port allocation lor the 1I0ppy controller
board. Port-mapped devices use anly Ihe lower eight addrfSS
bits la sp&cify whlch port is being addressed.
The upper eight address bils
are ignored completely and s re
nal relevant 10 por(-mapped devices. nuee olher sigm!ls
(WA·. AD' and lOCY') are used by port-mapped devices ta
datermine whelher an 1/0 operation is la accur. lf WA' a.,d
IOCYC' are both law, Ihis condition deflnes an aUI,tut
aperalion in progress.
Figure 6
(FOC schematic diagram) should now be relerrad la
for
the remainder of Ihe Oeeodlng Logic discussion.
U21, pin
B. is Ihe oulpul of afour-input NANO gale. This l'ln
should be low when any 01 the ports E0H through EFH é ra
being addressed. U21, pin 6. is also an oulput 01 a lour-in~ ul
NANO
gale which shauld go low when the pori belilg
addressed cantains an FHEX in Ihe low·order nibble 01 tle
port address.
Table 1. Port AllocaUon
PORT #
ALLOCATION
fUNCTION
E0H Pla Port A - Data
Printer and fOC INT.
status
E1H PlO Port B -
Oata
Printer Oat<l (output)
E2H PlO Port A - Control Configuring Port A
E3H
Pla Port B - Control Configuring Port 8
E4H FOC Status/CMO Register
FOC Status and CMO
E5H FOC Track Register Current Track Add.
E6H
FOC Sector Register Current Sector Add.
E7H FOC
Data Register Data To or From
Oiskette
EaH Soft
fOC Resel Out Resets fOC
EFH Drive
Select Latch Drive, Mode, Side
Select
1

These two outputs, labeled XF' and EX', are combined at pins
4
and 5 01 U22. U22. pin 6 Is Ihe decoder lor the drive-select
(U11) mapped
at port EFH. This oulput is combined witt'! our
at U22, pins 9 and la ta produce Ihe signallabeled DRVSEl'
at U22, pin B.
The rising edge 01 DRVSEL" is used by pin 9of un ta latch
the data present
on the internai data bus corresponding ta an
output ta pon EFH. This data pattern is used ta determine the
drive, mode, and side selection. The bit allocation for this laten
is detailed
in Tlble 2.
The signal labeled EX' is used as an enable 10 gate Ihe
addresses
A31 and A21 to the control inputs 01 U23 (Binary ta
Decimal Decoder.) The slgnats A31 and A2t. atong with At! and
AQt lorm the inputs to the decoder U23. U23, pins 1. 2. 3. 4. 5.
6.7.9 and 10 are the outputs which produce Ihe ehip enabtes
lor the PlO,
FOC, and soit reset togie.
The pon decode tabeted ES" is combined with the signal our
at U34 pins 1 and 2. The resultlng signal Irom U34 pin. 3is
combined with RE$ETI'
al U14, pins 12 and 13. The output 01
U14, pin 11 is atow-going strobe which resets U1S if an output
ta port
EBH is exeeuted or the front"panet reset switch is
actuated.
CPUIN is asignal generated
by the decoding logic for the
purpose 01 switchlng the direction of the data bus transceivers
(U30. U31) in preparation lor an input operation.
There
are two conditions which require the data bus trans-
celvers
to switch direction such that they drive data outward 10
the system data bus:
(1) Port input operation
(2) Inlerrupt acknowledge cycte
The port-input operation is detected by the combination of
Bny
01 the ports EOH through E7H being addressed concurrer Uy
with an Input operation in progress.
U34, pin '11 will go low when this condition is deteeted. Il
SYNCI' and IOROI' are both tow. this condition indicates an
interrupt acknowtedge cycle is in progress and Ihat t1e
înterrupting device should present ils vactor
to the data bus.
Intermpl priority 15 determined by Ihe signallEtN (pin 13 01 t;'le
system bus).
If IEIN is hlgh during an inlemJpt acknowtedge cycle, no device
01 higher prlorlty is requesting service and the requesh 19
device may bring ils lEOUT tow to prevent devlces of 10'A er
prjority Irom receiving service. Ahigh on pin 1 of US indicates
an inlerrupt acknowtedge cycle Is in progress. Ahign on pir 2
of
U5 indicales no higher priority device is requesting service.
Ahigh on pin t3 01 US indlcales adevice on Ihis board is
requestlng service.
Il ail these conditions are true, pin
12, US (INTAK') will go JON.
This output is combined with the output Irom pin 11 of U13 al
pins 4 and 5 01 U14. If eilher pin 4 or pin 5 of U14 goes ION.
then pin 6 01 U14 will also go low. U2 inverts this signal and "in
1201 U2 will go high (CPUIN). Il CPUtN is high, the dala bJS
transceivers disabte their receivers and enable their drivers to
gate data onto the system data bus. This allows the PlO 10
transfer ils inlerrupt vector to the CPU.
Table 2. BIT Allocation
Port EFH, Drive Select Latch (output only)
07 06 05
O,
03 02 01
De
Mode Select Side Select Ulll,lsed Ullused
DRV3SEl DRV2SEl
DAV1SEl
DRV0SEl
t'J" FM Mode
0"Side 1
1" NOTSEL 1'" NOTSEL ,
.. NOTS El
, "NOTSEl
1'" MFM Mode
1::Side0
0" SEL
~:: SEL
0" SEL
~ '" SEL
NOTE: D3 lhrouqh D0 -only one of these bits should be low per output instruction.
2

Bue Interface Loglc
Good design practice dictates most signaIs to and Iram the
system bus must be butlered so anly one
TIL load per board
is presented
10 each nan-inverting buffer lor lhe Z-80 control
signais. This buHering
Is accomplished by U32 and U33. (Noie:
The enables tor both these parts are lied low. allowing these
signais
10 be driven onlo the board at ail times. Open collector
devices are
use<! 10 drive the outputs to the bus which may be
driven by other boards, INTRO" and XFERRO.)
There is abasic problem with using aZ-80/P10 with the
WD1791. The PlO has anan-inverting dala bus white the
W01791 utilizes an inverting data bus. One extra stage ot
inversion is required
lar the W01791. U19 and U20 accomplish
this extra inversion. These transceivers are normally receivlng
data but are enabled ta drive data toward the system bus when
an input operation (rom the ports assigned ta
the FOC is in
progress.
Z-80/PIO
Interface Loglc
The Z-80 parallel 110 (Pla) interface controller is agenera
purpose, programmable, Iwo-port device which provides m
compatible intertacing between peripheral devices and thE
Z-80 CPU.
Any al the follawing modes can be selected for either port:
byte output
byte Input
byte bi-directionaJ A(port Aonly)
byte or control mode
ln addition, the PlO provides aelean and minimallogie methoc
for generating mode 2interrupts ta the Z-80 CPU.
Port Ais used in the control
mode, which allows the eight 110
lines (A0 through A7) la be configured as either inputs or
outputs. An eight·bit mask reglster and aIwo-bit mask control
reglster
aHow interrupts ta he generated. dependent on the
lagic states of the 1/0
Unes. Port Ais primarity used for slatus
checking and generating interrupts.
07
Printer Busy
0= Not Busy
1=Busy
04
Primer Faull
0'" Fault
1= Not Fault
Table
3. BIT Allocation
Port E'H. Printer, FOO, FOC Interrupt Statu'
06
Paper Empty
" = Paper not Empty
1= Paper Empty
03·
PRIME
High ta Law
Transition
Resets Printer
01
Two·Sided Oiskette
1'" Two-Sided Oiskette Preset
CJ =Single-Sided Oiskette
05
Printer Select
0= Selected
1'" Not Selected
02·
Oisk Change
0= Ooor nol OpenCfI
1=Ooor Opened
Dt
FOC lNT REQUEST
1=FOC is Interrupting
0'" Not Inlerrupting
°02 indicates that the selected drive has nad its dOOf opene<! since it was tast selected.
°03 is an output which resets sorne printers.
3

One 110 line is conligured as an oulput and provides the
"prime" signal lor
the printer interface. The bit allocations for
this port are detailed in Table 3.
POO Bis used in Ihe output mode lor the purpose 01 outpulling
characters
to the printer. Tha outputs 01 port B (BO through B7)
are isolated lrom
the printer with an octal noninverting buffer,
U4. (Note: The anables
are tled low, 9atin9 whatever data is
presented ta the inputs 01 U4 directly ta its outputs. The printer
cable system roules this parallel data
ta the printer,)
Pin 21 of the PlO (U12), labeted BRDV, produces ahigh·
going pulse which indicates valid data is present
on tha port B
outputs. The rising edge
olthis pulse provides atrigger for pin
3of
U6. U6 is aone-shot which produces 1.5 .... 5low-going
pulse
at pin 4when triggered.
The rising edge
01 the 1.5 .... sstrobe is used by the printer ta
latch Ihe eight bits of parallel data present atthe outputs 01 U4.
The BRDY signal stays active until Ihe rising edge 01 PACK'
(which indicates
the printer has accepted Ihe data). The rising
edge may also generale an interrupt
il port Bhas been
programmed
la use interrupls. This provides an eflicienl
method
for ~etermining when the printer can accept anew
charactar withoui using
status·chec~ing loops.
The PlO interfaces direclly la the system bus with a'minimum
of external componenls.
00 through 07 (U12) form abi-
directional data path
to the syslem bus. The signais labeled
AQlI and A 11 deterrnine which port is addressed and whether
the data transfer is intended lor the command register.
Il CEPIO·, 10AOI·. and ROI' are alllow, an input operation is
in progress. If CEPIO· and IOROI· are low with ROI· high, an
output operation is in progresS. Il IEIN is high. and INTROI·,
SVNCI', IOROI' and IEO are low,
an interrupt ac~nowledge
cycle for the PlO 15 in progress. Il SYNCI' is high and RESTI'
is
low, a Iow is produced at pin 8 01 U14. Il this sequence
occurs withoul ROI' and IOROI·
low, the PlO Iogic enters a
reset state.
For a more detalled discussion of the PlO
operation, consullthe Zilog Z-8fIJIP/O TechnicaJ Manua/.
Dlak Bu •• Selector loglc
The Model Il Floppy Disk-Printer Interface Board supports up
10 lour drives (one internai, three eXlernal). This function is
implemented
by using Iwo disk-drive interface busses, one for
the internai drive and one lor Ihe externat drives. J0 is the
connector used
lor the inlernal drive and P1 is the edge
connector
usecl for the external drives.
4
U17 and U16 (quad IWo-ta-one data selectors) are used ta
select which set of inpuls from the disk drive busses are rou:ed
ta the 1791 FOC chip, Pin 1 01 bath parts are the control pins
lor the data seleclor.
11 U17, pin 1 and U 16, pin 1are high, lhe
external inputs are selected. Alow selects the internaI inpu' s.
This control signal (Iabeled INT'IEXTl Is derived Irom he
outputs of adeclmal decoder (U36). U36 uses Ihe Iower hur
bits ollhe drive·select latch (U 11) as its inputs to decocle which
drive is selected. The decoder used
in lhis way prevents mo}re
than one drive Irom being selected al atime.
ReedlWrlte Data Pulse Shaplng
Loglc
Two one-shots (112 01 U15 and 1/2 al U6) are used to enslJre
the read and wrile dala pulses are approximately 250 ns in
duration
DI.k Buas Output Driver.
U25 and U1 QI are high-current open collector drivers use<! 10
bulter the oulput signais lrom the drive select latch and Ihe
FOC chip ta the 1I0ppy dis~ drives. (Schematic note: Ecch
output signal ta the drives has Iwo bullers associated ~ iÎh
each signal -one
set is used lor :he internai drive buss and
the other set is used lor the external drive buss. No selectlo}ic
is required for Ihese output signaIs since the drive select toits
define which drive is active.)
Wrlte Precompensatlon and Clock Recovery Loglc
U28 (WD1691), U29 (W02143) and
U24 (lS629), along witt! a
lew passive eomponents, comprise the write precompensatiOfl
and read clock recovery lagic.
The W01691 is an
lSI device which minimizes the extemal
laglc required ta inlerface the
1791 FOC chip ta adisk dri,'e.
With ltle use al
an external VCO (U24), the WD1691 will derive
the RClK signal lor the 1791, while providing an adjustmllnt
signal for the
VCQ, to keep the RClK synchronous with t'le
read data Irom the drive.
Write precompensation control signais are also provlded
by lne
W01691 la Inlerface directly
10 the W02143 (U29) clcc~
generalor.
The read clock recovery section
01 the WD1691 has live n-
puts: OOEN, VCQ, RoO·, WG and VFOE·; and three oulpUlS:
PU, PO· and RClK. The inputs VFOE" and WG, when be,lh
low, enable the clock recovery lagie. When WG is high, awrrle
operation is
in progress and the dock recovery circuits cre
disabled regardless 01 the stale 01 any other inputs.
The
wrile precompensalion section 01 the WD1691 W1S
deslgned ta he used wilh the WD2143 cloc~ generator. Wrte
precompensalion
is not used in single-density mode and tle
signal DOEN when high indicates Ihis condition,

ln cIolIblEroensily mode (ODEN =0), the signais EARLYand
LATE are used
10 select aphase input (01'-04') on the leading
edge of WDIN. The STe lina is lalchad high when this occurs.
causing the WD2143 to slart ils pulse generalion. 02· is used
as the wrile data pulse on nominal (EARLY=
LATE =Il). 01" 18 used lOf the early and 03' tS used lor the laie.
The leading edge of 04' rasets the STe lina in anHcipalion of
the neX! dala pulse. When TG43 =0or DDEN: 1, precom-
pensation is disabled and any transitions on the WOIN line will
eppear on the WOQUT lina.
When VFOE' and WG are (ow, the dock recovery circuits are
enabled. When the RDO" line goe5 low, lhe PU or PD" signais
will become active.
Il
the ROC" line ha5 made Ils transllion in the beginnlng 01 the
RCLK window, PU will go Irom ahigh impedance stale to a
loglc one, requesting
an Increase in VCO frequency. Il the
ROO" line has made its transition at lhe end ot the RClK
window, PU will remain in the high impedance slale while PO'
will
go to alagic zero, requesling adecrease in the VCO
frequency.
When lhe leading edge
01 ROO' occurs in the center 01 the
RCLK window, bath PU and PO" will remain in lhe high impe-
dance slale, indicating that no adjustmenl ot lhe VCO Ire-
quency is required. By tying
PU and PO" together. an ad just-
ment signal is created which will be forcecl low lor adecrease
in
VCO Irequency and lorcecl high lOf an increase in VCO
Irequency.
To speed up rise limes and stabîlize the output voltage. a
resislor dîv\der, usîng R2. A21 and A24, is used to adjusl lhe
tri-stale level
al apprOlcimately 1.4V. This adjuslment results in
aworsl case voilage swing ot
+! -1V, which Îs acceplable lor
the Irequency control input of the VCO (U24).
This signal derived Irom
the combination 01 PU and PD" will
eventually correct the VCO input to exactty
the same frequency
multiple as the AoO" signal. The leading edge 01 the AOD·
signal will then occur in
the exact center 01 the AClK window,
an ideal condition for the 1791 internai recovery circuits.
wo
,
,
•
no
•
woo~
•
"'
---
VFOE/WF
•
tG.J
•
..,
'"
"
"
"
"
"
"
"
"
'"
B-
RelK
CONTROL
H
..
1r
2.-:/
'u
cow
pvcc
.,
P"'U
FIL rEJl
ODEN
P" ,...-
."
pLAn
PEARL'!'
1-
~T(;4J
g.,o ..
--
PIIECQM
POCH"
"'FOE
"'FOE
-
lOGIC
"
..
,W,
OEl'IUX
ClOClC
p.o
"
..
p.u
rr=
,
.0
PRCLK
E""LY
LATCM
1
WCI ..
p~
"""'"
L"'H
WODUT
'"
Figure 1, WD1691 Block Dlagr.m
5

W01791 -Floppy Olek Controller IC
The W01791 is an MOS LSI device which perfarms tha
functions 01 aFloppy Disk formaUcontroller in asingle-chip
Implementation.
The W01791 cantains aH Ihe features 01 its predecessor, the
1771, plus the added leatures necessary to read, write and
lormat adouble-denslty dlskelte. These include: address mark
detecllon,
FM and MFM encode and decode lagie, window
extension
and write precompensalion.
WD1791 OrgenlZllUon
The Floppy oisk Formaller black diagram Is iIIustraled ln
Figure
2. The primary seclions include Ihe parallel Processor
Interface
and the Floppy olsk interface.
Oeta Shlft Reglster -This eight,bil resister assembles seriai
data Irom the Read Data input (RAW REAO) du ring Read
operations and transI ers seriai data la the Write Data output
during Wrile operations.
-1
"" 1
.,
_ .... "
.......
,~ .. ·,,·oo
-
...
•
•
•
•
Oeta Reglet.r -This eight-bil register 15 used as aholding
reglster during Oisk
Read and Wrile operations. In Disk Rud
operations, the assembled data byte Is transrerred in paraUelto
the Data Register Irom the Data Shift Aegister. In Disk Write
operations, inlormation
is translerred in parallel Iram the Data
Reglster
to the Data Shift Register. When executing the Seek
command, the Data Reglsler halds the address 01 tha desir9d
track position. This register can be Ioaded rrom the OAl and
gated onlo the
DAl under processor control.
Treck Regleter -This eight·bit regisler ho Ids the track
number 01 the current Read/Wrila head position. It is
Incremented
by one every lime the head Is steppe<! in (towards
Track
76) and decremented by one when the head is stepp:!d
ouI (Iawards Track 0). The contents 01 the register are
compared with the record track number
in the ID field duri1g
disk
Read, Write and Verily operations. The Track Regis'er
can
be Ioaded Irom or translerrad ta the oAl. This Regis' er
should not be loaded when the FOC is busy.
Sector Regleter (SR) -This eighl-bit register holds Ile
address of the desired seclor position. The contents 01 11e
reglster are compared with the recorded seclor number in Ile
-l
LJ
'--------- .. '
•
' ..
-
•
•
-
-
..
,.,.",.
'00'-
.".
-•
. _,
....
-,
..
.'
Figure 2. WD1791 Black Dlegr.m

JO field during disk Read or WrÎte operations. The Sector
Regisler contents
can be loaded Irom or translerred la the
DAl. This register should nol be loaded when the FOC is busy.
Command Reglster (CRI -This eight·bil regisler holds the
command presently being execuled. This regisler should riot
be loaded when the FDC is bU!iy except ta load aforce
lnlerrupt
commando This action results in an inlerrupl. The
command register can be loaded from the DAL bul not read
onlo
the OAL
Status Aeglater (STRI -This eight·bil register holds device
Slalus information. The meaning of lhe Status bits is afunction
of lhe conlents ot the Command Regisler. This register can be
read onto the OAL but not loaded from the DAL
CRC logle -This lagie is used to check or to generate lhe
16-bit Cyclic Redundancy Check (CRC).
The CRC includes ait
inlormation starllng with
the address mark and up to the CRC
characters. The CRC register is present 10 ones (l's) prior 10
data belng shitled through Ihe circuit.
Arlthmetlc/loglc Unit (AlU) -The ALU is aseriai
comparator. încrementer and decrementor, Il ls used for
register modification and comparisons with
the disk recorded
ID lield.
Timing and Control - Ali computer and Floppy Oisk interface
controls are generated throughout Ihe
10gic. The interna)
device timing is generated from
an external clock,
The
1791 has two differenl modes 01 operation. according to
Ihe stale of DOEN. When ODEN = O. double dansîly (MFM) is
assumed. When DDEN =
1. single density (FM) is assumed.
AM Detector -This address mark deteclor delecls tD. data
and index address marks during Read and Wrile operations.
Proeessor Interface
The interface
ta the processor is accomplished lhrough the
eight Data Access Lines (oAl) and associated control signaIs.
The
OAL are used to transler DaIa. Slatus and Control word
out of. or into, the F01791.
The DAl are lhree·state bulfers that are enabled as oulput
drivers when Chip Enable (CE')
and Read Enable (RE') are
active (Iow·\ogic state) or act
as inpul receivers when CE' and
Write Enable (WE') are active.
When transler
of data la the Floppy Disk Controller is requir&1
by the host processor. the devtce address is decoded and CE'
is made low. The least-slgnifieanl address bits A1 and AIJ..
combined with the signais RE' during aRead operation or WE'
during aWrite operation. are Interpteted
as selecting lh.!
foJlowing registots:
Port
Addreaa
Al·AI Read (RPI
Wrlte (WeO)
A1
AO
E4H
00Stalus Regisler Command Register
ESH
01Track Register Track Regisler
EBH 10Sector Register Sector Reglster
E7H
1 1 Data Regisler
Data Register
Table
4. Reglater Sheet
Ouring Direct Memory Access (OMA). lypes
of data transfer~,
betweBrl the Data Register of the FD1791 and lhe DMA. lhl'
Oata Raquest (DAO) output is used in data Transler control
This signal aise appears
as status bit 1during Read and Wrilt
operations,
On Disk Read operation. the Data Aaquest is activated (se
high when
an assembled seriai input byte is translerred ir
parallelto the Data Aegister). This bit is
c1eared when the DaI.
Register is read by the processer Of DMA controller,
If the Data Register is read alter one or more characlers arf
lost (by having new data ttanslerred into the reglster prior tc
the processer readout). the lost Data bit is set in the Statu!
Regist8f. The Read operalion continues until the end 01 Ihf
sector is reached.
On Disk Write operalions. lhe Data Requesl is activated wher
the Data Register translers
Its contents to the Data Shil'
Regisler
and requires anew data byte, lt Is resel when the
Data Shifl Register is loaded with new data by the processor 01
DMA conltoller.
Il new data
Is not loaded at the time the next seriai byte i~
required by the Floppy Oisk. abyte al zeroes ig wrilten on the
diskelte and the lost Data bit is set in the Slatus Aegister.
At the completion of every command,
an JNTRO is genetated.
INTRO is reset by either reading the status register or
b-y
loading the command register with anew commando In
addition. INTRQ is generated when aForce Interrupl command
condilion
is met
7

8
Floppy DIBk Interface
The W01791 has
two modes 0..!....E.E:!ratlon. according to the
state 01 OoEN (pin 37). When DDEN = 1. single density ls
selecte<:!. When DDEN ::: G. double density is selecte<!. In
ei(her case. the ClK input (pin 24) is at 2 MHz. When the clock
is al 2MHz, Ihe stepping rates of
3, 6, 10, and 15 ms are
obtainable if TEST"
::: 1.
Head POBltlonlng
Four commands cause positioning
01 the Read·WrÎte head
(reler ta the
FOI 79X-C2 Data Sheet published by Western
Digital.)
The period 01 each posilioning step is specilied by Ihe
rfjeld
in bits 1and 0of the command ward.
After
the tast directional step. an additional 15 miUiseconds
(ms) of head-selling lime takes place if the Verily
flag is sel ln
Type 1commands. (Note: This time doubles ta 30 ms for a 1
MHz clock.)
If TEST '" 0, there is zero-selling time. There is
also a15ms head-setling lime il the EIlag is set in any Type Il
or III commando
The rates (shown ln Table 5) can be applied to aStep-
Direcllon Motor lhrough the device inlerface.
Step - A
2~s (MFM) or 4!J.s (FM) pulse 1s provided as an
output ta the drive. For every step pulse issued, the drive
moves one track location
in adirection delermined by the
direclional output.
DirectIon (DIRe) -The Direction signal
is active high when
stepping
in and low wl"ten stepping out. The Direction signal is
vaUd 121-1.s belore lhe first stepping pulse ls generated.
When aSeek. Step or Restore command is executed.
an
optional verification of ReadlWrite Mad position can be
performed
by setling bit 2(V = 1) in the command ward ta a
laglc
,.
The verification operation bagins atthe end 01 the 151-1.s sel1ing
lime after the head is loaded against lhe media. The track
numbar for the lirsl encountered
ID Field is compared against
the contents
01 the Track Regisler.
Il the track
numbers compare and the ID Field CycliC
Redundancy Check (CAC) is correct, the verily operation
is
complele and an INTRO is generated with no errors. The 1791
must lind an ID lield with acorrect track number and a
correct CAC within live revolulions of the media: otherwise,
the
seek error is set and an INTRO is generated.
The foilowing example explains the use al the Stepping Raies
Table:
If Clock is 2MHz and ï5DtN (double density nol) is h gh
(1) and il bit Al is low (0) white bit AD is high (1) and TEST is
high (1), then
the stepping lime will be six mslstep.
CLK 2MHz: 2MHz 1MHz
lMHz 2MHz lMHz:
DDEN 0101X X
R1AO TEST TEST TEST TEST TEST TEST
=1 =1 =1 =1 =0 =0
0 0 3ms 3ms 6ms 6ms Approx. Appro<.
016ms 6ms
12 ms 12 ms
200IL
S
400!J.~:
1• 10 ms 10 ms 2G ms 20 ms
1 1
15 ms 15 ms
30 ms
30 ms
Table
S. Stepplng Rates
The Head load (HlD) oulput contrais lhe movement of . he
ReadIWrite head against the media. HlD is activaled at he
beginning of aType 1command if lhe hllag is set (h '" 1), at
the end of the Type 1command il the verity Ilag is sel (V = 1),
or upon receipt of any Type Il or III commando Once HlD is
active, it remalns active until either aType 1command is
received wilh
(h ::: 0 and V '" 0); or il the F01791 is an l,jle
state (non-busy) and 15 Index pulses have occurred, il is res ~l.
Head load Timing (HLn is an input to the Fo1791 which is
used tor the head engage lime.
When HlT = 1, the F01791
assumes the head is completely engaged.
The head engage
lime is typically
30 la 65 ms, depending on the specification!; 01
Ihe drive used.
"CO ., __ ---.J
l~ '0 >O'·'ir-------
Head L08d Timing
The low la high transition on HlD is used ta lire a one shot (1/2
01 U15). This one shot has alime perlod of approximatfdy
50ms. The output of the one shot is then used lor
Hl T a ld
supplied as an Input to the 1791.
When bath HlD and Hl Tare lrue, the 1791 will then read Ire m
or write 10 lhe media. The "and" 01 HlD and Hl T ~ppears a~ a
slalus bit
in Type 1stalus.
ln summary for the Type 1commands: 1/ h'" 0and V ::: 0.
HlD is sel at the beginning 01 the command and Hl Tis roI
sampled nor is there an internai 15ms delay. Il h'" 0and V'"
1, HlD Is set near the end 01 the command, an internai 15ns
delay occurs, and Ihe FD1791 waits lor HU la ba true. "h -
1
and V - 1. HlD is set al the beginning al the commando