Ramtron VersaKit-30 Series User manual
VersaKit-30xx
User Guide Rev 2.0
This user guide addresses the features, setup and operation of the VersaKit development
system for the evaluation and programming of Ramtron’s high performance, fully-
integrated, FRAM-Enhanced™, 8051-based VRS51L3xxx microcontrollers.
Table of Contents
1VERSAKIT-30XX DEVELOPMENT SYSTEM OVERVIEW ..........................................................................................2
2OVERVIEW OF THE VERSAKIT-30XX DEVELOPMENT BOARD..............................................................................3
3OVERVIEW OF THE VJTAG-USB INTERFACE........................................................................................................10
4MINIMAL CONFIGURATION OF THE TARGET BOARD ..........................................................................................13
5DEVELOPMENT KIT SETUP FOR VRS51L3074 EVALUATION ..............................................................................14
6VERSAKIT-30XX DEVELOPMENT BOARD SCHEMATICS .....................................................................................24
Ramtron International Corporation ♦http://www.ramtron.com
1850 Ramtron Drive Colorado Springs ♦MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208
♦
Colorado, USA, 80921 1-800-545-FRAM, 1-719-481-7000
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VersaKit-30xx
1 VersaKit-30xx Development System Overview
The VersaKit-30xx development kit is a plug-and-play evaluation system for the VRS51L3xxx series of high performance,
fully-integrated, FRAM-Enhanced™ 8051 microcontrollers. The VersaKit-30xx provides a complete and comprehensive
programming and development platform, with ample prototyping space and easy access to chip peripherals and I/Os.
The VersaKit-30xx development system features:
•VRS51L3074 in QFP-64 package soldered onboard (contact Ramtron for details on the
VRS51L3174 in QFP-44 package and the VRS51L2070)
•FM31xx MCU companion, FM25xx SPI FRAM and FM24xx I²C FRAM devices installed
•5x2 header to connect VJTAG-USB programming/debugging interface
•2 DB9 serial port female connectors and 1 onboard RS-232 transceiver with configuration jumper
•Tact switches for manual reset and external interrupt of the processor
•Four sets of 16 probing points around VRS51L3074 device
•22x2 header alongside prototyping area to access QFP-44 device pins (header pin number corresponds to device
pin number)
•32x2 header alongside prototyping area to access QFP-64 device pins (header pin number corresponds to the
device pin number)
•Prototyping space
•Character LCD interface header footprint
•External crystal footprint
•8 uncommitted user LEDs
•Onboard 3.3V regulator with power-on LED
•Optional regulator footprint
1.1 The VersaKit-30xx content:
oDevelopment board that supports the VRS51L3074 (or the VRS51L2070)
oVJTAG-USB programming/debugging interface
oUSB Cable
o6V Power supply
Figure 1: VersaKit-30xx
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VersaKit-30xx
1.2 Supported Devices
The VersaKit-30xx ships with a VRS51L3074-40-Q soldered onto the development board.
VRS51L3174 Evaluation
Note that the VersaKit-30xx can also be used for evaluation of the VRS51L3174 (44-pin version of the VRS51L3074),
since its peripherals are a subset of the VRS51L3074. A dedicated development board will be available for the 44-pin
VRS51L3174 (part number VersaKit-31xx) in the future that is based on the VersaKit-30xx (there is a 44-pin QFP footprint
under the installed VRS51L3074 on the VersaKit-30xx devboard for this purpose). Users should contact Ramtron for
VersaKit-31xx availability. In the short term, code can be developed on the VRS51L3074 and easily ported to the
VRS51L3174.
This user guide will address features associated with the VersaKit-31xx development board.
2 Overview of the VersaKit-30xx Development Board
The figure below offers a detailed look at the VersaKit-30xx development board and its principal features, which will be
addressed in this document.
Figure 2: VersaKit-30xx development board
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VersaKit-30xx
2.1 Power Supply Requirements
The VersaKit-30xx development board is powered via either the Versa JTAG USB (VJTAG-USB) board or an external
power supply connected to PJ1. The VJTAG-USB provides up to about 110mA of power to the devboard or target board.
The development board consumes from 30 to 40mA, leaving approximately 70mA for prototype development
If your prototype’s total power consumption is more than 70mA, we recommend using the external power supply shipped
with the VersaKit-30xx. This should be connected to PJ1 on the devboard and can supply up to 300mA.
Note: If the external power supply is connected to PJ1, remove the JP1 jumper on the VJTAG-USB board.
Figure 3: JP1 jumper of the VJTAG-USB board
If you need to use another power source, ensure that it respects the following parameters:
Table 1. Development board power supply specifications
Nominal input Voltage 6VDC
Maximum input voltage 11V DC
Current 200mA+
Plug Type 2.1mm Female Plug (Center
positive)
Warning: Many commercially-available wall-mount DC power adapters exceed their output voltage rating when in low
load condition. If you do not plan to use the power supply provided with the kit, verify that the specifications on the one
you choose meets the requirements above before using it with the development board.
Ensure that the input voltage supplied to the devboard PWR-IN input is always below 11 volts.
2.2 VersaKit-30xx Devboard: Onboard Power Supply Configuration Regulators & JP1 Jumper
The VersaKit-30xx devboard includes a 3.3V low drop-out linear regulator to power the VRS51L3074 (through the JP1
jumper) and the RS-232 transceiver. This regulator provides up to 250mA of power and includes a thermal shutdown
feature.
To facilitate use of the devboard as a prototyping platform, access to the 3.3V regulator output and ground access are
available via two 4x2 header footprints located on each side of the prototyping area.
The development board also features an auxiliary LM2937 regulator footprint, which is powered by a DC power input and
whose output is accessible on the H6 4x2 header footprint. The R9 resistor provides a path from the U4 output and H6
VDD to the Reg102-3.3 regulator output.
Heat from the regulators is dissipated through the devboard PCB. As such, the area on the PCB around the regulators
may become hot when the regulators are operating.
Warning: It is mandatory to remove resistor R9 when installing a regulator in position U4.
Please refer to the development board schematics at the end of this document for more details about regulator
configuration.
2.3
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VersaKit-30xx
P1, P2 - RS-232 DB9 Connectors for Serial Ports
The development board includes a 2-channel RS-232 transceiver and two DB9 connectors to access the VRS51L3074’s
UARTs.
P1 – Provides access to VRS51L3074 UART 0
P2 – Provides access to VRS51L3074 UART 1
A set of four jumpers enables the P1 and P2 connectors to be assigned to the UARTs. A set of four headers (JP2, JP3,
JP4, JP5) located directly below the P1 DB9 Connector configures the connection between the VRS51L3074, the RS-232
transceiver and DB9 connectors P1 and P2. Several configurations are possible with different header settings, but the two
configurations below are the most typical:
Typical Configuration 1
JP2 1-2 VRS51L3074 UART1 P1.2-RXD1 routed on P1
JP3 1-2 VRS51L3074 UART1 P1.3-TXD1 routed on P1
JP4 1-2 VRS51L3074 UART0 P3.0-RXD0 routed on P2
JP5 1-2 VRS51L3074 UART0 P3.1-TXD0 routed on P2
JP2
JP3
11
JP4
JP5
11
Typical Configuration 2
JP2 2-3 VRS51L3074 UART1 RXD1a routed on P1 (alternate UART1 pins)
JP3 2-3 VRS51L3074 UART1 TXD1a routed on P1 (alternate UART1 pins)
JP4 2-3 VRS51L3074 UART0 P2.4-RXD0a routed on P2 (alternate UART1 pins)
JP5 2-3 VRS51L3074 UART0 P2.3-TXD0a routed on P2 (alternate UART1 pins)
JP2
JP3
11
JP4
JP5
11
Figure 4: Typical configurations for headers and serial ports
2.4
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VersaKit-30xx
VRS51L3074 Peripheral and I/O Access and Development Board Prototyping Area
The development board includes a set of probe points that surround the VRS51L3074. These probe points provide a
direct connection to the device pins for signal probing.
Figure 5: Probing points around the VRS51L3074-40-Q
Access to the device I/Os is also possible through two header footprints organized as follows:
The H17 header footprint provides access to the VRS51L3074 pins. Pin assignment on Header H17 directly corresponds
to the VRS51L3074 pin-out.
If the VRS51L3174 is installed on the PCB, Header H16 provides a direct connection to the 44-pin device and the H16
Header pin assignment directly corresponds to the device pin-out.
Uncommited
User LEDs
3.3V and
Ground
access
VRS51L3074 64/44-Pin
Peripherals and I/Os Access
for 64/44-Pin Packages
User Prototyping
Area
Ground point
access
Char. LCD
footprint
Figure 6: Prototyping area and access to VRS51L3074 I/O and peripherals pins
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2.4.1 Probe headers for peripheral and I/O access around the VRS51L3074 QFP-64
The following figure shows the pin connections of the header footprints located around VRS51L3074-40-Q on the
development board:
Figure 7: Probing vias around the VRS51L3074
2.4.2 Header footprints for VRS51L3074 QFP-64 peripherals and I/O access
To access the VRS51L3074 I/Os and peripherals, the devboard provides a 64-pin header footprint near the prototyping
area. This header footprint provides access to all pins on the chip. The diagram below shows the header footprint pin-out.
P1.5 - SDO
P3.0 - RXD0 - PC0.1
P1.7 - SDI – SDA* RESET
P4.4
P1.1-CS1-T2EX
P1.3 - CS3 - TXD1
P1.0 - CS0-T2IN
P4.0-T1OUT
P2.1-PWM1-AD9
P2.3-PWM3-TXD0*-AD11
P2.5-PWM5-AD13
P3.1 - TXD0
P0.2-AD2
P4.3-TDI
P0.6-AD6
P0.4-AD4
CM0-ALE
P0.0-AD0
P2.7-PWM7-AD15
VDD
P1.6 - SCK-SCL*-PC1.3
P1.2-CS2-RXD1-PC1.1-T2OUT*
P1.4 – SS-T1OUT*
P4.5 - T0OUT
P3.6-WR
XTAL1-P4.6
GND
P2.0-PWM0-AD8
P2.2-PWM2-AD10
P0.5 - AD5
P4.2-TDO
P0.7 - AD7
P0.3 - AD3
P0.1 - AD1
P4.1-TME
P2.4-PWM4-RXD0*-AD12
P2.6-PWM6-AD14
P3.3-INT1-PC1.0
P3.7-RD
XTAL2-P4.7
P3.5-T1-SDA-T1IN
P3.2 - INT0 - PC0.0
P3.4-SCL-T0IN -PC0.3
34
35
36
37 39 41 43
246810
12 14 16 18 20 22 24 26 28 30 32 38 40 42 44
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 331
54
55
56
57 59 61 63
46 48 50 52 58 60 62 64
45 47 49 51 53
P5.1 - PWM1*
P5.3 - PWM3*
P5.0 – PWM0*
P5.2 – PWM2*
GND
P5.4 – PWM4*
P5.6 – PWM6*P5.5 – PWM5*
P5.7 – PWM7*
VDD
T1EX-TXD1*
RXD1-T0EX-PC1.2 P6.7-A7
P6.5-A5P6.6-A6
P6.4-A4
P6.2-A2
P6.3-A3
P6.1-A1
P6.0-A0
H17 – VRS51L3074 QFP-64 Peripheral and I/O Access
Figure 8: Pin description of H17 I/O and peripheral access
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2.4.3 Probe headers for peripherals and I/O access around the VRS51L3174 QFP-44
The following figure shows the pin connections of the header footprints located around VRS51L3174 QFP-44 on the
development board:
Figure 9: Probing vias around the VRS51L3174
2.4.4 Header footprints for VRS51L3174 QFP-44 peripheral and I/O access
To access the VRS51L3174 QFP-44 I/Os and peripherals, the development board provides a 44-pin header footprint near
the prototyping area. This header footprint provides access to all the pins on the chip. The diagram below describes the
header footprint pin-outs.
P1.5 - SDO
P3.0 - RXD0 - PC0.1
P1.7 - SDI – SDA* RESET
P4.4
P1.1-CS1-T2EX
P1.3 - CS3 - TXD1
P1.0 - CS0-T2IN
P4.0-T1OUT
P2.1-PWM1-AD9
P2.3-PWM3-TXD0*-AD11
P2.5-PWM5-AD13
P3.1 - TXD0
P0.2-AD2
P4.3-TDI
P0.6-AD6
P0.4-AD4
CM0-ALE
P0.0-AD0
P2.7-PWM7-AD15
VDD
P1.6 - SCK-SCL*-PC1.3
P1.2-CS2-RXD1-PC1.1-T2OUT*
P1.4 – SS-T1OUT*
P4.3 - T0OUT
P3.6-WR
XTAL1-P4.6
GND
P2.0-PWM0-AD8
P2.2-PWM2-AD10
P0.5 - AD5
P4.2-TDO
P0.7 - AD7
P0.3 - AD3
P0.1 - AD1
P4.1-TME
P2.4-PWM4-RXD0*-AD12
P2.6-PWM6-AD14
P3.3-INT1-PC1.0
P3.7-RD
XTAL2-P4.7
P3.5-T1-SDA-T1IN
P3.2 - INT0 - PC0.0
P3.4-SCL-T0IN -PC0.3
H16 – VRS51L3174 QFP-44 Peripherals and I/Os access
34
35
36
37 39 41 43
246810
12 14 16 18 20 22 24 26 28 30 32 38 40 42 44
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 331
Figure 10; Pin description of H21 access to VRS51L3174 QFP-44 peripherals
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VersaKit-30xx
Ground Points on the Development Board
The VersaKit-30xx development board provides a ground access point (S1) located above the H18 Header on the right
side of the PCB. This point can be used to connect measurement instruments to ground.
2.5 Tact Switches
The development board includes two tact switches:
oSW1 – VRS51L3074 Reset Switch. This switch allows a manual reset of the VRS51L3074 device. The
VRS51L3074 reset is active low.
Note: During programming or in-circuit debugging of the VRS51L3074, do not press SW1. Doing so could
result in loss of synchronization between the Versa Ware JTAG software and VRS51L3074 debugger.
oSW2 – VRS51L3074 Interrupt Switch. This switch allows users to manually send a low pulse to the device’s
INT0 pin. A connection can be established from the SW2 to the VRS51L3074 INT1 pin by installing a 0Ω
resistor at position R28 and removing the 0Ωresistor from R27.
2.6 User LEDs
The development board includes a set of eight uncommitted, 3mm, green user LEDs. The anode of each LED is
connected to the board’s VCCMCU supply line through a 680R current limiting resistor, while the cathode of each LED is
connected to the user LED’s H13 header footprint.
2.7 Character LCD Module Header Footprint
The development board features a header footprint (LCD1) for easy installation of a character LCD module. When
installed, the character LCD module header footprint and the VRS51L3074 are configured as follows:
Table 2: Character LCD header footprint pin-out
LCD Connected to
LCD Data [7:4] P0 [7:4]
LCD Data [3:0] Not connected
LCD E P0.2
LCD RW P0.1
LCD RS P0.0
LCD VEE Accessible through H9
Most character LCD modules require a 5V supply. The LCD supply is accessed through H14. If the LCD module operates
from 3.3V, a 0Ωresistor can be installed at position R31 to connect the LCD module supply and the devboard supply.
The LCD drive pin (VEE) is accessible through H9. The LCD driving voltage that must be applied on the VEE pin of the
LCD module depends on the LCD type and varies among different manufacturers. Please consult the datasheet of your
specific LCD module to establish the proper voltage. For your convenience, we have included an unpopulated 0805
resistor footprint between the H9 and the LCD VEE pin, as well as a 0805 capacitor footprint between the LCD VEE pin
and the development board ground.
The LCD module backlight pins are accessible via the H15 2x1 header footprint
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VersaKit-30xx
2.8 Onboard FM24C64 I2C FRAM, FM25CL64 SPI FRAM and FM31256 MCU Companion
A 5V, 64Kb I²C FRAM device (FM24CL64) is included with the development board at position U8. The SCL and SDA
lines of FM24C64 are connected to the H12 2x1 header footprint.
The development board also features a FM31256 Processor Companion including FRAM at position U8, featuring 256Kb
of FRAM memory, a real-time clock (RTC), a watchdog timer, an event counter and power fail monitoring circuitry. A 32
kHz crystal required for driving the FM31256’s RTC is also included on the PCB.
Two 2KΩpull-up resistors (R15 and R16) are connected between the 3.3V supply and the SDA and SCL lines,
respectively. Two header footprints are provided for accessing the FM3164 I/Os. The FM3164’s I²C communications
interface is connected to H12.
Finally, an FM25CL64, a 3V 64Kb SPI FRAM, is also installed on the development board at position U5. The device
communication interface I/Os are accessible through the H7 header footprint.
3 Overview of the VJTAG-USB interface
The VJTAG-USB board is a USB-based JTAG interface for in-circuit programming and debugging of Ramtron’s
VRS51L3074 and other JTAG-based microcontrollers. The VJTAG-USB connects directly to the VersaKit-30xx devboard
and can be used on any prototype/production board featuring a Ramtron JTAG based MCU. The following figure depicts
the VJTAG-USB interface and its principal features.
Figure 11: VJTAG-USB Interface
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VersaKit-30xx
3.1 VJTAG-USB Power Supply Considerations and JP1 Header
The VJTAG-USB interface takes power via the USB serial bus; It can be used to provide a 3.3V supply to either the
devboard or the connected target board, provided that the power current consumption does not exceed `~100mA in total.
The JP1 Jumper provides a connection between the VJTAG-USB 3.3V power supply and the target board 3.3V power. If
the target board gets its power supply from an external source, such as a DC adaptor, we recommended removing the
JP1 Jumper.
3.2 Power and Status LEDs
The VJTAG-USB features two green surface mount LEDs indicating the state of the board.
The power LED is connected to the 3.3V supply of the VJTAG-USB. Depending on the state of the USB driver, when the
USB cable is connected to the VJTAG-USB, the power LED may either turn ON or stay OFF. However, when the Versa
Ware JTAG software is activated and the target device is recognized, the power LED will turn on and remain on.
If the USB cable is disconnected from the VJTAG-USB board while the Versa Ware JTAG is idling, when you reconnect
the board, the power LED will remain off until the <Synchronize> button is clicked.
The status LED reports on communication between the Versa Ware JTAG software and the VJTAG-USB board.
Table 3: VJTAB-USB LED Functions
Status LED Programmer Mode Debug Mode
Off Versa Ware JTAG Software is
idling: The program in the target
may or may not run.
Status LED should be ON or blinking
Sporadic
blinking
Indicates that the Versa Ware
JTAG Software and the VJTAG-
USB board are communicating
Some operations such as <Restart>, will make both
power and status LEDs ,blink
Blink X The target processor device is executing code
On X The target processor has halted
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VersaKit-30xx
3.3 H2 JTAG Interface Connector
The VJTAG-USB features a 5x2 female socket (H2), located on the bottom side of the PCB. H2 is used to access the
JTAG interface port of the VRS51L3074, which is installed on the devboard or target board.
On the devboard, the JTAG interface is accessed using a 5x2 male header. The header pin-out is shown below:
Figure 12: VJTAG-USB interface connector pin-out
The PWRCTRL line on the target board’s JTAG header is optional. However, if the target board supply is from an
external source and the onboard regulator does not have a power control feature, uncheck “Automatic power control” in
the Versa Ware JTAG Software Device Options window.
Figure 13: Versa Ware Automatic power control setting
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VersaKit-30xx
4 Minimal Configuration of the Target Board
The following diagram demonstrates the target board configuration required for in-circuit programming and in-circuit
debugging of the VRS51L2070/3074 using the VJTAG-USB interface.
Figure 14: JTAG interface access on target board
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VersaKit-30xx
5 Development Kit Setup for VRS51L3074 Evaluation
5.1 VersaKit-30xx Hardware Setup
The VRS51L3074 includes a Versa-JTAG programming/debugging interface port, accessed via the 5x2 header at position
H2 (JTAG) on the development board. To evaluate the VRS51L3074, use the VersaKit-30xx VJTAG-USB to interface with
Ramtron’s Windows®-based Versa Ware JTAG programming/debugging software.
Figure 15: VJTAG-USB interface for programming and debugging the VRS51L3074
5.1.1 Basic VersaKit-30xx setup for VRS51L3074 evaluation
Setup of the VersaKit-30xx is quick and easy. Failure to perform the setup operations in the recommended order may
result in software/OS instability.
First, insert the VJTAG-USB into the VersaKit-30xx devboard’s Header H2 so that the CN1, USB connector sits directly
above the rightmost DB9 connector. If the VJTAG-USB is going to provide the power supply for the devboard, then a
jumper should be inserted at position JP1. If the board is going to receive power from an external source, remove the
jumper from JP1.
Figure 16: Step 1: Install the VJTAG-USB on the development board
Next, connect the external power supply to the devboard (if required) and then connect the USB cable to the VJTAG-USB
cboard.
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VersaKit-30xx
Figure 17: Connecting the USB Cable into the VJTAG-USB (no external power supply)
Figure 18: Connecting the power supply to the development board then the USB Cable to the VJTAG-USB
Warning: Do not remove the VJTAG-USB board from the development board without first disconnecting the USB cable.
This may cause the Windows® OS to become unstable, requiring a computer reboot.
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VersaKit-30xx
5.2 Overview of the Versa Ware JTAG Software
Versa Ware JTAG is a Windows®-based software tool that provides a user-friendly development platform for all Ramtron
microcontrollers featuring a JTAG interface (the VRS51L2xxx, VRS51L3xxx and future derivatives).
The Versa Ware JTAG Software is composed of two parts:
oVersa Ware JTAG Programmer
The Versa Ware JTAG Programmer is used to perform operations such as erase, program, read, etc., on the target
device’s Flash memory.
oVersa Ware JTAG Debugger
The Versa Ware JTAG Debugger is a user interface that links the in-circuit debugger and the source code. All Ramtron
MCUs with a JTAG interface include an integrated debugger that enables in-application debugging of the device via its
JTAG interface.
The Versa Ware JTAG Debugger is compatible with the SDCC, Keil and Ride compilers.
The Versa Ware JTAG software was developed on Windows XP, but should operate properly on Windows Vista and
Windows 2000 operating systems. It should also work on a Window 98 SE operating system on a computer with a UBS
interface. Users without a USB interface, can use Ramtron’s parallel port version of the JTAG interface. Please contact
Ramtron to order one.
The following window shows the in-circuit debugger in action when the source code XRAM, SFR page 0, and watch list
windows are open and the program is halted at a breakpoint.
Figure 19: Versa Ware JTAG debugger window
The Versa Ware JTAG Debugger provides a comprehensive set of configuration options allowing users to tailor the
user interface, watch variables and breakpoints settings.
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VersaKit-30xx
5.3 Installing the Versa Ware JTAG Software
Installing the Versa Ware JTAG software is a two-step process that is handled automatically by the installation program.
•Versa Ware JTAG software installation
•Prolific PL2303X USB driver installation
As with most software/driver installations, we suggest creating a System Restore point before running the setup. To
install Versa Ware JTAG, run the Versa_Ware_JTAG_3x_SETUP.exe file available for download on the Ramtron Web
site and follow the instructions provided by the installation wizard.
Figure 20: Versa Ware JTAG Setup
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VersaKit-30xx
5.4 Getting Started Using the Versa Ware JTAG Software
Once the software is installed, it can be run directly from the setup program, or by clicking on the Versa Ware JTAG
shortcut created during the installation process.
5.4.1 Versa Ware JTAG programming interface
Upon startup, the software will attempt to connect to the VJTAG-USB interface.
Action Toolbar
File Information Window
Status Bar
Figure 21: Versa Ware JTAG programming interface
Most of the functions provided by the Versa Ware JTAG software are executable via the action toolbar.
To download a HEX file into the VRS51L3074:
1. Ensure that the Versa-JTAG interface is properly connected to the H2 header of the development board.
2. Click on the synchronize button. The status bar should show: “VRS51L3074-40-Q waiting for instruction”.
3. Click open to select the HEX file to be programmed into the VRS51L3074.
4. Click erase then program to erase and program the Flash. By default, after this process is complete, the
program will start.
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VersaKit-30xx
The synchronize button can be used to halt execution of the VRS51L3074 program and put the device into program
mode. The run button restarts program execution.
The options button allows configuring the programming options, set the Flash security options, and activates the in-
circuit debugger.
Figure 22: Versa Ware JTAG Device Options
Changes to any of the device options will become effective the next time an erase then program operation is initiated.
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VersaKit-30xx
5.4.2 Using the Versa Ware JTAG Debugger
Once the program is loaded into the VRS51L3074 Flash memory and the debugger is enabled, activate the debugger by
clicking on the debugger button. Upon startup, the debugger will halt the processor at address 0x0000 and wait.
Figure 23: Versa Ware Debugger upon startup
Once the debugger starts, you can either run the program at full speed by clicking on run or set a breakpoint anywhere
in the code by either double clicking on a specific code line and then pressing run or by setting the breakpoint
manually. Alternatively, you can manually set breakpoints anywhere in the code by clicking the breakpoint setting
button .
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Table of contents
