Texas Instruments ADS58H40 User manual

User's Guide
SLAU455–August 2012
ADS58H40 EVM
This document serves as a user’s guide for the ADS58H40 Evaluation Module (EVM). The EVM provides
a platform for evaluating the ADS58H40, a quad-channel, 14-bit telecommunications analog-to-digital
converter (ADC) operating at sampling rates of up to 250 MSPS. Designed for low-power consumption
and high spurious free dynamic range (SFDR), the ADC has low-noise performance and outstanding
SFDR over a large input-frequency range.
The four ADC channels are separated into two blocks with two ADCs each. Each block can individually be
configured into three different operating modes: 11-bit Operating mode, 11-bit SNRBoost mode, 14-bit
High Resolution Burst mode.
This EVM is ideally suited for mating with the TSW1400 Capture Card for performing a data capture into a
capture buffer, uploading the sample data to a PC, performing an FFT, and reporting on SNR, SFDR, and
other performance metrics.
For more information regarding the ADS58H40 and the related evaluation tools, please refer to the
following:
• ADS58H40 – Quad 14-bit 250-MSPS ADC with SNRBoost and Burst Mode (SBAS589)
• TSW1400 – High-Speed Data Capture and Pattern Generation Platform (SLWU079)
• ADS58H40 EVM Configuration Software (SLAC533)
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Block Diagram ............................................................................................... 2
1.2 EVM Power Supply ................................................................................................ 3
1.3 EVM Connectors and Jumpers ................................................................................... 4
1.4 EVM ADC Input Circuit Configurations .......................................................................... 6
2 Software Control ............................................................................................................ 7
2.1 Installation Instructions ............................................................................................ 7
2.2 Software Operation ................................................................................................ 7
3 Basic Test Procedure ..................................................................................................... 10
3.1 Test Block Diagram .............................................................................................. 10
3.2 Test Set-up Connection .......................................................................................... 11
3.3 ADS58H40 Software Quick Start Guide ....................................................................... 11
3.4 ADS58H40 and TSW1400 Setup Guide ...................................................................... 11
List of Figures
1 Simplified ADS58H40 EVM Block Diagram ............................................................................. 2
2 Simplified ADS58H40 EVM Power Supply .............................................................................. 3
3 ADS58H40 EVM Connector and Jumper Locations.................................................................... 4
4 ADS58H40 ADC Input Circuit ............................................................................................. 6
5 ADS58H40 Clock Input Circuit ............................................................................................ 6
6 ADS58H40 Main Panel..................................................................................................... 8
7 ADS58H40 SNRBoost/Burst Mode Panel ............................................................................... 9
8 ADS58H40 and TSW1400 Test Setup Block Diagram............................................................... 10
9 Select ADS58H40 in the High Speed Converter Pro GUI Program ................................................ 12
10 Load ADC Firmware Prompt............................................................................................. 12
1
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14-bit
ADC
J6
J7
14-bit
ADC
J8
J9
J10
14-bit
ADC
J11
J12
14-bit
ADC
J13
J14
Digital
Block
+
Output
Formatter
CLKOUTABP/M
DAB[1:13]P/M
13
DAB[0]/OVRAB
CLKOUTCDP/M
DCD[1:13]P/M
13
DCD[0]/OVRCD
J5
Power
Supply
Circuits
USB
to
SPI
6 V only
J1
USB J4
ADS58H40
CLK IN
CH B
CH C
CH D
CH A
Introduction www.ti.com
11 ADS58H40 11-bit Operating Mode, Single Tone Test Result: Fs = 245.76 MSPS, Fin = 170 MHz ........... 13
12 ADS58H40 11-bit SNRBoost Mode, Single Tone Test Result: Fs = 245.76 MSPS, Fin = 170 MHz........... 14
13 TSW1400 Trigger Option................................................................................................. 15
14 ADS58H40 14-bit High-Resolution Mode, Single Tone Test Result: Fs = 245.76 MSPS, Fin = 170 MHz.... 16
List of Tables
1 Power Supply Options...................................................................................................... 3
2 ADS58H40 EVM Connectors.............................................................................................. 4
3 ADS58H40 EVM Jumper Options ........................................................................................ 5
4 ADS58H40 EVM Pushbutton Switches .................................................................................. 5
5 ADS58H40 EVM LED Indicators.......................................................................................... 6
1 Introduction
1.1 EVM Block Diagram
Figure 1 shows a simplified block diagram of the default configuration of the EVM. The four analog inputs
are supplied to the EVM through a single-ended SMA connection, then transformer coupled, turning the
single-ended signal into a balanced differential signal, and then input to the ADS58H40. A dual
transformer input circuit provides better phase and amplitude balance of the input signal when compared
to the performance delivered by a single transformer input circuit.
Figure 1. Simplified ADS58H40 EVM Block Diagram
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GND
6 V
J2
J3
TPS62420
JP2
1TPS7A8001
LDO 3.3 V To ADC
To ADC
PWR IN
J1
TPS2400
JP3
1
JP6
1TPS7A8001
LDO 1.9 V
JP5
1
Overvoltage
Protection Circuit
Dual Output
DC/DC Converter
Low Noise LDO
Low Noise LDO
www.ti.com Introduction
The clock input is supplied by way of a single-ended signal to an SMA connector and transformer coupled
producing a differential clock signal for the ADS58H40.
Power to the EVM is typically supplied by a single 6-V power brick. Banana jacks may also be used to
supply power to the EVM. All necessary voltages for the ADS58H40 are derived from the 6-V input
connection.
1.2 EVM Power Supply
Figure 2 illustrates the power supply options available on the EVM. Jumpers are used to choose the
power supply options, with the default jumper positions indicated by the darker portion of the jumper that
represents the presence of the jumper. For jumper and feedback resistor configuration, see Table 1.
Figure 2. Simplified ADS58H40 EVM Power Supply
Table 1. Power Supply Options
Power Supply JP2 JP3 JP4 JP5 R3 R7 Comment
Options
Dual outputs DC/DC converter supplies 3.85 V and 2.4 V to two
Option #1 649 536
1-2 1-2 1-2 1-2 low-noise LDOs. The low-noise LDOs output 3.3 V and 1.9 V,
(Default) kΩkΩrespectively.
536 390 Low-noise LDOs are bypassed. DC/DC converter powers the
Option #2 2-3 2-3 2-3 2-3 kΩkΩADC directly.
The default power path has an efficient dual output DC-DC switching power supply to first step down the
input supplies for the low-noise LDOs. The low-noise LDOs generate the 3.3 V and 1.9 V for the ADC
power.
The low-noise LDOs can be bypassed, allowing the DC/DC power supply to directly power the ADC. In
this implementation, adjust the feedback resistors of the DC/DC converter accordingly.
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GND PWR
IN
ADS58H40
CLKIN
CH B
J2J3
J5
J10
J9
J8
J4
USB
DNI
J1
CHA
J7
J6
DNI
JP11
1
JP2
JP3
PDN
1
CHC
J11
J12
DNI
J13
J14
1
JP9
SNRB_EN JP7
RESET
JP6
JP5
JP1JP4
1
1
1
1
1
JP12
TRIG
IN
JP8
TRIG
RDY JP10
HIRES
SW1
RESET
SW2
TRIG
EN
6VDC
D1
USB_PWR
D2 D3
TRIG
RDY
D4
HIRE
S
CHD
DNI
LVDS LVDS
Introduction www.ti.com
1.3 EVM Connectors and Jumpers
Figure 3. ADS58H40 EVM Connector and Jumper Locations
The locations of the connectors, jumpers, pushbutton switches, and LEDs are shown in Figure 3. The
EVM has power connectors or banana jacks connecting the main power for power distribution. The SMA
connectors connect the ADC input and ADC clock input to the ADC. Typically, the ADC inputs are
transformer coupled, accepting single-ended connections. The input circuit can be configured to connect
to two SMA connectors for differential signaling. Table 2 lists the connector information for the EVM.
Table 2. ADS58H40 EVM Connectors
Reference Designator Description
J1 6 V (main) power input
J2 6 V (main) power input
J3 Ground return
J4 USB Mini-B connector
J5 SAMTEC high-speed LVDS connector
J6 CH A input (positive)
J7 CH A input (negative) DNI
J8 CH B input (positive)
J9 CH B input (negative) DNI
J10 ADC clock input
J11 CH C input (positive)
J12 CH C input (negative) DNI
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Table 2. ADS58H40 EVM Connectors (continued)
Reference Designator Description
J13 CH D input (positive)
J14 CH D input (negative) DNI
The on-board jumper options allow configuration of on-board power supplies and ADC options. Many of
the jumper selections that involve DC inputs or static control signals are by way of push-on square post
jumpers. The jumper options are listed in Table 3. The table indicates the default settings of the jumpers
as the EVM is normally shipped. Some of the jumpers are open circuit by default.
Table 3. ADS58H40 EVM Jumper Options
Reference Default Optional
Function Function
Designator Setting Setting
JP1 DNI Connects low-noise LDO (U2) input to main N/A
power input
JP2 1-2 Connects DC/DC converter (U3) output to low- 2-3 Connects DC/DC converter (U3) output
noise LDO (U2) input directly to the ADC
JP3 1-2 Connects low-noise LDO (U2) output to ADC 2-3 Connects DC/DC converter (U3) output
directly to the ADC
JP4 DNI Connects low-noise LDO (U4) input to main N/A
power input
JP5 1-2 Connects DC/DC converter (U3) output to low- 2-3 Connects DC/DC converter (U3) output
noise LDO (U4) input directly to the ADC
JP6 1-2 Connects low-noise LDO (U4) output to ADC 2-3 Connects DC/DC converter (U3) output
directly to the ADC
JP7 2-3 Connects ADC RESET pin G6 to SW1 RESET 1-2 Connects ADC RESET pin G6 to DRVDD
switch
JP8 1-2 Connects ADC TRIG_RDY pin G4 to LED Open ADC TRIG_RDY pin G4 is open
circuit
JP9 2-3 Disables ADC SNRBoost 1-2 Enables ADC SNRBoost
JP10 1-2 Connects ADC HIRES pin G5 to LED circuit Open ADC HIRES pin G5 is open
JP11 2-3 Enables ADC 1-2 Power down the ADC or allows the ADC
to standby (configured by CONFIG 0x45,
bit D0)
JP12 2-3 Connects trigger signal from SW2 switch to 1-2 Connects trigger signal from TSW1400
ADC trigger input. This can be used to start the rev. E to the ADC trigger input
auto-burst process.
There are two pushbuttons on the EVM. While JP7 is set in the 2-3 position, the pushbutton switch, SW1,
provides a hardware reset to the ADS58H40. Upon powering up, the ADC can either accept a hardware
reset by pressing SW1 or by toggling the software reset switch on the EVM GUI. Table 4 lists the
descriptions of each pushbutton switch.
If the ADS58H40 is configured for high resolution burst mode, pressing SW2 while JP12 is set to the 2-3
position allows the ADC to enter burst mode. The SW2 pushbutton also provides the initial pulse needed
to start the auto-burst mode process after the ADC is configured in High Resolution Auto-Burst mode.
Table 4. ADS58H40 EVM Pushbutton Switches
Reference Purpose
Designator
SW1 While JP7 is set in the 2-3 position, pressing SW1 resets the ADC. The ADC can be reset either by pressing
SW1 or with a software reset in the GUI.
SW2 While JP12 is set in the 2-3 position, pressing SW2 allows the ADC to enter burst mode. This can also
provide the initial pulse needed start the auto-burst process.
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J10
CLK IN 1:4 0.1 PF
0.1 PF
121:
121:
0.1 PF
14-bit
ADC
Jp
Jn
0 :
0 :
0 :
0 :
0 :
0 :
0 :
0 :
DNI DNI
DNI
DNI
DNI
25:
25:
0.1 PF 0.1 PF 0.1 PF 0.1 PF
0 :
10 :
10 :
25 :
25:
82 nH
10 pF
3rd Order Bandpass Filter RLR Circuit RLCR Circuit
1:1 1:1
VCM
Introduction www.ti.com
LED D1 is lit indicating the presence of the 6-V supply voltage to the EVM, while LED D2 is lit indicating
the presence of the USB to serial converter power. LEDs D3 and D4 indicate the status of the ADS58H40
High Resolution Burst Mode. Table 5 lists the description of each LED indicator.
Table 5. ADS58H40 EVM LED Indicators
Reference Description
Designator
D1 When lit, D1 shows the presence of the 6-V (main) power supply
D2 When lit, D2 shows the presence of the USB to serial converter power
D3 When lit, D3 indicates that the ADC is ready to enter trigger mode
D4 When lit, D4 indicates that the ADC is in high resolution burst mode
1.4 EVM ADC Input Circuit Configurations
Figure 4 shows the ADS58H40 ADC input circuit. The default setup has a dual 1:1 impedance ratio
transformer input circuit, which achieves better phase and amplitude balance of the input signal than is
typically produced by a single transformer input circuit. Third-order bandpass filter component pads are
available for installing bandpass filter components. The default components for the bandpass filter are
either zero Ωor open circuit.
The default input termination is 50 Ω, which is formed by two 25-Ωresistors connected to the ADC VCM
node. If the user chooses to use 100-Ωtermination with the 1:2 impedance transformer, the optional RLR
differential arm can be used to tune the in-band flatness.
The ADC analog input consists of a switched-capacitor-based, differential sample-and-hold (S/H)
architecture. Due to the opening and closing of the sampling glitches, the kick-back noise from the S/H
circuit may affect the ADC performance. Besides the on-chip R-C filter of the ADC input, the external
RLCR circuit provides additional filtering of the glitches. The default RLCR components have been
optimized for input bandwidth centered at 185 MHz. For additional RLCR components of different center
frequencies, refer to the ADS58H40 datasheet (SBAS589).
Figure 4. ADS58H40 ADC Input Circuit
Figure 5 shows the ADS58H40 clock input circuit. The clock signal goes through the 1:4 impedance ratio
transformer increasing the clock amplitude by two (1:4 impedance ratio equals to 1:2 voltage ratio). The
two 121-Ωresistors will impedance transform back to the primary side as 50-Ωload impedance for the
signal source generator. For ADC evaluation, set the signal generator output to 10 dBm.
Figure 5. ADS58H40 Clock Input Circuit
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2 Software Control
2.1 Installation Instructions
• Open the ADS58H40_Installer_vxpx folder (xpx represents the latest version, which is 2.0 at the time
of this writing)
• Run Setup.exe
• Follow the on-screen instructions
• Once installed, launch by clicking on the ADS58H40_GUI_vxpx program in Start →All Programs →
Texas Instruments ADCs
• When plugging in the USB cable for the first time, the Found-New-Hardware-Wizard prompts to install
the USB drivers
– When a pop-up screen opens, select Continue Downloading
– Follow the on-screen instructions to install the USB drivers
– If needed, access the drivers directly in the install directory
2.2 Software Operation
The software allows programming control of the ADS58H40 device. The front panel provides a tab for
common control of the ADS58H40 and a SNRBoost/Burst Mode tab for control of the special data capture
modes. The GUI tabs provide a convenient and simplified interface to the most-used registers of each
device.
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2.2.1 Control Options
Figure 6. ADS58H40 Main Panel
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Figure 7. ADS58H40 SNRBoost/Burst Mode Panel
2.2.2 Register Control
•Send All: Sends the register configuration to all devices
•Save Regs: Saves the register configuration for all devices
•Load Regs: Load a register file for all devices.
– Select Load Regs button
– Double click on the data folder
– Double click on the desired register file
– Click Send All, ensuring all of the values are loaded properly
2.2.3 Miscellaneous Settings
•Reset USB: Toggle this button if the USB port is not responding. This generates a new USB handle
address
Note: Reset the board after every power cycle and click the Reset USB button on the GUI
•Exit: Stops the program
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PC
USB
USB J1
J4
J5
USB Mini-B
Signal Generator
(Input Source)
Signal
Generator
(CLK Source)
CLK
J10
CHB
J8
CHA
J6
+5 V
J5
J12
TSW1400
J3
USB Mini-B
CHC
J11
CHD
J13
To A, B, C, D
Channels
BPF BPF
Synchronized
Sources
+6 V
Basic Test Procedure www.ti.com
3 Basic Test Procedure
This section outlines the basic test procedure for testing the EVM.
3.1 Test Block Diagram
The test set-up for evaluation of the EVM with the TSW1400 Capture Card is shown in Figure 8. As seen
in this figure, the evaluation setup involves a clock from a high-quality signal generator and a sine wave
for the analog input from a high-quality signal generator. High-order, narrow-bandpass filters are usually
required on clock and input frequency to remove phase noise and harmonic content from the input sine
waves. If the two signal generators are not synchronized by an external reference signal to make the clock
and input frequency coherent, then the resulting FFT first needs a windowing function, such as Hanning or
Blackman-Harris, applied to the data.
Figure 8. ADS58H40 and TSW1400 Test Setup Block Diagram
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