AKM AKD4127-A User manual

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
- 1 -
GENERAL DESCRIPTION
The AKD4127-A is an evaluation board for AK4127, the digital sample rate converter. The AKD4127-A
has the digital audio interface and can achieve the interface with digital audio system via opt-connector.
Ordering guide
AKD4127-A --- AK4127 Evaluation Board
FUNCTION
•DIR/DIT with optical input/output
•10pin Header for AKM AD/DA evaluation board
Opt In AK4114
10pin
Header
DSP
Data
5V GND
Opt OutAK4114
10pin
Header
DSP
Data
AK4127
COAX
Regulator
COAX
Figure 1. AKD4127-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AK4127 Evaluation Board Rev.0
AK
D4127-
A

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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Operation sequence
1) Set up the power supply lines.
[VCC] (Red) = +5V (for regulator)
[DGND] (Black) = 0V
Each supply line should be distributed from the power supply unit.
The regulator can be supplied 3.3V to all circuits.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4127 should be reset once bringing SW1 (PDN) “L” upon power-up.
Evaluation mode
(1) Setting for Input port
(1) When using DIR function of AK4114 (U3)
When using PORT1 (DIR) or J1 (COAX), nothing should be connected to PORT2 (INPUT).
JP2
IBICK JP3 SDTI JP4 ILRCK
•SW3 setting (See Table 1)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. IDIF2-0 and PLL2-0 of SW3
should be used by default setting.
SW3 No. Name ON (“H”) OFF (“L”) Default
1 DITH Dither ON Dither OFF L
2 PLL2 H
3 PLL1 L
4 PLL0
PLL Mode Setting
Fixed to default H
5 IDIF0 L
6 IDIF1 H
7 IDIF2
AK4127 Audio I/F Format Setting
Fixed to default L
Table 1. SW3 Setting

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2
IBICK JP3 SDTI JP4 ILRCK
•SW3 setting (See Table 2)
Upper-side is “H” and lower-side is “L”.
SW3 No. Name ON (“H”) OFF (“L”) Default
1 DITH Dither ON Dither OFF L
2 PLL2 H
3 PLL1 L
4 PLL0
PLL Mode Setting
Refer to Table 3 H
5 IDIF0 L
6 IDIF1 H
7 IDIF2
AK4127 Audio I/F Format Setting
Refer to Table 4 L
Table 2. SW3 Setting
Mode Master / Slave PLL2 PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK SMUTE
(Note 4)
0 L L L
8k ∼96kHz
1 L L H Manual
2 L H L
8k ∼216kHz
16k ∼216kHz
(Note 1)
Depending on
IDIF2-0 Not needed. Semi-Auto
3 L H H Reserved
4 H L L 32fsi (Note 3)
5 H L H 64fsi
6 H H L 128fsi
Manual
7
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
H H H
8k ∼216kHz
(Note 2) 64fsi
Not
needed. Semi-Auto
8 L L L
8k ∼216kHz 128fs
9 L L H
8k ∼108kHz 256fs
10 L H L
8k ∼54kHz 512fs Manual
11 L H H
8k ∼216kHz 128fs Semi-Auto
12 H L L
8k ∼216kHz 192fs
13 H L H
8k ∼108kHz 384fs
14 H H L
8k ∼54kHz 768fs Manual
15
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
H H H
8k ∼216kHz
64fs
192fs Semi-Auto
Table 3. PLL Setting (Input PORT)
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the
datasheet. 470Ω, 0.22µF and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet.

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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Mode IDIF2 IDIF1 IDIF0 SDTI Format ILRCK IBICK IBICK Freq Master / Slave
0 L L L 16bit, LSB justified ≥32fsi
1 L L H 20bit, LSB justified ≥40fsi
2 L H L 24/20bit, MSB justified ≥48fsi
3 L H H 24/16bit, I2S Compatible ≥48fsi or
32fsi
4 H L L 24bit, LSB justified
Input Input
≥48fsi
Slave
5 H L H 24bit, MSB justified 64fs
6 H H L 24bit, I2S Compatible Output Output 64fs Master
7 H H H Reserved
Table 4. Input Audio Interface Format (Input PORT)
(2) Setting for Output port
(1) When using DIT function of AK4114 (U4)
When using PORT4 (DIT) or J2 (TX), nothing should be connected to PORT3 (OUTPUT). When BICK and
LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed.
JP6
OBICK JP7 OLRCK
•SW4 setting (See Table 5)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. ODIF2-0, CMODE2-0 and
OBIT1-0 of SW3 should be used by default setting.
SW4 No. Name ON (“H”) OFF (“L”) Default
1 ODIF1 H
2 ODIF0
AK4127 Output Audio I/F Format Setting
Fixed to default L
3 CMODE2 H
4 CMODE1 L
5 CMODE0
AK4127 Mode Setting
Fixed to default L
6 OBIT1 H
7 OBIT0 AK4127 Output bit Length Setting
Fixed to default H
Table 5. SW4 Setting

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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(2) All clocks are fed through the 10pin port
When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT).
JP6
OBICK JP7 OLRCK
•SW4 setting (See Table 6)
Upper-side is “H” and lower-side is “L”.
SW4 No. Name ON (“H”) OFF (“L”) Default
1 ODIF1 H
2 ODIF0
AK4127 Output Audio I/F Format Setting
Refer to Table 7 L
3 CMODE2 H
4 CMODE1 L
5 CMODE0
AK4127 Mode Setting
Refer to Table 8 L
6 OBIT1 H
7 OBIT0 AK4127 Output bit Length Setting
Refer to Table 9 H
Table 6. SW4 Setting
Mode ODIF1 ODIF0 SDTO Format
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified
3 H H I2S Compatible
Table 7. Output Audio Interface Format 1 (Output PORT)
Mode CMODE2 CMODE1 CMODE0 Master / Slave OMCLK fso
0 L L L Master 256fso 8k ∼108kHz
1 L L H Master 384fso 8k ∼108kHz
2 L H L Master 512fso 8k ∼54kHz
3 L H H Master 768fso 8k ∼54kHz
4 H L L Slave Not used. Set to DVSS. 8k ∼216kHz
5 H L H Master 128fso 8k ∼216kHz
6 H H L Master 192fso 8k ∼216kHz
7 H H H Master (Bypass) Not used. Set to DVSS. 8k ∼216kHz
Table 8. Master/Slave Control (Output PORT)
Mode OBIT1 OBIT0 SDTO Output
0 L L 16bit
1 L H 18bit
2 H L 20bit
3 H H 24bit
Table 9. Output Audio Interface Format 2 (Output PORT)

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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Other jumper pins set up
1. JP1 (RX) : Select of RX input
COAX: COAX input.
RX: Optical input. <Default>
2. JP5 (CKSO) : AK4114 BICK and LRCK setting
H: BICK: 2.048MHz ∼12.288MHz, LRCK: 32kHz ∼192kHz
L: BICK: 2.048MHz ∼6.144MHz, LRCK: 32kHz ∼96kHz <Default>
When BICK and LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed.
3. JP8 (TX) : Select of TX output
BNC: BNC connector (J2) output.
OPT: Optical (PORT4) output. <Default>
The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK4127 and the AK4114. Keep “H” during normal operation.
The AK4127 and the AK4114 should be resets once bringing “L” upon power-up.
[SW2] (SMUTE): Soft mute of AK4127
Indication for LED
[LED1] (UNLOCK): Monitor UNLOCK pin of the AK4127. LED turns on when unlock occurs.
[LED2] (ERF): Monitor INT0 pin of the AK4114 (U3). LED turns on when unlock or parity error occurs.

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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MEASUREMENT RESULTS
[Measurement condition]
•Measurement unit : Audio Precision, System Two Cascade
•Power Supply : AVDD = DVDD = 3.3V
•Band width : 20Hz ∼FSO/2
•Temperature : Room
[Measurement Result]
SRC Characteristics SDTO Lcht SDTO Rch Unit
THD+N (Input = 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI=192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
130.4
125.0
136.9
124.7
96.1
130.4
125.0
136.9
124.7
96.1
dB
dB
dB
dB
dB
Dynamic Range (Input = 1kHz, −60dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI=192kHz/48kHz
WorstCase(FSO/FSI=48kHz/32kHz)
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz
137.3
137.3
137.3
135.6
135.7
139.7
137.3
137.3
137.3
135.6
135.7
139.7
dB
dB
dB
dB
dB
dB

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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[Plot] AK4127 FFT Plot (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS], fin=1[KHz]
-200
+0
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Fig 6. FFT Plot (Input Level= 0[dBFS])
AK4127 FFT Plot (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=-60[dBFS], fin=1[KHz]
-200
+0
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Fig 7. FFT Plot (Input Level= −60[dBFS])

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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AK4127 THD+N vs Input Level (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V],fin=1[KHz]
-140 +0-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
-180
-100
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
d
B
F
S
Fig 1. THD+N vs. Input Level
AK4127 THD+N vs Input Frequency (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS]
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-160
-80
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
d
B
F
S
Fig 2. THD+N vs. Input Frequency (Input Level= 0[dBFS])

ASAHI KASEI [AKD4127-A]
<KM085601> 2006/11
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AK4127 THD+N vs Input Frequency(fsi=48[KHz], fso=44.1[KHz])AVDD=DVDD=3.3[V], Input Level=-60[dBFS]
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-180
-100
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
d
B
F
S
Fig 3. THD+N vs. Input Frequency (Input Level= −60[dBFS])
AK4127 Linearity(fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], fin=1[KHz]
-150 +0-140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Fig 4. Linearity