RDS PIRA32 User manual

Pira.cz PIRA32 Microcontroller
FM Broadcast Radio Data System Encoder MCU
with single communication port
DESCRIPTION
The PIRA32 Microcontroller forms a fully digital
Radio Data System encoder that has been
developed especially for FM broadcasting. It
implements physical and data-link layers and
supports extended set of RDS services.
All functions are controlled by the RS-232 interface.
The device supports optional I2C slave peripherals
such as EEPROM memory, RTC, LCD display or
digital potentiometer.
FEATURES
Single supply
Typical operating current: 9 mA @ 5 V
Minimum external parts
I2C bus for external peripherals like EEPROM,
real time clock, LCD or digital potentiometer
External TA and Program switch
Two indication LED outputs
Both stereo and mono operation possible
Built-in digital 19 kHz pilot tone PLL with
software phase shift adjustment
Parallel 8-bit D/A converter, 361 kHz sampling
rate (over-sampled)
Broadcast quality output signal
Only simple output filter required
RDS/RBDS signal:
conforms to CENELEC EN50067 / EN 62106
Continuous RDS transmission during all
operations
Firmware update capability
Communication bus:
RS-232, bidirectional
Baud rate: 1200 to 19200 Bd
Packages available: 28-Pin PDIP
28-Pin SOIC
TYPICAL APPLICATIONS
FM broadcast RDS encoders with single
communication port
RDS testing, research and development
Important Note:
This datasheet is not intended to be a complete PIRA32 system designer’s reference source.
For more information on the features, characteristics, control and use refer to these documents:
“PIRA32 RDS Encoder Technical Manual” (available online)
“PIRA32 LCD Display” (available online)
“PIRA32 Device Configuration” (optional, available on request)
“PIRA32 LCD Display Multiplexing” (optional, available on request)
The manufacturer is not liable for any damages, including but not limited to, lost profits, lost savings, or other
incidental or consequential damages arising out of the use of this product.
No part of this datasheet may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying, recording or information storage and retrieval systems, for any purpose other
than the purchaser's personal use.
Information in this document is subject to change without notice.
Revision 2017-06-09

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TABLE OF CONTENTS
1PIN DIAGRAMS AND DESCRIPTION............................................................................................................. 3
1.1 28-pin PDIP, 28-pin SOIC ......................................................................................................................... 3
1.1. Internal logical structure (simplified).......................................................................................................... 5
2ELECTRICAL CHARACTERISTICS ............................................................................................................... 6
3DESIGN NOTES .............................................................................................................................................. 7
3.1 Device reset .............................................................................................................................................. 7
3.2 Crystal oscillator........................................................................................................................................ 7
3.3 Power supply............................................................................................................................................. 7
3.4 Internal PLL............................................................................................................................................... 7
3.5 External TA switch..................................................................................................................................... 7
3.6 RS-232 interface........................................................................................................................................ 7
3.7 Digital-to-Analog converter........................................................................................................................ 8
3.8 Output low-pass filter................................................................................................................................. 9
3.9 Expansion I2C bus..................................................................................................................................... 9
3.10 Operation without EEPROM on I2C bus.................................................................................................... 9
4CONNECTION DIAGRAMS............................................................................................................................10
4.1 Basic connection diagram ....................................................................................................................... 10
4.2 Reference connection diagram................................................................................................................ 11
4.2.1 Setting up............................................................................................................................................11
4.2.2 I/O connectors and control items ........................................................................................................11
4.2.3 Schematic diagram.............................................................................................................................12
4.2.4 Part list................................................................................................................................................13
5PACKAGE DETAILS......................................................................................................................................14
5.1 28-Lead Skinny Plastic Dual In-Line –300 mil Body (PDIP) ................................................................... 14
5.2 28-Lead Plastic Small Outline –Wide, 300 mil Body (SOIC)................................................................... 15

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1 PIN DIAGRAMS AND DESCRIPTION
1.1 28-pin PDIP, 28-pin SOIC
Pin name
Description
/RESET
Device reset
Logical low on this pin holds the device in reset state.
If the reset function is not required, connect this pin to VDD through a resistor.
/SYNC
Pilot sync. switch
Drive this pin low to confirm the pilot tone validity and to enable internal pilot
PLL assuring stable phase relation between pilot tone and RDS sub-carrier.
If the pilot sync. function is not required (mono transmission), connect this pin
to VDD through a resistor so internal clock reference will be used.
PILOT
Pilot tone input
The pilot tone must comply with TTL levels. If pilot tone is not available or
does not meet the specifications required, the /SYNC pin should be driven
high.
PROGRAM
Program select
Selects between two different RDS data sets (program 1 or program 2).
If the program external switching function is not required, connect this pin to
VDD through a resistor.
TA
TA switch
RDS Traffic Announcement (TA) flag control.
If the TA external switching function is not required, connect this pin to VDD
through a resistor.

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VDD
Positive supply
Apply VDD power supply voltage to this pin.
Decoupling capacitor is required on VDD and VSS pins. A 100 nF 10-50V
ceramic capacitor is recommended. The decoupling capacitor should be
placed as close to the pins as possible.
VSS
Ground reference
All VSS pins must be connected.
OSC IN
Crystal oscillator input
Tie to 4.332 MHz crystal pin.
OSC OUT
Crystal oscillator output
Tie to 4.332 MHz crystal pin.
Can be used for clocking another device on the board.
LED1
Operation LED
Connect an indication LED (+) through a resistor or leave unconnected.
LED2
Pilot LED
Connect an indication LED (+) through a resistor or leave unconnected.
SCL
I2C serial clock output
Open-drain terminal, external 2k pull-up resistor is required.
SDA
I2C serial data input/output
Open-drain terminal, external 2k pull-up resistor is required.
TXD
Serial port transmit data
Serial RS-232 port transmit data output (software selectable 1200 to 19200
bps). Logical high = idle.
This pin is required for proper software configuration of the device.
RXD
Serial port receive data
Serial RS-232 port receive data input (software selectable 1200 to 19200
bps). Logical high = idle.
This pin is required for proper software configuration of the device.
DA0-DA7
D/A Converter bit 0 to 7
These pins together form driving signal for parallel D/A converter. A simple
low-cost R/2R resistor network can serve the D/A converter function. The R
value should be 1k.
All pins marked as “reserved” should be left unconnected or tied to VDD through a 10k resistor.

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1.1. Internal logical structure (simplified)
PLL 57 kHz
NCO DSB-SC
modulator Output
latches
Output
data
buffer
/48
RDS group
sequencer
Operational
memory
(RAM)
Internal
RTC
IIC
controller
Command
interpreter
RX buffer
48 bytes
Power
supply
Reset
OSC
Internal
reference
RDS on/off
PILOT
TA
PROGRAM
DA0-DA7
VDD VSS
SYNC
RESET OSC IN OSC OUT
LED1
SCL
SDA
RXD
TXD
LED2
Command buffer
280 bytes
P32 MCU
Scheduler

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2 ELECTRICAL CHARACTERISTICS
Maximum Ratings
Ambient temperature under bias............................................................................................-40 °C to +125 °C
Storage temperature..............................................................................................................-65 °C to +150 °C
Voltage on VDD with respect to VSS ...........................................................................................-0.3 V to +7.5 V
Voltage on any I/O pin with respect to VSS......................................................................-0.3 V to (VDD + 0.3 V)
Maximum current sourced by any output pin...........................................................................................25 mA
Maximum current sunk by any output pin ................................................................................................25 mA
Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
VDD
Supply voltage
4.2
-
5.5
V
FOSC
Oscillator Frequency
-0.01 %
4.332
+0.01 %
MHz
FS
D/A Converter sampling
rate
-
361
-
kHz
BPLL
PLL capture range
-
8
-
Hz
Stereo broadcast
TPU
Power-up delay
-
-
1100
ms
FCLK
I2C clock frequency
-
400
-
kHz

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3 DESIGN NOTES
3.1 Device reset
A reset is generated by holding the /RESET pin low.
The device has a noise filter in the reset path which
detects and ignores small pulses.
A reset pulse is generated on-chip whenever VDD
rises above a certain threshold. This allows the
device to start in the initialized state when VDD is
adequate for operation.
To take advantage of this feature, tie the /RESET
pin through a resistor (1k to 10k) to VDD. This will
eliminate external RC components usually needed
to create a reset delay.
Figure 4.1 –Device reset.
When the device starts normal operation (i.e., exits
the reset condition), device operating parameters
(voltage, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the
device must be held in reset until the operating
conditions are met.
3.2 Crystal oscillator
The oscillator circuit should be placed on the same
side of the board as the device. The load capacitors
should be placed next to the oscillator itself.
The load capacitor value depends on the crystal
characteristics. Optimal value ensures the FOSC to
lie in the tolerance range given in section Electrical
characteristics. A good starting value is 22 pF for
the load capacitors.
Figure 4.2 –Crystal oscillator.
Recommended crystal type is
Auris Q- 4,332000M-HC49US-F-30-30-D-16
or equivalent.
3.3 Power supply
The power supply must be bypassed close to the
device with a 100 nF ceramic capacitor. The output
RDS level varies proportionally to the supply
voltage.
3.4 Internal PLL
The PIRA32 Microcontroller includes an internal
phase locked loop, which synchronises the RDS
subcarrier with 19 kHz pilot tone in case of stereo
broadcast. Parameters of the PLL are controlled by
software.
Pilot tone is tied to the PILOT input pin and must
comply with TTL levels.
The PLL is active if the /SYNC pin is driven low.
This configuration makes easy to connect commonly
available clock recovery circuits (LM567) if the pilot
tone needs to be filtered from MPX signal.
The PLL should be disabled in case of mono
broadcast by driving the /SYNC pin high or by the
command EXTSYNC.
3.5 External TA switch
The external TA switch can set the Traffic
Announcement flag to 1. The TA flag is set to 1 if
the TA input is driven low. This can be done using
simple mechanical switch or any logic circuit.
Where the external TA switch feature is not
required, the TA pin must be tied to VDD through a
resistor.
3.6 RS-232 interface
The RS-232 interface is used for the device
configuration and data transfers. The RXD and TXD
pin levels are compatible with TTL. For connection
to external equipment an inverter and level
converter is required (for example MAX232).
The serial data format is given in the RDS Encoder
Technical manual (available online).

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3.7 Digital-to-Analog converter
The Microcontroller uses parallel 8-bit D/A converter with over-sampling technique. Digital data provided on DA
pins can be directly formed into final analogue RDS output signal using low-cost resistor network.
Figure 4.3 shows accurate 8-bit DAC using R/2R resistor network. It’s a binary weighted DAC that creates each
value with a repeating structure of 2 resistor values, R and R times two. This is an optimal DAC for this device.
The resistor value tolerance must not exceed 2 %.
Figure 4.3 - 8-bit D/A converter R/2R network
Figure 4.4 –Output RDS signal on oscilloscope (horizontal: 200 µs/div, vertical: 500 mV/div).
6

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3.8 Output low-pass filter
The output RDS signal modulated at 57 kHz subcarrier requires no special filtering. Spurious products are kept
below -70 dB broadcast limit and the D/A conversion residues around the sampling frequency can be cut-off using
any simple low-pass filter. This may be based either on active filter or a simple LC element. For FM broadcast
purposes the low-pass filter rejection should be at least 20 dBc on the sampling frequency. It is recommended for
high quality FM broadcasting that the output filter characteristics interpolate at least these values:
15 kHz
57 kHz
360 kHz
-20 dB
0 dB
-30 dB
3.9 Expansion I2C bus
The PIRA32 Microcontroller supports several external devices that extend its functions and features. All of these
devices are optional, i.e. the final design is highly customizable. The devices are recognized automatically on
power-up or device reset.
The I2C devices supported are listed in following table:
Device name
Manufacturer
Description
24LC256
Microchip
Serial EEPROM. Non-volatile memory for storing RDS and
configuration data. Recommended for proper function.
PCF8563
NXP
Battery powered backup real-time clock (RTC).
MCP23008
Microchip
Parallel port for 16×2 LCD display based on HD44780 driver.
MCP4551-103
Microchip
Digital potentiometer for software control of RDS output level.
3.10 Operation without EEPROM on I2C bus
Operation without EEPROM is possible. If EEPROM is not detected on the I2C bus after power-up or reset, the
RAM memory is filled with blank data. The RDS generator is turned off. The user may fill the RAM with valid
values using RS-232 ASCII commands and then turn on the RDS generator by the command RDSGEN=1.

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4 CONNECTION DIAGRAMS
4.1 Basic connection diagram
Figure 4.1.1 - Sample application circuit - schematic diagram
The figure above effectively represents minimum required connection for proper operation. It is a
default circuit for further extensions and development purposes.
Notes to the basic connection diagram:
TA
Traffic announcement switch. Driving this pin low will activate the RDS TA flag. (Optional)
PILOT
Pilot input (19 kHz TTL) from stereo encoder or pilot recovery circuit. (Optional)
RS232
RS232 interface in TTL levels for connection to a PC or any data provider through a level
converter, USB adapter or Ethernet adapter.
PLL_SYNC
Synchronization source selection:
0 –External pilot, 1 –Internal clock.
IIC
Expansion I2C bus.
RDS_OUT
Final RDS output (already modulated at 57 kHz sub-carrier, signal level 5 Vpp).
For direct FM broadcasting, additional 57 kHz bandpass filter is recommended:
-20 dB (15 kHz), 0 dB (57 kHz), -30 dB (360 kHz).

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4.2 Reference connection diagram
The reference connection diagram represents typical application for the PIRA32 Microcontroller.
The application includes:
Real time circuit with back-up battery
Pilot tone recovery circuit for enabling RDS and pilot tone synchronization using MPX input signal
RDS level set by onboard trimmer (either single- or multi-turn)
Single RS-232 interface for setup and control purposes
Mixing RDS and MPX to enable 'loopthrough' mode of operation for FM transmitters with no dedicated
RDS/SCA input
4.2.1 Setting up
After assembly, the setting up can be made in a few steps:
Without any input signal connected, adjust 19 kHz (±100 Hz) on pin 3 of the IC2
Initialize the EEPROM memory (in the Windows control software, select RDS Encoder - Special -
Initialize, or follow the Technical manual)
4.2.2 I/O connectors and control items
J5
Output
J6
Optional pilot/MPX input
JP2
Loopthrough mode enabling jumper
R27
RDS level adjust (0 to 1.4 V peak to peak)
JP4
RDS level boost enabling jumper (RDS level ×2)
POWER
DC power supply input (8 to 16 V)
JP1
Analog section power supply jumper. See the Technical manual for
details. Can be replaced by a permanent connection.
J1
Optional TA switch input (short to enable RDS TA)
J2
Optional Program switch input
LED1
Operational LED
LED2
Pilot sync. LED

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4.2.3 Schematic diagram

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4.2.4 Part list
Part
Value
IC1
24LC256-I/P
IC2
PIRA32 Microcontroller
IC3
MAX232
IC4
LM567
IC5
TLC272
IC6
7805
IC7
PCF8563
D1, D2
1N4007
D3, D4
LED 5mm
D5, D6
1N4148
Y1
4.332 MHz crystal
Y2
32.768 kHz crystal
L1
09P-331K (330 uH)
L2
09P-152J (1.5 mH)
RE1
signal relay
J4
CANON 9F connector
J5, J6
BNC connector
C1, C2, C3, C4
1u (min. 50V, electrolytic)
C5, C10
100u (min. 25V, electrolytic)
C6, C11, C12, C18, C19, C20, C24, C26, C32
100n (ceramic)
C7, C8
10u (min. 35V, electrolytic)
C9, C33
100u (min. 16V, electrolytic)
C13, C14, C30
22p (ceramic)
C15, C16, C25
4n7 (foil)
C17
22n (5%, foil)
C21
3n3 (foil)
C22
220n (foil)
C23, C29
1n (ceramic)
C27
47n (5%, foil)
C28
330p (ceramic)
C31
4u7 (foil)
BT1
CR2032 battery in vertical socket
POWER
DC power connector
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11,
R12, R13, R17, R29, R30, R36, R37
2k
R14, R19, R26, R31, R32, R33, R39
10k
R15, R18, R22
15k
R16, R20, R21, R24
33k
R23
4k7
R25
91R
R27
trimmer 1k
R28
trimmer 5k
R35
150k
RN1
3x 1k resistor network
RN2
4x 1k resistor network

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5 PACKAGE DETAILS
5.1 28-Lead Skinny Plastic Dual In-Line –300 mil Body (PDIP)
Units
INCHES
Dimension Limits
MIN
TYP
MAX
Number of Pins
n
28
Pitch
p
.100
Top to Seating Plane
A
.140
.150
.160
Molded Package Thickness
A2
.125
.130
.135
Base to Seating Plane
A1
.015
-
-
Shoulder to Shoulder Width
E
.300
.310
.325
Molded Package Width
E1
.275
.285
.295
Overall Length
D
1.345
1.365
1.385
Tip to Seating Plane
L
.125
.130
.135
Lead Thickness
c
.008
.012
.015
Upper Lead Width
B1
.040
.053
.065
Lower Lead Width
B
.016
.019
.022
Overall Row Spacing §
eB
.320
.350
.430
Mold Draft Angle Top

5°
10°
15°
Mold Draft Angle Bottom

5°
10°
15°
Notes:
§ Significant Characteristic
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010”
(0.254 mm) per side.

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5.2 28-Lead Plastic Small Outline –Wide, 300 mil Body (SOIC)
Units
MILLIMETERS
Dimension Limits
MIN
TYP
MAX
Number of Pins
n
28
Pitch
p
1.27
Overall Height
A
2.36
2.50
2.64
Molded Package Thickness
A2
2.24
2.31
2.39
Standoff §
A1
0.10
0.20
0.30
Overall Width
E
10.01
10.34
10.67
Molded Package Width
E1
7.32
7.49
7.59
Overall Length
D
17.65
17.87
18.08
Chamfer Distance
h
0.25
0.50
0.74
Foot Length
L
0.41
0.84
1.27
Foot Angle Top

0°
4°
8°
Lead Thickness
c
0.23
0.28
0.33
Lead Width
B
0.36
0.42
0.51
Mold Draft Angle Top

0°
12°
15°
Mold Draft Angle Bottom

0°
12°
15°
Notes:
§ Significant Characteristic
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010”
(0.254mm) per side.