Renesas R-Car V3M User manual

V3M Starter Kit
HW Manual
Rev. 2.30 January 2019
RENESAS ADAS
R-CAR / V3M
Y-ASK-RCAR-V3M-WS10
Y-ASK-RCAR-V3M-WS20
Hardware Manual
www.renesas.com
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).

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Notice
1. Descriptions of circuits, software and other related information in this document are provided only to
illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or
system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or
third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any
other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or arising
from the use of Renesas Electronics products or technical information described in this document, including
but not limited to, the product data, drawing, chart, program, algorithm, application examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other
intellectual property rights of Renesas Electronics or others.
4. You shall not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in
whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
you or third parties arising from such alteration, modification, copy or otherwise misappropriation of
Renesas Electronics products.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and
"High Quality". The intended applications for each Renesas Electronics product depends on the product’s
quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment;
audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights);
large-scale communication equipment; key financial terminal systems; safety control
equipment; etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may
pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power
control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics
disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use
of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. When using the Renesas Electronics products, refer to the latest product information (data sheets, user’s
manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas
Electronics with respect to maximum ratings, operating power supply voltage range, heat radiation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions or
failure or accident arising out of the use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics
products, semiconductor products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to
radiation resistance design. Please ensure to implement safety measures to guard them against the possibility
of bodily injury, injury or damage caused by fire, and social damage in the event of failure or malfunction
of Renesas Electronics products, such as safety design for hardware and software including but not limited
to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any
other appropriate measures by your own responsibility as warranty for your products/system. Because the

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evaluation of microcomputer software alone is very difficult and not practical, please evaluate the safety of
the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the
environmental compatibility of each Renesas Electronics product. Please investigate applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU
RoHS Directive carefully and sufficiently and use Renesas Electronics products in compliance with all these
applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses
occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You shall not use Renesas Electronics products or technologies for (1) any purpose relating to
the development, design, manufacture, use, stockpiling, etc., of weapons of mass destruction, such as nuclear
weapons, chemical weapons, or biological weapons, or missiles (including unmanned aerial vehicles
(UAVs)) for delivering such weapons, (2) any purpose relating to the development, design, manufacture, or
use of conventional weapons, or (3) any other purpose of disturbing international peace and security, and
you shall not sell, export, lease, transfer, or release Renesas Electronics products or technologies to any third
party whether directly or indirectly with knowledge or reason to know that the third party or any other party
will engage in the activities described above. When exporting, selling, transferring, etc., Renesas Electronics
products or technologies, you shall comply with any applicable export control laws and regulations
promulgated and administered by the governments of the countries asserting jurisdiction over the parties or
transactions.
10. Please acknowledge and agree that you shall bear all the losses and damages which are incurred from the
misuse or violation of the terms and conditions described in this document, including this notice, and hold
Renesas Electronics harmless, if such misuse or violation results from your resale or making Renesas
Electronics products available any third party.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without
prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information
contained in this document or Renesas Electronics products.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also
includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas
Electronics.
(Rev.3.0-1 November 2016)

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General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For
detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as
any technical updates that have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accordance with the directions given under Handling of Unused Pins in the
manual.
⎯The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI,
an associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled
as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
⎯When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
⎯The characteristics of Microprocessing unit or Microcontroller unit products in the same group but
having a different part number may differ in terms of the internal memory capacity, layout pattern,
and other factors, which can affect the ranges of electrical characteristics, such as characteristic
values, operating margins, immunity to noise, and amount of radiated noise. When changing to a
product with a different part number, implement a system-evaluation test for the given product.

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How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the SoC. It is intended for users designing application systems incorporating the SoC. A basic
knowledge of electric circuits, logical circuits, and SoCs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the
body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the
text of the manual for details.
Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be
obtained from the Renesas Electronics Web site.
Document
Type
Description
Document Title
Document No.
User’s manual
for Hardware
Hardware specifications (pin assignments, memory maps,
peripheral function specifications, electrical characteristics,
timing charts) and operation description
Note: Refer to the application notes for details on using
peripheral functions.
xxx/xx Group
User’s Manual:
Hardware
This User’s manual
Renesas
Technical
Update
Product specifications, updates on documents, etc.

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2. Notation of Numbers and Symbols
The symbol “#” suffixed to the pin (or signal) name means that the pins (or signals) are active “L”.

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4. List of Abbreviations and Acronyms
Abbreviation
Full Form
CPLD
Complex Programmable Logic Device
GPIO
General Purpose Input Output
SoC
System on a Chip
JTAG
Joint Test Action Group
SPI
Serial Peripheral Interface
QSPI
Quad Serial Peripheral Interface
CoM-Express
Computer on Module - Express
HSSTP
High Speed Serial Trace Probe (for High Speed Debugging)
LVDS
Low-voltage differential signaling (for video output and High Speed Debugging)
HDMI
High-Definition Multimedia Interface
USB
Universal Serial Bus
GUI
Graphical User Interface
PMIC
Power Management Integrated Circuit
RGMII
Reduced gigabit media-independent interface
DIPSW
Dual In-line Package Switch
IPL
Initial Program Loader
All trademarks and registered trademarks are the property of their respective owners.

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Contents
1. Introduction......................................................................................................................................12
1.1 General Function..................................................................................................................................................... 12
1.2 Power requirement.................................................................................................................................................. 14
1.3 Order codes............................................................................................................................................................. 14
1.4 Operating conditions............................................................................................................................................... 14
1.5 V3M Starter Kit block diagram .............................................................................................................................. 15
1.6 Board releases......................................................................................................................................................... 16
1.7 Fan connector pinout............................................................................................................................................... 16
2. SoC Mode ........................................................................................................................................17
3. Connectors / LEDs / Components....................................................................................................19
3.1 Connectors.............................................................................................................................................................. 19
3.2 JTAG Connector..................................................................................................................................................... 20
3.3 Switches.................................................................................................................................................................. 20
3.4 LEDs....................................................................................................................................................................... 21
3.5 Components ............................................................................................................................................................ 22
4. V3M Starter Kit Configuration Tool ...............................................................................................23
4.1 First use................................................................................................................................................................... 23
4.2 Configuration tool overview................................................................................................................................... 23
4.3 Volatile/Non-volatile .............................................................................................................................................. 24
4.4 Terminal blocking virtual COM ports..................................................................................................................... 24
4.5 SCIF disabled by hardware..................................................................................................................................... 24
5. Flash Memory Selection..................................................................................................................26
5.1 Multiplexing drawing.............................................................................................................................................. 26
5.2 Flash Memory Selection (via CPLD/GUI).............................................................................................................. 26
5.3 Boot Memory Selection.......................................................................................................................................... 27
5.4 Selection via SW4 switch ....................................................................................................................................... 28
5.5 eMMC memory....................................................................................................................................................... 29
6. LVDS...............................................................................................................................................30
6.1 Multiplexing drawing.............................................................................................................................................. 30
6.2 Selection (via CPLD/GUI)...................................................................................................................................... 30
7. Trace Connector...............................................................................................................................32
7.1 Pinout...................................................................................................................................................................... 32
7.2 HSSTP over LVDS pins ......................................................................................................................................... 32
8. Ethernet............................................................................................................................................33
8.1 Multiplexing drawing.............................................................................................................................................. 33
8.2 Selection (via CPLD/GUI)...................................................................................................................................... 33
9. Software LEDs.................................................................................................................................34
9.1 LED 6 / LED 7 / LED 8 switching (via CPLD)...................................................................................................... 34
10. Software DIPSW............................................................................................................................35
10.1 Drawing of configuration........................................................................................................................................ 35
10.2 SW5 available depending on CPLD ....................................................................................................................... 36
11. Power switching for domains VDDQ_DU and VDDQ_VIN01....................................................37
11.1 Overview................................................................................................................................................................. 37
11.2 Drawing of configuration........................................................................................................................................ 37

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11.3 Power up sequence for 3.3V................................................................................................................................... 37
11.4 Power settings configuration................................................................................................................................... 38
12. Reset...............................................................................................................................................39
12.1 Drawing of configuration........................................................................................................................................ 39
13. Serial communications...................................................................................................................40
13.1 Overview................................................................................................................................................................. 40
13.2 SCIF0 block diagram.............................................................................................................................................. 40
14. Booting by SCIF0 (Serial Interface)..............................................................................................41
14.1 Booting procedure................................................................................................................................................... 41
14.2 Terminal.................................................................................................................................................................. 41
14.3 Uploading Mini-Monitor......................................................................................................................................... 42
15. Procedure for flashing on-board QSPI and Hyper-Flash memories..............................................44
15.1 Hardware set-up...................................................................................................................................................... 44
15.2 QSPI Flash Erasing................................................................................................................................................. 44
15.3 Writing the boot loader (IPL) to the QSPI (sector 1).............................................................................................. 45
15.4 Hyper-Flash Erasing ............................................................................................................................................... 46
15.5 Writing the boot loader (IPL) to the Hyper-Flash (sector 1)................................................................................... 47
16. V3M device hardware pin allocation.............................................................................................48
16.1 GPIO table .............................................................................................................................................................. 48
17. Daughter boards.............................................................................................................................51
18. List of known limitations...............................................................................................................52
18.1 QSPI speed limitation ............................................................................................................................................. 52
18.2 eMMC availability.................................................................................................................................................. 52
18.3 Initial power-up....................................................................................................................................................... 52
18.4 HDMI EDID read errors......................................................................................................................................... 52
18.5 Multiplexors and Switches...................................................................................................................................... 52
18.6 CPLD updates......................................................................................................................................................... 52
19. Attachments ...................................................................................................................................53
19.1 Schematic................................................................................................................................................................ 53
19.2 Mechanical drawing................................................................................................................................................ 53
19.3 CoM-Express pin out.............................................................................................................................................. 53

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Figures
Figure 1. ASK-RCAR-V3M-WS10 Starter Kit top view............................................................................................... 12
Figure 2. ASK-RCAR-V3M-WS10 Starter Kit bottom view........................................................................................ 12
Figure 3. Power connector definition.............................................................................................................................. 14
Figure 4. V3M Starter Kit block diagram...................................................................................................................... 15
Figure 5. CPLD and SW4 multiplexing diagram........................................................................................................... 17
Figure 6. SW4 or CPLD selection.................................................................................................................................... 18
Figure 7. Connectors placement top view....................................................................................................................... 19
Figure 8. Connectors placement bottom view................................................................................................................ 19
Figure 9. Switches placement top view............................................................................................................................ 20
Figure 10. Top view of the board. LEDs position........................................................................................................... 21
Figure 11. Component position on top side. ................................................................................................................... 22
Figure 12. Component position on bottom side.............................................................................................................. 22
Figure 13. Device manager view. Check for COMx ports............................................................................................. 23
Figure 14. V3M Starter Kit configuration tool. ............................................................................................................. 24
Figure 15. Routing SCIF0 to CoM-Express connector.................................................................................................. 25
Figure 16. Flash memories multiplexing drawing.......................................................................................................... 26
Figure 17. Flash memory selection.................................................................................................................................. 27
Figure 18. Mode settings by register or by DIP SW4 selection..................................................................................... 27
Figure 19. SoC Mode interface........................................................................................................................................ 27
Figure 20. Write CPLD.................................................................................................................................................... 28
Figure 21. eMMC block diagram.................................................................................................................................... 29
Figure 22. LVDS path multiplexing. ............................................................................................................................... 30
Figure 23. LVDS and HDMI selection using the configuration tool............................................................................. 31
Figure 24. Ethernet RGMII interface multiplexing....................................................................................................... 33
Figure 25. Ethernet selection. .......................................................................................................................................... 33
Figure 26. LED switching................................................................................................................................................. 34
Figure 27. SW5 drawing of configuration. ..................................................................................................................... 35
Figure 28. SW5 switching by CPLD................................................................................................................................ 36
Figure 29. Power switching.............................................................................................................................................. 37
Figure 30. Power-up sequence......................................................................................................................................... 37
Figure 31. VDDQ_VIN01 voltage at start-up when set to 3.3V.................................................................................... 38
Figure 32. Power settings configuration ......................................................................................................................... 38
Figure 33. Reset drawing of configuration. .................................................................................................................... 39
Figure 34. SCIF0 block diagram..................................................................................................................................... 40
Figure 35. Boot source selection. ..................................................................................................................................... 41
Figure 36. Terminal configuration.................................................................................................................................. 41
Figure 37. Ready to receive code..................................................................................................................................... 42
Figure 38. Tera-Term. Send Mini-Monitor to the System RAM.................................................................................. 42
Figure 39. Upload process................................................................................................................................................ 42
Figure 40. Command terminal......................................................................................................................................... 43
Figure 41. QSPI device selection...................................................................................................................................... 44
Figure 42. Mini-Mon memory erase................................................................................................................................ 45
Figure 43. Memory erase.................................................................................................................................................. 45
Figure 44. Mini-Mon load program to QSPI flash......................................................................................................... 45
Figure 45. Program area selection................................................................................................................................... 46
Figure 46. QSPI device selection...................................................................................................................................... 46
Figure 47. Memory erase process.................................................................................................................................... 47
Figure 48. Daughter board example................................................................................................................................ 51

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Tables
Table 1. Board functions.................................................................................................................................................. 12
Table 2. Order codes......................................................................................................................................................... 14
Table 3. Fan connector pinout......................................................................................................................................... 16
Table 4. SoC mode............................................................................................................................................................ 18
Table 5. Connectors.......................................................................................................................................................... 19
Table 6. JTAG Connector pinout.................................................................................................................................... 20
Table 7. Switch description.............................................................................................................................................. 20
Table 8. LEDs description................................................................................................................................................ 21
Table 9. List of components. ............................................................................................................................................ 22
Table 10. Boot source selection........................................................................................................................................ 28
Table 11. HSSTP connector pinout................................................................................................................................. 32
Table 12. GPIO table........................................................................................................................................................ 48

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1. Introduction
Figure 1. ASK-RCAR-V3M-WS10 Starter Kit top
view.
Figure 2. ASK-RCAR-V3M-WS10 Starter Kit bottom
view.
1.1 General Function
The ADAS R-CAR V3M Starter Kit is designed to support development of automotive applications based on the SoC
R-CAR V3M from Renesas Electronics.
Table 1. Board functions
Board
Function
Item
Description
Note
CPU
ARM CA53 (ARMv8)
800 MHz dual core, with
NEON/VFPv4, L1$ I/D
32K/32K, L2$ 512K
ARM CR7 (ARMv7)
800 MHz, with VFPv3,
L1$ I/D 32K/32K, I/D-
TCM 32K/32K, lock-
step
Memory
SoC Internal
448KBytes System
RAM
DDR
2 GBytes (6.4
GBytes/s)
DDR3L-1600, 32-bit
wide
Hyper-Flash
(Bootable)
64 MiBytes Hyper-Flash
(RPC, reduced pin-
count)
(512 Mbits, 160 MHz,
320 MBytes/s)
Alternatively to on-board
Hyper/QSPI flash memory: 2ch
QSPI
(max. 80 MHz, 80 MBytes/s)
QSPI Flash
(Bootable)
64MiBytes QSPI (512
Mbits, 80 MHz, 80
MBytes/s)

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eMMC
16 to 32GiBytes eMMC
(HS200) [available only
for PCB V3.00 and later]
Available
Parallel SRAM/ROM
(Bootable)
-
Available (shared with many other
functions)
Video out
HDMI
No native HDMI; derived
from LVDS by converter
HDMI connector (type A,
19 pins)
HDMI 1.4, up to
1080p60, 148.5 MHz,
(no audio)
Alternatively to on-board connector
(shared with trace and LVDS)
RGB (Parallel)
-
RGB888 (Shared with many other
functions)
LVDS
-
1 channel (4+1CLK differential pairs)
TIA/EIA-644, max 148.5 MHz,
(shared with trace and HDMI)
Video in
Serial
-
MIPI-CSI2, 1 channel (4-lanes)
VC/DT supported, up to
1.5Gbps/lane
Parallel
-
2 channels, RGB/YCbCr/Raw, max
100 MHz
(shared with many other functions)
Interfaces
EthAVB
PHY + RJ45 connector
(100/1000)
Alternatively to on-board PHY:
RGMII V1.3 interface (2.5V)
SCIF
1 channel via Mini-USB-
B (via FT232 USB-to-
UART bridge)
Up to 3 additional channels (shared)
(on-board channel optionally)
HSCIF
-
Up to 4 channels (shared)
MSIOF (SPI)
-
Up to 4 channels (SPI/IIS,
master/slave, 66 MHz) (shared)
CAN-FD
-
Up to 2 channels, 8Mbps (shared)
I2C
For on-board
peripherals
Up to 5 channels, 400kHz,
master/slave (shared)
DigRF
-
Available
Timer
PWM
-
Up to 5 channels (shared)
HMI
output
3 LEDs at GPIOs
-
input
4 DIP-switches at
GPIOs
-
ADC
-
8 channels, 12-bit
GPIOs
-
14 GPIOs by default, up to 105
GPIOs (shared)
Reset
Reset button (and LED)
Input and output
Power
5V/3A input
PMIC for all required
voltages (OTP)
Power-up/down signals
Power-good status
Boot Source
Hyper-Flash, QSPI,
SCIF, JTAG debugger
QSPI Flash, SCIF, JTAG debugger,
parallel ROM
Debug IF
JTAG debug
20-pin (2.54mm)
ARM_EML
(“Lauterbach”)
Available
JTAG trace
EMT-A53-16K/R7-4K
Available

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1.2 Power requirement
Special attention must be paid when using the power supply. Use only the 5V/3A power supply provided on the Starter
Kit. Higher voltages may damage permanently the R-CAR V3M Starter Kit.
Power connector counterpart type: diameter 5.5mm, center pin 2.0mm, insertion depth 8.85mm.
Note that the V3M Starter Kit powers-up directly, there is no power switch.
The SW1 and SW2 have no function.
Figure 3. Power connector definition.
1.3 Order codes
Table 2. Order codes.
Boards
Order Codes
V3M Starter Kit. SoC silicon version 1.0
Y-ASK-RCAR-V3M-WS10
V3M Starter Kit. SoC silicon version 2.0
Y-ASK-RCAR-V3M-WS20
1.4 Operating conditions
This board is intended to operate within the temperature range of 0 °C –40 °C.
Parallel trace
On-board connector for
HSSTP probe (shared
with LVDS)
Available (shared with LVDS and
HDMI)
Clocks
All necessary clocks on-
board
-
Mode
Can be configured by
CPLD, DIPSW, USB or
software
-
Cooling
Heat-sink and fan
-
Expansion
-
CoM Express connector (440-pin)
backwards-compatible to H3 Starter
Kit
Interrupts
-
NMI, IRQ on GPIOs
Size
95 x 95 mm (equivalent
to CoM Express type 6)
-
SoC
Soldered
-

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1.5 V3M Starter Kit block diagram
Figure 4. V3M Starter Kit block diagram
QSPI0
QSPI1 V3M SoC
SCIF0
JTAG
MD (Mode Pins)
DU_DOTCLKIN
EXTAL
EXTALR
LEDS
LED1: Power 3.3V
LED2: Power 5V
LED3: Reset#
LED4: SeriaI
LED5: Serial
LED6: User Led
LED7: User Led
LED8: User Led
V3M Starter Kit
Block Diagram
Rev 1.4
2019.01.18
DDR3L
1GiB DDR3L-1600
MT41K512M16
DDR3L
1GiB DDR3L-1600
MT41K512M16
HyperFlash
64 MiB
S26KS512S
QSPI Flash
64 MiB
S25FS512
eMMC HS200
8 to 32 GiB
PMIC
DA9063L
USB to Serial
FT232RL
Mini-USB
CN9:
CPLD 1
MAX V
5M570ZM100
CPLD 2
MAX V
5M570ZM100
Ethernet
PHY
KSZ9031 RJ45
LVDS-> RGB
THC63LVD1024
HDMI
Transmitter
ADV7511
HSSTP
CN1:
HDMI TypeA
CN2:
FAN
CN4:
POWER
CN5:
Reserved
CN7:
JTAG
CN6:
MODE
SW4
DIP SWITCH 8pos
User SW
SW5
DIP SWITCH 4pos
LED6
LED7
LED8
Symplified block diagram
MODE_PINS
VDDQ_VIN01
VDDQ_DU
CoM-Express
CN3:
Power Switch
LTC4415
3.3V
1.8V
Power Switch
LTC4415
3.3V
1.8V
SW7
SW6
SEL_DU
SEL_VIN01
SCIF0
CONFIGURATION
CoM-Express
CN3:
SW3 RESET#
JTAG
CN6:
HSSTP
CN1:
VCC_1.0V
VCC_1.35V
VCC_1.8V
VCC_3.3V
CoM-Express
CN3:
System Clock
16.66 MHz
RCLK
32.768 KHz
DU Dot clock
148.5 MHz
SCIF Clock
14.7456 MHz
SCIF_CLK
CoM-Express
CN3:
VDDQ_VIN01
VDDQ_DU
eMMC
CoM-Express
CN3:
External
QSPI
External
HyperFlash QSPI1
QSPI1
QSPI0
QSPI0
SW4.8
CPLD1 MD[4:1]
CPLD1
CPLD1
CPLD1
LVDS
EthAVB (RGMII)
CoM-Express
CN3:
CPLD1
PRESET#
PRESETOUT#
RESET_FROM_COMEXPRESS#
PRESET#
HSSTP
CN1:
RGB888
CoM-Express
CN3:
CSI0 4 Lanes + Clock
4x SCIF
4x HSCIF
4x MSIOF
2x CAN-FD
5x I2C (400KHz)
DigRF
5x PWM
8x ADC
14 GPIOs + 105 Shared
NMI, IRQ
1: GND
2: 5V
3: N.C
VCC_2.5V
CN3:
CoM-Express
I2C0
0-ohm N.A.
VDDQ_VIN01
VDDQ_DU

R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30 Page 16 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
1.6 Board releases
[DS] Design Sample: main test coverage
[ES] Engineering Sample: Function test coverage 80%
[CS] Customer sample: Functional test coverage 100% pass
[MP] Mass Production: CE and temperature test pass
1.7 Fan connector pinout
Table 3. Fan connector pinout
Pin Number
Description
1
PWM#
2
5V
3
N.C.

R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30 Page 17 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
2. SoC Mode
The SoC mode is configured by using dedicated GPIO pins on the SoC. These pins are driven by a CPLD which is the
responsible to set up the GPIOs during reset.
The CPLD contains a register where the SoC mode configuration is stored. Some of the configuration bits of the SoC
register are accessible through the DIP switch 4 (SW4) available on the board. The rest of the bits have a default value.
The preset values are shown in the Table 4. It is possible to write the CPLD register via proprietary CPLD interface or from
PC with the GUI provided by Renesas. The SoC is also connected to the CPLD interface and can modify the SoC mode
register if it is necessary.
Figure 5. CPLD and SW4 multiplexing diagram.
The CPLD contains a multiplexer to select the Boot Mode configuration source either from the SW4 or from the internal
register. This should be defined with the GUI under the tab “SOC mode configuration” and then selecting the desired option
on the “MODE setting” checkbox as shown in the figure 4.
REG
MUX
Reset
CPLD R-Car V3M
PC
SW4
Reset
Reset
Mode
Pins
MDxx

R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30 Page 18 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
Figure 6. SW4 or CPLD selection.
Table 4. SoC mode.
Mode
Switch
Description
L / ON
H / OFF
Default
MD0
Free running
Prohibited
LOW
MD1
SW4.1
Boot device selection [0]
L
H
ON
MD2
SW4.2
Boot device selection [1]
L
H
ON
MD3
SW4.3
Boot device selection [2]
L
H
OFF
MD4
SW4.4
Boot device selection [3]
L
H
ON
MD5
SW4.5
Secure authorization
Enabled
Disabled
OFF
MD7
SW4.6
Master boot processor
A53 (CPU0)
CR7
OFF
MD8
Databus width of Area 0 space
8 bit
16 bit
LOW
MD9
EXTAL/XTAL
Clock
Crystal
LOW
MD13
EXTAL input frequency [0]
LOW
MD14
EXTAL input frequency [1]
LOW
MD15
SW4.7
Architecture Selection
AArch32
AArch64
OFF
MD16
Reserved. Fix to H
HIGH
MD18
CLKOUT frequency setting
66.67 MHz
44.44 MHz
LOW
MD19
DDR clock frequency
DDR 1600
(800 MHz)
DDR 1333
(666.67 MHz)
LOW
MD21
Debugging mode
Disabled
Coresight
HIGH
MD23
Field BIST mode
Mode 0
Mode 1
LOW
MD25
Field BIST mode
Disabled
Enabled
LOW
MD26
Reserved. Fix to L
LOW

R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30 Page 19 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
3. Connectors / LEDs / Components
3.1 Connectors
Figure 7. Connectors placement top view.
Figure 8. Connectors placement bottom view.
Table 5. Connectors.
Connector
Type
Function
CN1
ERF8-020-05.0-L-DV-L-K-TR
HSSTP Connector
CN2
HMDI Type-A
HDMI Output
CN3
TYCO ELECTRONICS 3-5353652-6 (*)
COM Express Interface
CN4
Header 3 way
Fan Connector
CN5
PJ-063AH
Power Input (5V/3A)
CN6
Header 20 way shrouded SMD
JTAG / TRACE
CN7
-
Internal Use
IC8
J0G-0001NL
Ethernet Connector 100Mbps/1Gpbs
CN9
Mini-B USB
Serial SCIF0
(*) Mating type on top side of an application board: TYCO ELECTRONICS 3-1827231-6
CN7
HDMI ETHERNET
POWER 5V/3A
TRACE
SERIALJTAG
CN4
FAN
CN2 IC8
CN5
CN1
CN6 CN9
CN4
VSS
5V
NC
CoM-Express 440 Pin
CN3

R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30 Page 20 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
3.2 JTAG Connector
Table 6. JTAG Connector pinout.
Pin
Number
Function
I/O
Level
Remark
Pin
Number
Function
I/O
Level
Remark
1
VTREF
O
1.8V
-
2
VSUPPLY
I
1.8V
Not
connected
3
TRST#
I
1.8V
-
4
GND
-
0V
-
5
TDI
I
1.8V
-
6
GND
-
0V
-
7
TMS
I
1.8V
-
8
GND
-
0V
-
9
TCK
I
1.8V
-
10
GND
-
0V
-
11
N.C.
O
1.8V
-
12
GND
-
0V
-
13
TDO
O
1.8V
-
14
GND
-
0V
-
15
PRESET#
I/O
1.8V
Open
Drain
16
GND
-
0V
-
17
N.C.
-
-
-
18
GND
-
0V
-
19
N.U.
-
-
Not used
20
GND
-
0V
-
3.3 Switches
Figure 9. Switches placement top view
Table 7. Switch description
Switch
Function
SW3
Reset
SW4
Mode configuration
SW5
GPIO input and user LEDs
SW6
VCC_VDDQ_DU Select
3.3V or set by CPLD
SW7
VCC_VDDQ_VIN01 Select
3.3V or set by CPLD
SW5
SW4
SW3
SW6 SW7