Renesas M16C/50 Series User manual

RENESAS MCU
M16C Family / M16C/50 Series
Rev.1.10 Sep 2011
16
All information contained in these materials, including products and product specifications, represents
information on the product at the time of publication and is subject to change by Renesas Electronics
Corp. without notice. Please review the latest informaton published by Renesas Electronics Corp.
through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).
User's Manual
www.renesas.com
M16C/5L Group, M16C/56 Group
User’s Manual: Hardware
User's Manual: Hardware

Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.

About This Manual
1. Purpose and Target User
This manual is designed to be read primarily by application developers who have an understanding of this
microcomputer (MCU) including its hardware functions and electrical characteristics. The user should have
a basic understanding of electric circuits, logic circuits and, MCUs.
This manual consists of six main categories: Overview, CPU, System Control, Peripherals, Electrical
Characteristics, and Usage Notes.
The M16C/5L Group, M16C/56 Group includes the documents listed below. Verify this manual is the latest
version by visiting the Renesas Electronics website.
Carefully read all notes in this document prior to use. Notes are found throughout each chapter, at the end
of each chapter, and in the dedicated Usage Notes chapter.
The Revision History at the end of this manual summarizes primary modifications and additions to the
previous versions. For details, please refer to the relative chapters or sections of this manual.
Type of Document Contents Document Name Document Number
Datasheet Overview of Hardware and Electrical
Characteristics M16C/5L Group, M16C/56 Group
Datasheet
R01DS0035EJ0110
User’s Manual:
Hardware Specifications and detailed descriptions of:
-pin layout
-memory map
-peripherals
-electrical characteristics
-timing characteristics
Refer to the Application Manual for
peripheral usage.
M16C/5L Group,
M16C/56 Group
User’s Manual:
Hardware
This publication
User’s Manual:
Software/Software
Manual
Descriptions of instruction set M16C/60, M16C/20,
M16C/Tiny Series
Software Manual
REJ09B0137
Application Note -Usages
-Applications
-Sample programs
-Programming technics using
Assembly language or C
programming language
Available on the Renesas Electronics
website.
Renesas Technical
Update Bulletins on product specifications, documents, etc.

2. Numbers and Symbols
The following explains the denotations used in this manual for registers, bits, pins and various numbers.
(1) Registers, bits, and pins
Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier
after the symbol.
Example: PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Numbers
A binary number has the suffix “b” except for a 1-bit value.
A hexadecimal number has the suffix “h”.
A decimal number has no suffix.
Example: Binary notation: 11b
Hexadecimal notation: EFA0h
Decimal notation: 1234

3. Registers
The following illustration describes registers used throughout this manual.
Symbol
EXAMPLE Address 9999h Reset Value 000X 1X00b
Example Register
Bit Symbol Bit Name Description
AAAA0 Example bit 0
RW
0 1 b0b7 b6 b5 b4 b3 b2 b1
RW
AAAA1 RW
Reserved Set this bit to 1. RW
Reserved Set this bit to 0. The read value is
undefined. RW
WO
AAAA6 Example bit 1 Functions vary with operating modes WO
Example flag RO
b2 b1
0 0 : XX function
0 1 : YY function
1 0 :Do not set this value.
1 1 : ZZ function
—
(b2) No register bit. If necessary, set this bit to 0. The read value is undefined. —
—
(b3)
—
(b4)
AAAA5
AAAA7 0: Example detected
1: Example not detected
See Note 1 See Note 2
See Note 4
See Note 3
Notes:
1. Blank box: Set this bit to 0 or 1 according to the function.
0: Set this bit to 0.
1: Set this bit to 1.
X: Nothing is assigned to this bit.
2. RW: Read and write
RO: Read only
WO: Write only (the read value is undefined)
—: Not applicable
3. Reserved bit: This bit field is reserved. Set this bit to a specified value. For RW bits, the written value is
read unless otherwise noted.
4.
yNo register bit(s): No register bit(s) is/are assigned to this field. If necessary, set to 0 for possible future
implementation.
yDo not use this combination: Proper operation is not guaranteed when this value is set.
yFunctions vary with operating modes: Functions vary with peripheral operating modes. Refer to register
illustrations of the respective mode.

4. Abbreviations and Acronyms
The following acronyms and terms are used throughout this manual.
All trademarks and registered trademarks are the property of their respective owners.
Abbreviation/Acronym Meaning
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment Bus
I/O Input/Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connection
PLL Phase Locked Loop
PWM Pulse Width Modulation
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator

A- 1
Quick Reference ...............................................................................................................B-1
1. Overview ..................................................................................................1
1.1 Features........................................................................................................................................ 1
1.1.1 Applications ......................................................................................................................... 1
1.2 Specifications................................................................................................................................ 2
1.3 Product List................................................................................................................................... 6
1.4 Block Diagram .............................................................................................................................. 8
1.5 Pin Assignments......................................................................................................................... 10
1.6 Pin Functions.............................................................................................................................. 16
2. Central Processing Unit (CPU)...............................................................19
2.1 Data Registers (R0, R1, R2, and R3).........................................................................................20
2.2 Address Registers (A0 and A1).................................................................................................. 20
2.3 Frame Base Register (FB).......................................................................................................... 20
2.4 Interrupt Table Register (INTB)................................................................................................... 20
2.5 Program Counter (PC)................................................................................................................ 20
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................................... 20
2.7 Static Base Register (SB)........................................................................................................... 20
2.8 Flag Register (FLG).................................................................................................................... 20
2.8.1 Carry Flag (C Flag) ............................................................................................................ 20
2.8.2 Debug Flag (D Flag) .......................................................................................................... 20
2.8.3 Zero Flag (Z Flag) .............................................................................................................. 20
2.8.4 Sign Flag (S Flag) .............................................................................................................. 20
2.8.5 Register Bank Select Flag (B Flag) ................................................................................... 20
2.8.6 Overflow Flag (O Flag) ...................................................................................................... 20
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................. 21
2.8.8 Stack Pointer Select Flag (U Flag) .................................................................................... 21
2.8.9 Processor Interrupt Priority Level (IPL) ............................................................................. 21
2.8.10 Reserved Areas ................................................................................................................. 21
3. Memory ..................................................................................................22
4. Special Function Registers (SFRs) ........................................................24
4.1 SFRs........................................................................................................................................... 24
4.2 Notes on SFRs ........................................................................................................................... 55
4.2.1 Register Settings ............................................................................................................... 55
5. Protection...............................................................................................57
5.1 Introduction................................................................................................................................. 57
5.2 Register ...................................................................................................................................... 57
Table of Contents

A- 2
5.2.1 Protect Register (PRCR) ...................................................................................................57
5.3 Notes on Protection.................................................................................................................... 59
6. Resets....................................................................................................60
6.1 Introduction................................................................................................................................. 60
6.2 Registers..................................................................................................................................... 62
6.2.1 Processor Mode Register 0 (PM0) .................................................................................... 62
6.2.2 Reset Source Determine Register (RSTFR) ..................................................................... 63
6.3 Optional Function Select Area.................................................................................................... 64
6.3.1 Optional Function Select Address 1 (OFS1) ..................................................................... 64
6.4 Operations.................................................................................................................................. 66
6.4.1 Status after Reset .............................................................................................................. 66
6.4.2 Hardware Reset ................................................................................................................. 68
6.4.3 Power-On Reset Function ................................................................................................. 69
6.4.4 Voltage Monitor 0 Reset .................................................................................................... 70
6.4.5 Voltage Monitor 2 Reset .................................................................................................... 70
6.4.6 Oscillator Stop Detect Reset ..............................................................................................70
6.4.7 Watchdog Timer Reset ......................................................................................................70
6.4.8 Software Reset .................................................................................................................. 71
6.5 Notes on Resets......................................................................................................................... 72
6.5.1 Power Supply Rising Gradient ........................................................................................... 72
6.5.2 Power-On Reset ................................................................................................................ 72
6.5.3 OSDR Bit (Oscillation Stop Detect Reset Detect Flag) ...................................................... 72
6.5.4 Hardware Reset When VCC < Vdet0 ................................................................................ 72
7. Voltage Detector.....................................................................................73
7.1 Introduction................................................................................................................................. 73
7.2 Registers..................................................................................................................................... 74
7.2.1 Voltage Detector 2 Flag Register (VCR1) .......................................................................... 75
7.2.2 Voltage Detector Operation Enable Register (VCR2) ........................................................ 76
7.2.3 Voltage Monitor Function Select Register (VWCE) ........................................................... 77
7.2.4 Voltage Detector 2 Level Select Register (VD2LS) ........................................................... 78
7.2.5 Voltage Monitor 0 Control Register (VW0C) ...................................................................... 79
7.2.6 Voltage Monitor 2 Control Register (VW2C) ...................................................................... 80
7.3 Optional Function Select Area.................................................................................................... 82
7.3.1 Optional Function Select Address 1 (OFS1) ..................................................................... 82
7.4 Operations.................................................................................................................................. 83
7.4.1 Digital Filter ........................................................................................................................ 83
7.4.2 Voltage Detector 0 ............................................................................................................. 84
7.4.3 Voltage Detector 2 ............................................................................................................. 86
7.5 Interrupts..................................................................................................................................... 89

A- 3
8. Clock Generator.....................................................................................90
8.1 Introduction................................................................................................................................. 90
8.2 Registers..................................................................................................................................... 92
8.2.1 System Clock Control Register 0 (CM0) ............................................................................ 93
8.2.2 System Clock Control Register 1 (CM1) ............................................................................ 95
8.2.3 Oscillation Stop Detection Register (CM2) ........................................................................ 97
8.2.4 Peripheral Clock Select Register (PCLKR) ....................................................................... 99
8.2.5 PLL Control Register 0 (PLC0) ........................................................................................ 100
8.2.6 Processor Mode Register 2 (PM2) .................................................................................. 101
8.2.7 40 MHz On-Chip Oscillator Control Register 0 (FRA0) ................................................... 102
8.2.8 40 MHz On-Chip Oscillator Control Register 2 (FRA2) ................................................... 103
8.3 Clocks Generated by Clock Generators................................................................................... 104
8.3.1 Main Clock ....................................................................................................................... 104
8.3.2 PLL Clock ........................................................................................................................ 105
8.3.3 fOCO40M ........................................................................................................................ 106
8.3.4 fOCO-F ............................................................................................................................ 106
8.3.5 125 kHz On-Chip Oscillator Clock (fOCO-S) ................................................................... 106
8.3.6 Sub Clock (fC) ................................................................................................................. 107
8.4 CPU Clock and Peripheral Function Clocks............................................................................. 108
8.4.1 CPU Clock and BCLK ...................................................................................................... 108
8.4.2 Peripheral Function Clocks (f1, fOCO40M, fOCO-F, fOCO-S, fC32, fC, Main Clock) ..... 108
8.5 Clock Output Function...............................................................................................................110
8.6 System Clock Protection Function.............................................................................................110
8.7 Oscillator Stop/Restart Detect Function.....................................................................................111
8.7.1 Operation When CM27 Bit is 0 (Oscillator Stop Detect Reset) .........................................111
8.7.2 Operation When CM27 Bit is 1 (Oscillator Stop/Restart Detect Interrupt) ........................112
8.7.3 Using the Oscillator Stop/Restart Detect Function ...........................................................113
8.8 Interrupt .....................................................................................................................................113
8.9 Notes on Clock Generator.........................................................................................................114
8.9.1 Oscillator Using a Crystal or a Ceramic Resonator ..........................................................114
8.9.2 Noise Countermeasure .....................................................................................................115
8.9.3 CPU Clock ........................................................................................................................116
8.9.4 Oscillator Stop/Restart Detect Function ............................................................................116
8.9.5 PLL Frequency Synthesizer .............................................................................................117
9. Power Control....................................................................................... 118
9.1 Introduction................................................................................................................................118
9.2 Registers....................................................................................................................................118
9.2.1 Flash Memory Control Register 0 (FMR0) ........................................................................119
9.2.2 Flash Memory Control Register 2 (FMR2) ....................................................................... 120
9.3 Clock......................................................................................................................................... 122

A- 4
9.3.1 Normal Operating Mode .................................................................................................. 122
9.3.2 Clock Mode Transition Procedure ................................................................................... 126
9.3.3 Wait Mode ....................................................................................................................... 129
9.3.4 Stop Mode ....................................................................................................................... 131
9.4 Power Control in Flash Memory ............................................................................................... 133
9.4.1 Stopping Flash Memory ................................................................................................... 133
9.4.2 Reading Flash Memory ................................................................................................... 134
9.5 Reducing Power Consumption................................................................................................. 136
9.5.1 Ports ................................................................................................................................ 136
9.5.2 A/D Converter .................................................................................................................. 136
9.5.3 Stopping Peripheral Functions ......................................................................................... 136
9.5.4 Switching the Oscillation-Driving Capacity ...................................................................... 136
9.6 Notes on Power Control............................................................................................................ 137
9.6.1 CPU Clock ....................................................................................................................... 137
9.6.2 Wait Mode ....................................................................................................................... 137
9.6.3 Stop Mode ....................................................................................................................... 137
9.6.4 Low Current Consumption Read Mode ........................................................................... 138
9.6.5 Slow Read Mode ............................................................................................................. 138
10. Processor Mode...................................................................................139
10.1 Introduction............................................................................................................................... 139
10.2 Registers................................................................................................................................... 140
10.2.1 Processor Mode Register 1 (PM1) .................................................................................. 140
10.2.2 Program 2 Area Control Register (PRG2C) .................................................................... 141
10.2.3 Flash Memory Control Register 1 (FMR1) ....................................................................... 142
10.3 Software Wait............................................................................................................................ 143
10.4 Bus Hold................................................................................................................................... 143
11. Programmable I/O Ports.......................................................................144
11.1 Introduction............................................................................................................................... 144
11.2 I/O Ports and Pins..................................................................................................................... 145
11.3 Registers................................................................................................................................... 152
11.3.1 NMI Digital Debounce Register (NDDR) ......................................................................... 153
11.3.2 P1_7 Digital Debounce Register (P17DDR) .................................................................... 153
11.3.3 Pull-Up Control Register 0 (PUR0) .................................................................................. 154
11.3.4 Pull-Up Control Register 1 (PUR1) .................................................................................. 154
11.3.5 Pull-Up Control Register 2 (PUR2) .................................................................................. 155
11.3.6 Port Control Register (PCR) ............................................................................................ 156
11.3.7 Input Threshold Select Register 0 (VLT0) ....................................................................... 157
11.3.8 Input Threshold Select Register 1 (VLT1) ....................................................................... 158
11.3.9 Input Threshold Select Register 2 (VLT2) ....................................................................... 158

A- 5
11.3.10 Pin Assignment Control Register (PACR) ....................................................................... 159
11.3.11 Port Pi Register (Pi) (i = 0 to 3, 6 to 10) .......................................................................... 160
11.3.12 Port Pi Direction Register (PDi) (i = 0 to 3, 6 to 10) ......................................................... 161
11.4 Peripheral Function I/O............................................................................................................. 162
11.4.1 Peripheral Function I/O and Port Direction Bits ............................................................... 162
11.4.2 Priority Level of Peripheral Function I/O .......................................................................... 162
11.4.3 Digital Debounce Filters .................................................................................................. 163
11.5 Unassigned Pin Handling ......................................................................................................... 165
11.6 Notes on Programmable I/O Ports............................................................................................ 166
11.6.1 Pin Assignment Control ................................................................................................... 166
11.6.2 Influence of SD ................................................................................................................ 166
11.6.3 Input Voltage Threshold ................................................................................................... 166
12. Interrupts..............................................................................................167
12.1 Introduction............................................................................................................................... 167
12.2 Registers................................................................................................................................... 168
12.2.1 Processor Mode Register 2 (PM2) .................................................................................. 170
12.2.2 Interrupt Control Register 1
(BCNIC/TMOSIC, DM0IC to DM3IC, KUPIC,ADIC, S0TIC to S2TIC, S0RIC to S3RIC,
TA0IC to TA4IC, TB0IC to TB2IC, S4TIC/RTCCIC, S4RIC, C0WIC,S3TIC/C0EIC,
RTCTIC C0RIC, C0TIC, C0FRIC, C0FTIC, ICOC0IC, ICOCH0IC, ICOC1IC/IICIC,
ICOCH1IC/SCLDAIC, ICOCH2IC to ICOCH3IC, BTIC) .................................................. 171
12.2.3 Interrupt Control Register 2
(INT3IC, INT5IC, INT4IC, INT0IC to INT2IC) .................................................................. 172
12.2.4 Interrupt Source Select Register 3 (IFSR3A) .................................................................. 173
12.2.5 Interrupt Source Select Register 2 (IFSR2A) .................................................................. 174
12.2.6 Interrupt Source Select Register (IFSR) .......................................................................... 175
12.2.7 Address Match Interrupt Enable Register (AIER) ............................................................ 176
12.2.8 Address Match Interrupt Enable Register 2 (AIER2) ....................................................... 176
12.2.9 Address Match Interrupt Register i (RMADi) (i = 0 to 3) .................................................. 177
12.2.10 NMI Digital Debounce Register (NDDR) ......................................................................... 178
12.2.11 P1_7 Digital Debounce Register (P17DDR) .................................................................... 178
12.3 Types of Interrupts.................................................................................................................... 179
12.4 Software Interrupts ................................................................................................................... 180
12.4.1 Undefined Instruction Interrupt ........................................................................................ 180
12.4.2 Overflow Interrupt ............................................................................................................ 180
12.4.3 BRK Interrupt ................................................................................................................... 180
12.4.4 INT Instruction Interrupt ................................................................................................... 180
12.5 Hardware Interrupts.................................................................................................................. 181
12.5.1 Special Interrupts ............................................................................................................. 181
12.5.2 Peripheral Function Interrupts ......................................................................................... 181
12.6 Interrupts and Interrupt Vectors................................................................................................ 182
12.6.1 Fixed Vector Tables ......................................................................................................... 182

A- 6
12.6.2 Relocatable Vector Tables ............................................................................................... 183
12.7 Interrupt Control........................................................................................................................ 185
12.7.1 Maskable Interrupt Control .............................................................................................. 185
12.7.2 Interrupt Sequence .......................................................................................................... 186
12.7.3 Interrupt Response Time ................................................................................................. 187
12.7.4 Variation of IPL When Interrupt Request is Accepted ..................................................... 187
12.7.5 Saving Registers ............................................................................................................. 188
12.7.6 Returning from an Interrupt Routine ................................................................................ 189
12.7.7 Interrupt Priority ............................................................................................................... 189
12.7.8 Interrupt Priority Level Select Circuit ............................................................................... 189
12.7.9 Multiple Interrupts ............................................................................................................ 191
12.8 INT Interrupt.............................................................................................................................. 191
12.9 NMI Interrupt............................................................................................................................. 192
12.10 Key Input Interrupt.................................................................................................................... 192
12.11 Address Match Interrupt ........................................................................................................... 193
12.12 Non-Maskable Interrupt Source Discrimination........................................................................ 194
12.13 Notes on Interrupts................................................................................................................... 195
12.13.1 Reading Address 00000h ................................................................................................ 195
12.13.2 SP Setting ........................................................................................................................ 195
12.13.3 NMI Interrupt .................................................................................................................... 195
12.13.4 Changing an Interrupt Source ......................................................................................... 196
12.13.5 Rewriting the Interrupt Control Register .......................................................................... 197
12.13.6 Instruction to Rewrite the Interrupt Control Register ....................................................... 197
12.13.7 INT Interrupt .................................................................................................................... 198
13. Watchdog Timer ...................................................................................199
13.1 Introduction............................................................................................................................... 199
13.2 Registers................................................................................................................................... 201
13.2.1 Voltage Monitor 2 Control Register (VW2C) .................................................................... 202
13.2.2 Count Source Protection Mode Register (CSPR) ............................................................ 203
13.2.3 Watchdog Timer Refresh Register (WDTR) .................................................................... 203
13.2.4 Watchdog Timer Start Register (WDTS) .......................................................................... 204
13.2.5 Watchdog Timer Control Register (WDC) ....................................................................... 204
13.3 Optional Function Select Area.................................................................................................. 205
13.3.1 Optional Function Select Address 1 (OFS1) ................................................................... 205
13.3.2 Optional Function Select Address 2 (OFS2) ................................................................... 206
13.4 Operations................................................................................................................................ 207
13.4.1 Refresh Operation Period ................................................................................................ 207
13.4.2 Count Source Protection Mode Disabled ........................................................................ 208
13.4.3 Count Source Protection Mode Enabled ......................................................................... 209
13.5 Interrupts................................................................................................................................... 210

A- 7
13.6 Notes on the Watchdog Timer...................................................................................................211
14. DMAC...................................................................................................212
14.1 Introduction............................................................................................................................... 212
14.2 Registers................................................................................................................................... 214
14.2.1 DMAi Source Pointer (SARi) (i = 0 to 3) .......................................................................... 215
14.2.2 DMAi Destination Pointer (DARi) (i = 0 to 3) ................................................................... 215
14.2.3 DMAi Transfer Counter (TCRi) (i = 0 to 3) ....................................................................... 216
14.2.4 DMAi Control Register (DMiCON) (i = 0 to 3) .................................................................. 217
14.2.5 DMAi Source Select Register (DMiSL) (i = 0 to 3) .......................................................... 218
14.3 Operations................................................................................................................................ 221
14.3.1 DMA Enabled .................................................................................................................. 221
14.3.2 DMA Request .................................................................................................................. 221
14.3.3 Transfer Cycles ............................................................................................................... 222
14.3.4 DMAC Transfer Cycles .................................................................................................... 224
14.3.5 Single Transfer Mode ...................................................................................................... 225
14.3.6 Repeat Transfer Mode ..................................................................................................... 226
14.3.7 Channel Priority and DMA Transfer Timing ..................................................................... 227
14.4 Interrupts................................................................................................................................... 228
14.5 Notes on DMAC........................................................................................................................ 229
14.5.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) ............................................. 229
14.5.2 Changing the DMA Request Source ............................................................................... 229
15. Timer A.................................................................................................230
15.1 Introduction............................................................................................................................... 230
15.2 Registers................................................................................................................................... 233
15.2.1 Peripheral Clock Select Register (PCLKR) ..................................................................... 234
15.2.2 Clock Prescaler Reset Flag (CPSRF) ............................................................................. 234
15.2.3 Timer AB Division Control Register 0 (TCKDIVC0) ......................................................... 235
15.2.4 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) ........................................... 236
15.2.5 16-bit Pulse Width Modulation Mode Function Select Register (PWMFS) ...................... 237
15.2.6 Timer A Waveform Output Function Select Register (TAPOFS) ..................................... 238
15.2.7 Timer A Output Waveform Change Enable Register (TAOW) ......................................... 239
15.2.8 Timer Ai Register (TAi) (i = 0 to 4) ................................................................................... 240
15.2.9 Timer Ai-1 Register (TAi1) (i = 1, 2, 4) ............................................................................. 241
15.2.10 Count Start Flag (TABSR) ...............................................................................................241
15.2.11 One-Shot Start Flag (ONSF) ........................................................................................... 242
15.2.12 Trigger Select Register (TRGSR) .................................................................................... 243
15.2.13 Increment/Decrement Flag (UDF) ................................................................................... 244
15.2.14 Timer Ai Mode Register (TAiMR) (i = 0 to 4) ................................................................... 245
15.3 Operations................................................................................................................................ 246

A- 8
15.3.1 Common Operations .......................................................................................................246
15.3.2 Timer Mode ..................................................................................................................... 248
15.3.3 Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) ............... 252
15.3.4 Event Counter Mode (When Processing Two-Phase Pulse Signal) ................................ 256
15.3.5 One-Shot Timer Mode ..................................................................................................... 261
15.3.6 Pulse Width Modulation (PWM) Mode ............................................................................. 265
15.3.7 Programmable Output Mode (Timers A1, A2, and A4) .................................................... 270
15.4 Interrupts................................................................................................................................... 274
15.5 Notes on Timer A...................................................................................................................... 275
15.5.1 Common Notes on Multiple Modes ................................................................................. 275
15.5.2 Timer A (Timer Mode) ...................................................................................................... 276
15.5.3 Timer A (Event Counter Mode) ........................................................................................ 276
15.5.4 Timer A (One-Shot Timer Mode) ..................................................................................... 276
15.5.5 Timer A (Pulse Width Modulation Mode) ......................................................................... 277
15.5.6 Timer A (Programmable Output Mode) ........................................................................... 278
16. Timer B.................................................................................................279
16.1 Introduction............................................................................................................................... 279
16.2 Registers................................................................................................................................... 282
16.2.1 Peripheral Clock Select Register (PCLKR) ..................................................................... 283
16.2.2 Clock Prescaler Reset Flag (CPSRF) ............................................................................. 283
16.2.3 Timer Bi Register (TBi) (i = 0 to 2) ................................................................................... 284
16.2.4 Timer Bi-1 Register (TBi1) (i = 0 to 2) .............................................................................. 285
16.2.5 Pulse Period/Pulse Width Measurement Mode Function Select Register 1 (PPWFS1) .. 285
16.2.6 Timer B Count Source Select Register i (TBCSi) (i = 0 to 1) ........................................... 286
16.2.7 Timer AB Division Control Register 0 (TCKDIVC0) ......................................................... 287
16.2.8 Count Start Flag (TABSR) ............................................................................................... 287
16.2.9 Timer Bi Mode Register (TBiMR) (i = 0 to 2) ................................................................... 288
16.3 Operations................................................................................................................................ 289
16.3.1 Common Operations .......................................................................................................289
16.3.2 Timer Mode ..................................................................................................................... 291
16.3.3 Event Counter Mode ........................................................................................................ 293
16.3.4 Pulse Period/Pulse Width Measurement Modes ............................................................. 296
16.4 Interrupts................................................................................................................................... 301
16.5 Notes on Timer B...................................................................................................................... 302
16.5.1 Common Notes on Multiple Modes ................................................................................. 302
16.5.2 Timer B (Timer Mode) ...................................................................................................... 302
16.5.3 Timer B (Event Counter Mode) ........................................................................................ 302
16.5.4 Timer B (Pulse Period/Pulse Width Measurement Modes) ............................................. 303

A- 9
17. Three-Phase Motor Control Timer Function.........................................304
17.1 Introduction............................................................................................................................... 304
17.2 Registers................................................................................................................................... 308
17.2.1 Timer B2 Register (TB2) .................................................................................................. 309
17.2.2 Timer Ai, Ai-1 Register (TAi, TAi1) (i = 1, 2, 4) ................................................................. 309
17.2.3 Three-Phase PWM Control Register 0 (INVC0) .............................................................. 310
17.2.4 Three-Phase PWM Control Register 1 (INVC1) .............................................................. 312
17.2.5 Three-Phase Output Buffer Register i (IDBi) (i = 0, 1) ..................................................... 314
17.2.6 Dead Time Timer (DTT) ................................................................................................... 314
17.2.7 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) ..................................... 315
17.2.8 Timer B2 Special Mode Register (TB2SC) ...................................................................... 316
17.2.9 Position-Data-Retain Function Control Register (PDRF) ................................................ 317
17.2.10 Port Function Control Register (PFCR) ........................................................................... 318
17.2.11 Three-Phase Protect Control Register (TPRC) ............................................................... 318
17.3 Operations................................................................................................................................ 319
17.3.1 Common Operations in Multiple Modes .......................................................................... 319
17.3.2 Triangular Wave Modulation Three-Phase Mode 0 ......................................................... 325
17.3.3 Triangular Wave Modulation Three-Phase Mode 1 ......................................................... 330
17.3.4 Sawtooth Wave Modulation Mode ................................................................................... 337
17.4 Interrupts................................................................................................................................... 342
17.4.1 Timer B2 Interrupt ............................................................................................................ 342
17.4.2 Timer A1, A2, and A4 Interrupts ...................................................................................... 342
17.5 Notes on Three-Phase Motor Control Timer Function.............................................................. 343
17.5.1 Timer A and Timer B ........................................................................................................ 343
17.5.2 Influence of SD ................................................................................................................ 343
18. Timer S.................................................................................................344
18.1 Introduction............................................................................................................................... 344
18.2 Registers................................................................................................................................... 348
18.2.1 Time Measurement Register j (G1TMj) (j = 0 to 7) .......................................................... 350
18.2.2 Waveform Generation Register j (G1POj) (j = 0 to 7) ...................................................... 351
18.2.3 Waveform Generation Control Register j (G1POCRj) (j = 0 to 7) .................................... 352
18.2.4 Time Measurement Control Register j (G1TMCRj) (j = 0 to 7) ........................................ 354
18.2.5 Base Timer Register (G1BT) ........................................................................................... 356
18.2.6 Base Timer Control Register 0 (G1BCR0) ....................................................................... 357
18.2.7 Base Timer Control Register 1 (G1BCR1) ....................................................................... 358
18.2.8 Time Measurement Prescaler Register j (G1TPRj) (j = 6 and 7) ..................................... 359
18.2.9 Function Enable Register (G1FE) ................................................................................... 359
18.2.10 Function Select Register (G1FS) ..................................................................................... 360
18.2.11 Base Timer Reset Register (G1BTRR) ............................................................................ 361
18.2.12 Count Source Divide Register (G1DV) ............................................................................ 361

A- 10
18.2.13 Waveform Output Master Enable Register (G1OER) ...................................................... 362
18.2.14 Timer S I/O Control Register 0 (G1IOR0) ........................................................................ 363
18.2.15 Timer S I/O Control Register 1 (G1IOR1) ........................................................................ 364
18.2.16 Interrupt Request Register (G1IR) ................................................................................... 365
18.2.17 Interrupt Enable Register 0 (G1IE0) ................................................................................ 366
18.2.18 Interrupt Enable Register 1 (G1IE1) ................................................................................ 367
18.3 Operations................................................................................................................................ 368
18.3.1 Base Timer ...................................................................................................................... 368
18.3.2 Time Measurement Function ........................................................................................... 376
18.3.3 Waveform Generation Function ....................................................................................... 380
18.3.4 I/O Port Select Function .................................................................................................. 392
18.4 Interrupts................................................................................................................................... 393
18.4.1 IC/OC Base Timer Interrupt ............................................................................................. 394
18.4.2 IC/OC Channel 0 Interrupt to IC/OC Channel 3 Interrupt ................................................ 394
18.4.3 IC/OC Interrupt 0 and IC/OC Interrupt 1 .......................................................................... 394
18.5 Notes on Timer S...................................................................................................................... 395
18.5.1 Register Access ............................................................................................................... 395
18.5.2 Changing the G1IR Register ........................................................................................... 395
18.5.3 Changing Registers ICOCiIC (i = 0, 1) ............................................................................ 397
18.5.4 Output Waveform During the Base Timer Reset with the BTS bit ................................... 397
18.5.5 OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 register ................ 397
18.5.6 Interrupt Request When Selecting Time Measurement Function .................................... 397
19. Task Monitor Timer...............................................................................398
19.1 Introduction............................................................................................................................... 398
19.2 Registers................................................................................................................................... 399
19.2.1 Task Monitor Timer Register (TMOS) .............................................................................. 399
19.2.2 Task Monitor Timer Count Start Flag (TMOSSR) ............................................................ 399
19.2.3 Task Monitor Timer Count Source Select Register (TMOSCS) ....................................... 400
19.2.4 Task Monitor Timer Protect Register (TMOSPR) ............................................................. 400
19.3 Operation.................................................................................................................................. 401
19.4 Interrupt .................................................................................................................................... 402
19.5 Notes on Task Monitor Timer.................................................................................................... 403
19.5.1 Register Settings ............................................................................................................. 403
19.5.2 Reading the Timer ........................................................................................................... 403
20. Real-Time Clock...................................................................................404
20.1 Introduction............................................................................................................................... 404
20.2 Registers................................................................................................................................... 406
20.2.1 Real-Time Clock Second Data Register (RTCSEC) ........................................................ 407
20.2.2 Real-Time Clock Minute Data Register (RTCMIN) .......................................................... 408

A- 11
20.2.3 Real-Time Clock Hour Data Register (RTCHR) .............................................................. 409
20.2.4 Real-Time Clock Day Data Register (RTCWK) ............................................................... 410
20.2.5 Real-Time Clock Control Register 1 (RTCCR1) ...............................................................411
20.2.6 Real-Time Clock Control Register 2 (RTCCR2) .............................................................. 413
20.2.7 Real-Time Clock Count Source Select Register (RTCCSR) ........................................... 415
20.2.8 Real-Time Clock Second Compare Data Register (RTCCSEC) ...................................... 416
20.2.9 Real-Time Clock Minute Compare Data Register (RTCCMIN) ........................................ 417
20.2.10 Real-Time Clock Hour Compare Data Register (RTCCHR) ............................................ 418
20.3 Operations................................................................................................................................ 419
20.3.1 Basic Operation ............................................................................................................... 419
20.3.2 Compare Mode ................................................................................................................ 422
20.4 Interrupts................................................................................................................................... 428
20.5 Notes on Real-Time Clock........................................................................................................ 429
20.5.1 Starting and Stopping the Count ...................................................................................... 429
20.5.2 Register Settings (Time Data, etc.) .................................................................................. 429
20.5.3 Register Settings (Compare Data) .................................................................................. 429
20.5.4 Time Reading Procedure in Real-Time Clock Mode ....................................................... 430
21. Serial Interface UARTi (i = 0 to 4) ........................................................431
21.1 Introduction............................................................................................................................... 431
21.2 Registers................................................................................................................................... 434
21.2.1 UART Clock Select Register (UCLKSEL0) ...................................................................... 436
21.2.2 Peripheral Clock Select Register (PCLKR) ..................................................................... 436
21.2.3 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 4) ........................................... 437
21.2.4 UARTi Bit Rate Register (UiBRG) (i = 0 to 4) .................................................................. 438
21.2.5 UARTi Transmit Buffer Register (UiTB) (i = 0 to 4) .......................................................... 438
21.2.6 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 4) ....................................... 439
21.2.7 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 4) ....................................... 441
21.2.8 UARTi Receive Buffer Register (UiRB) (i = 0 to 4) .......................................................... 442
21.2.9 UART2 Special Mode Register 4 (U2SMR4) .................................................................. 444
21.2.10 UART2 Special Mode Register 3 (U2SMR3) .................................................................. 446
21.2.11 UART2 Special Mode Register 2 (U2SMR2) .................................................................. 447
21.2.12 UART2 Special Mode Register (U2SMR) ....................................................................... 448
21.2.13 Pin Assignment Control Register (PACR) ....................................................................... 449
21.3 Operations................................................................................................................................ 450
21.3.1 Clock Synchronous Serial I/O Mode ................................................................................ 450
21.3.2 Clock Asynchronous Serial I/O (UART) Mode ................................................................. 458
21.3.3 Special Mode 1 (I2C Mode) (UART2) .............................................................................. 467
21.3.4 Special Mode 2 (UART2) ................................................................................................. 482
21.3.5 Special Mode 3 (IE Mode) (UART2) ................................................................................ 486
21.3.6 Special Mode 4 (SIM Mode) (UART2) ............................................................................. 488

A- 12
21.4 Interrupts................................................................................................................................... 493
21.4.1 Interrupt Related Registers .............................................................................................. 493
21.4.2 Reception Interrupt .......................................................................................................... 494
21.5 Notes on Serial Interface UARTi (i = 0 to 4) ............................................................................. 495
21.5.1 Common Notes on Multiple Modes ................................................................................. 495
21.5.2 Clock Synchronous Serial I/O Mode ................................................................................ 495
21.5.3 Special Mode 1 (I2C Mode) ............................................................................................. 496
21.5.4 Special Mode 4 (SIM Mode) ............................................................................................ 498
22. Multi-master I2C-bus Interface .............................................................499
22.1 Introduction............................................................................................................................... 499
22.2 Registers Descriptions.............................................................................................................. 502
22.2.1 I2C0 Data Shift Register (S00) ........................................................................................ 503
22.2.2 I2C0 Address Register i (S0Di) (i = 0 to 2) ...................................................................... 504
22.2.3 I2C0 Control Register 0 (S1D0) ....................................................................................... 505
22.2.4 I2C0 Clock Control Register (S20) .................................................................................. 507
22.2.5 I2C0 Start/Stop Condition Control Register (S2D0) ......................................................... 509
22.2.6 I2C0 Control Register 1 (S3D0) ....................................................................................... 510
22.2.7 I2C0 Control Register 2 (S4D0) ....................................................................................... 514
22.2.8 I2C0 Status Register 0 (S10) ........................................................................................... 516
22.2.9 I2C0 Status Register 1 (S11) ........................................................................................... 521
22.3 Operations................................................................................................................................ 522
22.3.1 Clock ................................................................................................................................ 522
22.3.2 Generating a Start Condition ........................................................................................... 525
22.3.3 Generating a Stop Condition ........................................................................................... 527
22.3.4 Generating a Restart Condition ....................................................................................... 528
22.3.5 Start Condition Overlap Protect ....................................................................................... 529
22.3.6 Arbitration Lost ................................................................................................................ 531
22.3.7 Detecting Start/Stop Conditions ....................................................................................... 533
22.3.8 Operation after Transmitting/Receiving a Slave Address or Data ................................... 535
22.3.9 Timeout Detection ........................................................................................................... 536
22.3.10 Data Transmit/Receive Examples ................................................................................... 537
22.4 Interrupts................................................................................................................................... 542
22.5 Notes on Multi-master I2C-bus Interface .................................................................................. 545
22.5.1 Limitation on CPU Clock .................................................................................................. 545
22.5.2 Register Access ............................................................................................................... 545
23. CAN Module........................................................................................546
23.1 CAN SFRs................................................................................................................................ 549
23.1.1 CAN0 Control Register (C0CTLR) .................................................................................. 550
23.1.2 CAN0 Clock Select Register (C0CLKR) ......................................................................... 554

A- 13
23.1.3 CAN0 Bit Configuration Register (C0BCR) .................................................................... 555
23.1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7) ................................................................ 557
23.1.5 CAN0 FIFO Received ID Compare Register n (C0FIDCR0 to C0FIDCR1) (n = 0, 1) ..... 558
23.1.6 CAN0 Mask Invalid Register (C0MKIVLR) ..................................................................... 560
23.1.7 CAN0 Mailbox Register j (C0MBj) (j = 0 to 31) ................................................................ 561
23.1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER) ....................................................... 565
23.1.9 CAN0 Message Control Register (C0MCTLj) (j = 0 to 31) .............................................. 566
23.1.10 CAN0 Receive FIFO Control Register (C0RFCR) .......................................................... 570
23.1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR) ........................................... 573
23.1.12 CAN0 Transmit FIFO Control Register (C0TFCR) ......................................................... 574
23.1.13 CAN0 Transmit FIFO Pointer Control Register (C0TFPCR) ........................................... 576
23.1.14 CAN0 Status Register (C0STR) ..................................................................................... 577
23.1.15 CAN0 Mailbox Search Mode Register (C0MSMR) ......................................................... 580
23.1.16 CAN0 Mailbox Search Status Register (C0MSSR) ........................................................ 581
23.1.17 CAN0 Channel Search Support Register (C0CSSR) ..................................................... 583
23.1.18 CAN0 Acceptance Filter Support Register (C0AFSR) .................................................... 584
23.1.19 CAN0 Error Interrupt Enable Register (C0EIER) ............................................................ 585
23.1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR) .................................................. 587
23.1.21 CAN0 Receive Error Count Register (C0RECR) ............................................................ 590
23.1.22 CAN0 Transmit Error Count Register (C0TECR) ........................................................... 591
23.1.23 CAN0 Error Code Store Register (C0ECSR) .................................................................. 592
23.1.24 CAN0 Time Stamp Register (C0TSR) ............................................................................ 594
23.1.25 CAN0 Test Control Register (C0TCR) ............................................................................ 595
23.2 Operating Mode........................................................................................................................ 598
23.2.1 CAN Reset Mode ............................................................................................................. 599
23.2.2 CAN Halt Mode ................................................................................................................ 600
23.2.3 CAN Sleep Mode ............................................................................................................. 601
23.2.4 CAN Operation Mode (Excluding Bus-Off State) ............................................................. 602
23.2.5 CAN Operation Mode (Bus-Off State) ............................................................................. 603
23.3 CAN Communication Speed Configuration............................................................................... 604
23.3.1 CAN Clock Configuration ................................................................................................. 604
23.3.2 Bit Timing Configuration .................................................................................................. 604
23.3.3 Bit rate ............................................................................................................................. 605
23.4 Mailbox and Mask Register Structure....................................................................................... 606
23.5 Acceptance Filtering and Masking Function............................................................................. 608
23.6 Reception and Transmission .....................................................................................................611
23.6.1 Reception ........................................................................................................................ 612
23.6.2 Transmission ................................................................................................................... 614
23.7 CAN Interrupt............................................................................................................................ 615