Renesas FG4-768K Series User manual

User Manual
www.renesas.com
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
November 07, 2012
R01UH0076ED0103, Rev. 1.03
V850E2/Fx4
32-bit Microcontroller
32
Preliminary Document
V850E2/FG4 V850E2/FJ4 V850E2/FK4 V850E2/FL4
µPD70F3548
µPD70F3549
µPD70F3550
µPD70F4000
µPD70F4001
µPD70F4002
µPD70F3551
µPD70F3552
µPD70F3553
µPD70F3554
µPD70F4003
µPD70F4004
µPD70F4005
µPD70F4006
µPD70F3555
µPD70F3556
µPD70F3557
µPD70F3558
µPD70F4007
µPD70F4008
µPD70F4009
µPD70F4010
µPD70F3559
µPD70F3560
µPD70F4011
µPD70F4012

R01UH0076ED0103 Rev. 1.03 2
Nov 07, 2012
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
Notice
1. All information included in this document is current as of the date this document is issued. Such
information, however, is subject to change without any prior notice. Before purchasing or using any
Renesas Electronics products listed herein, please confirm the latest product information with a
Renesas Electronics sales office. Also, please pay regular and careful attention to additional and
different information to be disclosed by Renesas Electronics such as that disclosed through our
website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other
intellectual property rights of third parties by or arising from the use of Renesas Electronics
products or technical information described in this document. No license, express, implied or
otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product,
whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to
illustrate the operation of semiconductor products and application examples. You are fully
responsible for the incorporation of these circuits, software, and information in the design of your
equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third
parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this
document for any purpose relating to military applications or use by the military, including but not
limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture,
use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this
document, but Renesas Electronics does not warrant that such information is error free. Renesas
Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors
in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades:
“Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas
Electronics product depends on the product’s quality grade, as indicated below. You must check the
quality grade of each Renesas Electronics product before using it in a particular application. You
may not use any Renesas Electronics product for any application categorized as “Specific” without
the prior written consent of Renesas Electronics. Further, you may not use any Renesas
Electronics product for any application for which it is not intended without the prior written consent
of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or
losses incurred by you or third parties arising from the use of any Renesas Electronics product for
an application categorized as “Specific” or for which the product is not intended where you have
failed to obtain the prior written consent of Renesas Electronics.

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Nov 07, 2012
Notice
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly
specified in a Renesas Electronics data sheets or data books, etc.
8. You should use the Renesas Electronics products described in this document within the range
specified by Renesas Electronics, especially with respect to the maximum rating, operating supply
voltage range, movement power voltage range, heat radiation characteristics, installation and other
product characteristics. Renesas Electronics shall have no liability for malfunctions or damages
arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products,
semiconductor products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not
subject to radiation resistance design. Please be sure to implement safety measures to guard them
against the possibility of physical injury, and injury or damage caused by fire in the event of the
failure of a Renesas Electronics product, such as safety design for hardware and software including
but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for
aging degradation or any other appropriate measures. Because the evaluation of microcomputer
software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as
the environmental compatibility of each Renesas Electronics product. Please use Renesas
Electronics products in compliance with all applicable laws and regulations that regulate the
inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Renesas Electronics assumes no liability for damages or losses occurring as a result of your
noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the
information contained in this document or Renesas Electronics products, or if you have any other
inquiries.
“Standard”: Computers; office equipment; communications equipment; test and
measurement equipment; audio and visual equipment; home electronic
appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control
systems; anti-disaster systems; anti-crime systems; safety equipment; and
medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control
systems; medical equipment or systems for life support (e.g. artificial life support
devices or systems), surgical implantations, or healthcare intervention (e.g.
excision, etc.), and any other applications or purposes that pose a direct threat to
human life.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics
Corporation and also includes its majority-owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or
for Renesas Electronics.

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Nov 07, 2012
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage
notes on the products covered by this manual, refer to the relevant sections of the manual. If the
descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the
manual differ from each other, the description in the body of the manual takes precedence.
1. Handling of unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
– The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI,
an associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled
as described under Handling of Unused Pins in the manual.
2. Processing at power-on
The state of the product is undefined at the moment when power is supplied.
– The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is
completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited.
– The reserved addresses are provided for the possible future expansion of functions. Do not
access these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock signal
has stabilized.
– When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock
signal. Moreover, when switching to a clock signal produced with an external resonator (or by an
external oscillator) while program execution is in progress, wait until the target clock signal is
stable.
5. Differences between products
Before changing from one product to another, i.e. to one with a different part number, confirm that
the change will not lead to problems.
– The characteristics of MPU/MCU in the same group but having different part numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different part numbers, implement a system-evaluation test for each of the products.

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
Table of Contents
Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Precautions in the Handling of MPU/MCU Products . . . . . . 4
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
How to use this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Purpose and target readers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Special notations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Additional documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Content of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Notation of numbers and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Functional modules descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Functional modules abbreviation convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Product specific features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Further information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.1 V850E2/Fx4 Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.1.1 V850E2/Fx4 products features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.4 Product Name Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1 V850E2/Fx4 Port Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.2 Pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.2.3 Pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2.4 Port control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3 Port Group Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.2 Port control registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.3 Port function configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.4 Data input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.5 Configuration of electrical characteristics registers. . . . . . . . . . . . . . . . . . . . 78
2.4 V850E2/Fx4 Port Group Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.4.1 Port register protection clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.4.2 Common port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.4.3 V850E2/FG4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
2.4.4 V850E2/FJ4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.4.5 V850E2/FK4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.4.6 V850E2/FL4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.4.7 Non-port input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2.4.8 Alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2.4.9 Port and pin functions in stand-by modes. . . . . . . . . . . . . . . . . . . . . . . . . . 140
2.4.10 Port and pin functions during and after reset . . . . . . . . . . . . . . . . . . . . . . . 140
2.4.11 Recommended connection of unused pins. . . . . . . . . . . . . . . . . . . . . . . . . 141
2.5 Port Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.5.1 Port filters assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.5.2 Port filters clock supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.5.3 Port filters reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.6 Port Filters Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.6.1 Analog filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.6.2 Digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.6.3 Filter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 3 CPU System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.2 Peripheral Protection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
3.3 Timing Supervision Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.4 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.5 CPU Access Bus Structures and Latencies . . . . . . . . . . . . . . . . . . . . . . 168
3.5.1 CPU Subsystem modules access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
3.5.2 PBUS modules access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.5.3 PBUS Synchronizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
3.5.4 Module wait clocks insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.6 CPU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6.1 Power and clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6.2 CPU Subsystem busses overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3.6.3 V850E2/FG4 and V850E2/FJ4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 176
3.6.4 V850E2/FK4 and V850E2/FL4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 179
3.6.5 V850E2 system manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.7 Data flash wait cycle control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.8 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.2 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.3 Boundary Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.9 Mode pins and JP0 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
3.9.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3.9.2 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.9.3 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
3.9.4 Boundary scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.10 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.10.1 CPU data address and physical program address space. . . . . . . . . . . . . . 192
3.10.2 Program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.11 V850E2/Fx4 CPU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
3.11.1 DMA address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

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3.11.2 V850E2/Fx4 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
3.11.3 Memory areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
3.12 Back-up RAM (BURAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
3.12.1 Back-up RAM protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.13 Write protected Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.13.1 Register protection clusters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.13.2 Register protection unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
3.13.3 Register protection and interrupt/emulation break . . . . . . . . . . . . . . . . . . . 211
3.13.4 V850E2/Fx4 write protected registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
3.13.5 V850E2/Fx4 Protection registers overview . . . . . . . . . . . . . . . . . . . . . . . . . 214
3.13.6 Control protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . 216
3.13.7 Clock monitors protection cluster registers details . . . . . . . . . . . . . . . . . . . 218
3.13.8 Port protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
3.13.9 Self-programming protection cluster registers details. . . . . . . . . . . . . . . . . 220
3.13.10 OCD control protection cluster registers details . . . . . . . . . . . . . . . . . . . . . 221
Chapter 4 External Memory Controller (MEMC) . . . . . . . . . . . . . . . 222
4.1 V850E2/Fx4 MEMC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
4.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.1 Operation mode, connectable memory types . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.2 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.3 Operation setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.4 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.5 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.6 Programmable wait setting functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.2.7 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
4.4 Bus cycle type setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.4.1 Multiplexed bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.5 Bus control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.5.1 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.5.2 Operation enable/operation disable setting function . . . . . . . . . . . . . . . . . . 239
4.5.3 Bus size setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
4.5.4 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.6 Wait Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.6.1 Programmable data wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
4.6.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
4.6.3 Data setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.6.4 Data hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
4.6.5 Address setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
4.6.6 Address hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
4.6.7 Idle insertion function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
4.7 Memory Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
4.7.1 Multiplexed bus mode connection example. . . . . . . . . . . . . . . . . . . . . . . . . 249
4.8 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
4.8.1 Data flow during byte access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

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Chapter 5 Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.1 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.1.1 Exception handler switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.2 V850E2/Fx4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.2.1 Memory error exceptions MEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.2.2 System error exceptions SYSERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.2.3 Code flash error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
5.3 V850E2/Fx4 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.3.1 V850E2/Fx4 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.3.2 V850E2/Fx4 FE level non-maskable interrupt sharing . . . . . . . . . . . . . . . . 301
5.3.3 V850E2/Fx4 TAPA EI level maskable interrupt sharing. . . . . . . . . . . . . . . . 303
5.3.4 V850E2/Fx4 DMA interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
5.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.4.1 Edge Detection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.4.2 External interrupts as trigger and wake-up signals. . . . . . . . . . . . . . . . . . . 306
5.5 Interrupt Controller Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
5.6 Interrupt Acknowledgment and Restoring . . . . . . . . . . . . . . . . . . . . . . . 317
5. 6. 1 FE level non-maskable interrupt FENMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5. 6. 2 FE level maskable interrupt FEINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5. 6. 3 EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
5.7 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5. 7. 1 Mask function of EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . 324
5. 7. 2 Interrupt priority level judgment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5. 7. 3 Priority mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5. 7. 4 Pending interrupt report function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5. 7. 5 In-service priority clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
5.8 Exception Handler Address Switching Function . . . . . . . . . . . . . . . . . 331
Chapter 6 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.1 V850E2/Fx4 DMA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.2 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.1 DMA controller (DMAC) function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.2 DMA trigger factor register (DTFR) function . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.3 DMA access memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.3.4 Prioritization of channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.3.5 Stand-by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.4 DMAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.4.2 DMAC setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.4.3 Enabling or disabling writing control registers. . . . . . . . . . . . . . . . . . . . . . . 344
6.5 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
6.5.1 DTRC0 – DMA transfer request control register . . . . . . . . . . . . . . . . . . . . . 345
6.5.2 DTRSn – DMA transfer request select register. . . . . . . . . . . . . . . . . . . . . . 346
6.5.3 DSAnL – DMA source address register L . . . . . . . . . . . . . . . . . . . . . . . . . . 347
6.5.4 DSAnH – DMA source address register H . . . . . . . . . . . . . . . . . . . . . . . . . 349
6.5.5 DSCn – DMA source chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . 350

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6.5.6 DNSAnL – DMA next source address register L. . . . . . . . . . . . . . . . . . . . . 351
6.5.7 DNSAnH – DMA next source address register H . . . . . . . . . . . . . . . . . . . . 352
6.5.8 DNSCn – DMA next source chip select register . . . . . . . . . . . . . . . . . . . . . 353
6.5.9 DDAnL – DMA destination address register L. . . . . . . . . . . . . . . . . . . . . . . 354
6.5.10 DDAnH – DMA destination address register H . . . . . . . . . . . . . . . . . . . . . . 356
6.5.11 DDCn – DMA destination chip select register. . . . . . . . . . . . . . . . . . . . . . . 357
6.5.12 DNDAnL – DMA next destination address register L . . . . . . . . . . . . . . . . . 358
6.5.13 DNDAnH –DMA next destination address register H . . . . . . . . . . . . . . . . . 359
6.5.14 DNDCn –DMA next destination chip select register . . . . . . . . . . . . . . . . . . 360
6.5.15 DTCn – DMA transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
6.5.16 DNTCn – DMA next transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . 362
6.5.17 DTCCn – DMA transfer count compare register . . . . . . . . . . . . . . . . . . . . . 363
6.5.18 DTCTn – DMA transfer control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
6.5.19 DTSn – DMA transfer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
6.6 DMAC Function Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.1 DMAC transfer setting flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.2 DMAC transfer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.6.3 DMAC channel priority control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.6.4 Valid DMA transfer request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
6.6.5 Next address function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
6.6.6 Aborting/resuming DMA transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
6.6.7 Error response support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.6.8 Stand-by support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.7 DTFR Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.8 DTFR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.8.1 DTFRn – DMA trigger factor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.8.2 DRQCLR – DMA request clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.8.3 DRQSTR – DMA request check register. . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Chapter 7 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
7.1 Code Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
7.1.1 Code flash memory features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
7.1.2 Code flash memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
7.1.3 Data flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
7.2 Code Flash Memory functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 387
7.2.1 Code flash memory erasure and rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . 390
7.3 Data Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.3.1 Data flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.3.2 Data flash reading and writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.4 Flash Programming with Flash Programmer . . . . . . . . . . . . . . . . . . . . . 392
7.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
7.4.2 Communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
7.4.3 Pin connection with flash programmer PG-FP5 . . . . . . . . . . . . . . . . . . . . . 394
7.4.4 Flash memory programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
7.5 Code Flash Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
7.5.1 Self-Programming enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
7.5.2 Self-Programming library functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
7.5.3 Self-Programming internal RAM occupancy . . . . . . . . . . . . . . . . . . . . . . . . 404

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
7.5.4 Secure Self-Programming (boot cluster swapping). . . . . . . . . . . . . . . . . . . 405
7.5.5 Interrupt handling during flash Self-Programming. . . . . . . . . . . . . . . . . . . . 409
7.6 Flash Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
7.6.1 OPBT0 - Flash mask option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Chapter 8 Data CRC Function A (DCRA) . . . . . . . . . . . . . . . . . . . . . . . 412
8.1 V850E2/Fx4 DCRA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
8.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
8.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
8.4.1 DCRA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
8.4.2 DCRA registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Chapter 9 Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
9.1 Clock Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
9.2 General Description of Clock Generation and Control . . . . . . . . . . . 424
9.2.1 Clock generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
9.2.2 Clock selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
9.3 Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
9.3.1 Main Oscillator (MainOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . 431
9.3.2 Sub Oscillator (SubOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . 434
9.3.3 Low Speed Internal Oscillator (Low Speed IntOsc) clock generator. . . . . . 436
9.3.4 High Speed Internal Oscillator (High Speed IntOsc) clock generator . . . . . 437
9.3.5 Phase-Locked Loop (PLL) clock generators . . . . . . . . . . . . . . . . . . . . . . . . 440
9.4 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
9.4.1 Clock domains of Always–On–Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
9.4.2 Clock domains of Isolated–Area-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
9.4.3 Clock domains of Isolated–Area-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
9.5 Clock Domain Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
9.6 Frequency Output Function (FOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
9.6.1 FOUT Clock Divider (FOUTDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
9.7 Clock Monitor A (CLMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
9.7.1 V850E2/Fx4 CLMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
9.7.2 CLMA enable and start-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
9.7.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
9.7.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
9.7.5 Clock Monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
9.8 Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.2 Clock Controller registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.3 Clock generators registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
9.8.4 Clock selector control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Chapter 10 Stand-by Controller (STBC) . . . . . . . . . . . . . . . . . . . . . . . . . . 515
10.1 V850E2/Fx4 Stand-by Controller Features . . . . . . . . . . . . . . . . . . . . . . . 515
10.2 Stand-by Controller functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
10.2.1 Stand-by Controller signal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 520