Renesas FG4-768K Series User manual

User Manual
www.renesas.com
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
November 07, 2012
R01UH0076ED0103, Rev. 1.03
V850E2/Fx4
32-bit Microcontroller
32
Preliminary Document
V850E2/FG4 V850E2/FJ4 V850E2/FK4 V850E2/FL4
µPD70F3548
µPD70F3549
µPD70F3550
µPD70F4000
µPD70F4001
µPD70F4002
µPD70F3551
µPD70F3552
µPD70F3553
µPD70F3554
µPD70F4003
µPD70F4004
µPD70F4005
µPD70F4006
µPD70F3555
µPD70F3556
µPD70F3557
µPD70F3558
µPD70F4007
µPD70F4008
µPD70F4009
µPD70F4010
µPD70F3559
µPD70F3560
µPD70F4011
µPD70F4012

R01UH0076ED0103 Rev. 1.03 2
Nov 07, 2012
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
Notice
1. All information included in this document is current as of the date this document is issued. Such
information, however, is subject to change without any prior notice. Before purchasing or using any
Renesas Electronics products listed herein, please confirm the latest product information with a
Renesas Electronics sales office. Also, please pay regular and careful attention to additional and
different information to be disclosed by Renesas Electronics such as that disclosed through our
website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other
intellectual property rights of third parties by or arising from the use of Renesas Electronics
products or technical information described in this document. No license, express, implied or
otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product,
whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to
illustrate the operation of semiconductor products and application examples. You are fully
responsible for the incorporation of these circuits, software, and information in the design of your
equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third
parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this
document for any purpose relating to military applications or use by the military, including but not
limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture,
use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this
document, but Renesas Electronics does not warrant that such information is error free. Renesas
Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors
in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades:
“Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas
Electronics product depends on the product’s quality grade, as indicated below. You must check the
quality grade of each Renesas Electronics product before using it in a particular application. You
may not use any Renesas Electronics product for any application categorized as “Specific” without
the prior written consent of Renesas Electronics. Further, you may not use any Renesas
Electronics product for any application for which it is not intended without the prior written consent
of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or
losses incurred by you or third parties arising from the use of any Renesas Electronics product for
an application categorized as “Specific” or for which the product is not intended where you have
failed to obtain the prior written consent of Renesas Electronics.

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Nov 07, 2012
Notice
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly
specified in a Renesas Electronics data sheets or data books, etc.
8. You should use the Renesas Electronics products described in this document within the range
specified by Renesas Electronics, especially with respect to the maximum rating, operating supply
voltage range, movement power voltage range, heat radiation characteristics, installation and other
product characteristics. Renesas Electronics shall have no liability for malfunctions or damages
arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products,
semiconductor products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not
subject to radiation resistance design. Please be sure to implement safety measures to guard them
against the possibility of physical injury, and injury or damage caused by fire in the event of the
failure of a Renesas Electronics product, such as safety design for hardware and software including
but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for
aging degradation or any other appropriate measures. Because the evaluation of microcomputer
software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as
the environmental compatibility of each Renesas Electronics product. Please use Renesas
Electronics products in compliance with all applicable laws and regulations that regulate the
inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Renesas Electronics assumes no liability for damages or losses occurring as a result of your
noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the
information contained in this document or Renesas Electronics products, or if you have any other
inquiries.
“Standard”: Computers; office equipment; communications equipment; test and
measurement equipment; audio and visual equipment; home electronic
appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control
systems; anti-disaster systems; anti-crime systems; safety equipment; and
medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control
systems; medical equipment or systems for life support (e.g. artificial life support
devices or systems), surgical implantations, or healthcare intervention (e.g.
excision, etc.), and any other applications or purposes that pose a direct threat to
human life.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics
Corporation and also includes its majority-owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or
for Renesas Electronics.

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Nov 07, 2012
Under development: Preliminary document. Specifications in this document are tentative and subject to change.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage
notes on the products covered by this manual, refer to the relevant sections of the manual. If the
descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the
manual differ from each other, the description in the body of the manual takes precedence.
1. Handling of unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
– The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI,
an associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled
as described under Handling of Unused Pins in the manual.
2. Processing at power-on
The state of the product is undefined at the moment when power is supplied.
– The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is
completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited.
– The reserved addresses are provided for the possible future expansion of functions. Do not
access these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock signal
has stabilized.
– When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock
signal. Moreover, when switching to a clock signal produced with an external resonator (or by an
external oscillator) while program execution is in progress, wait until the target clock signal is
stable.
5. Differences between products
Before changing from one product to another, i.e. to one with a different part number, confirm that
the change will not lead to problems.
– The characteristics of MPU/MCU in the same group but having different part numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different part numbers, implement a system-evaluation test for each of the products.

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
Table of Contents
Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Precautions in the Handling of MPU/MCU Products . . . . . . 4
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
How to use this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Purpose and target readers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Special notations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Additional documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Content of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Notation of numbers and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Functional modules descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Functional modules abbreviation convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Product specific features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Further information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.1 V850E2/Fx4 Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.1.1 V850E2/Fx4 products features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.4 Product Name Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1 V850E2/Fx4 Port Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.2 Pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.2.3 Pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2.4 Port control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3 Port Group Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.2 Port control registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.3 Port function configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.4 Data input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.5 Configuration of electrical characteristics registers. . . . . . . . . . . . . . . . . . . . 78
2.4 V850E2/Fx4 Port Group Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.4.1 Port register protection clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.4.2 Common port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.4.3 V850E2/FG4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
2.4.4 V850E2/FJ4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.4.5 V850E2/FK4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.4.6 V850E2/FL4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.4.7 Non-port input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2.4.8 Alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2.4.9 Port and pin functions in stand-by modes. . . . . . . . . . . . . . . . . . . . . . . . . . 140
2.4.10 Port and pin functions during and after reset . . . . . . . . . . . . . . . . . . . . . . . 140
2.4.11 Recommended connection of unused pins. . . . . . . . . . . . . . . . . . . . . . . . . 141
2.5 Port Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.5.1 Port filters assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.5.2 Port filters clock supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.5.3 Port filters reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.6 Port Filters Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.6.1 Analog filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.6.2 Digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.6.3 Filter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 3 CPU System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.2 Peripheral Protection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
3.3 Timing Supervision Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.4 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.5 CPU Access Bus Structures and Latencies . . . . . . . . . . . . . . . . . . . . . . 168
3.5.1 CPU Subsystem modules access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
3.5.2 PBUS modules access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.5.3 PBUS Synchronizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
3.5.4 Module wait clocks insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.6 CPU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6.1 Power and clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6.2 CPU Subsystem busses overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3.6.3 V850E2/FG4 and V850E2/FJ4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 176
3.6.4 V850E2/FK4 and V850E2/FL4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 179
3.6.5 V850E2 system manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.7 Data flash wait cycle control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.8 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.2 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.8.3 Boundary Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.9 Mode pins and JP0 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
3.9.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3.9.2 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.9.3 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
3.9.4 Boundary scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.10 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.10.1 CPU data address and physical program address space. . . . . . . . . . . . . . 192
3.10.2 Program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
3.11 V850E2/Fx4 CPU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
3.11.1 DMA address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

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3.11.2 V850E2/Fx4 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
3.11.3 Memory areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
3.12 Back-up RAM (BURAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
3.12.1 Back-up RAM protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
3.13 Write protected Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.13.1 Register protection clusters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.13.2 Register protection unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
3.13.3 Register protection and interrupt/emulation break . . . . . . . . . . . . . . . . . . . 211
3.13.4 V850E2/Fx4 write protected registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
3.13.5 V850E2/Fx4 Protection registers overview . . . . . . . . . . . . . . . . . . . . . . . . . 214
3.13.6 Control protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . 216
3.13.7 Clock monitors protection cluster registers details . . . . . . . . . . . . . . . . . . . 218
3.13.8 Port protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
3.13.9 Self-programming protection cluster registers details. . . . . . . . . . . . . . . . . 220
3.13.10 OCD control protection cluster registers details . . . . . . . . . . . . . . . . . . . . . 221
Chapter 4 External Memory Controller (MEMC) . . . . . . . . . . . . . . . 222
4.1 V850E2/Fx4 MEMC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
4.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.1 Operation mode, connectable memory types . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.2 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.3 Operation setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.4 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.5 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.2.6 Programmable wait setting functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.2.7 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
4.4 Bus cycle type setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.4.1 Multiplexed bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
4.5 Bus control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.5.1 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.5.2 Operation enable/operation disable setting function . . . . . . . . . . . . . . . . . . 239
4.5.3 Bus size setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
4.5.4 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.6 Wait Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.6.1 Programmable data wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
4.6.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
4.6.3 Data setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.6.4 Data hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
4.6.5 Address setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
4.6.6 Address hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
4.6.7 Idle insertion function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
4.7 Memory Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
4.7.1 Multiplexed bus mode connection example. . . . . . . . . . . . . . . . . . . . . . . . . 249
4.8 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
4.8.1 Data flow during byte access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

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Chapter 5 Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.1 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.1.1 Exception handler switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.2 V850E2/Fx4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.2.1 Memory error exceptions MEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.2.2 System error exceptions SYSERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.2.3 Code flash error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
5.3 V850E2/Fx4 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.3.1 V850E2/Fx4 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.3.2 V850E2/Fx4 FE level non-maskable interrupt sharing . . . . . . . . . . . . . . . . 301
5.3.3 V850E2/Fx4 TAPA EI level maskable interrupt sharing. . . . . . . . . . . . . . . . 303
5.3.4 V850E2/Fx4 DMA interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
5.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.4.1 Edge Detection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.4.2 External interrupts as trigger and wake-up signals. . . . . . . . . . . . . . . . . . . 306
5.5 Interrupt Controller Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
5.6 Interrupt Acknowledgment and Restoring . . . . . . . . . . . . . . . . . . . . . . . 317
5. 6. 1 FE level non-maskable interrupt FENMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
5. 6. 2 FE level maskable interrupt FEINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5. 6. 3 EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
5.7 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5. 7. 1 Mask function of EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . 324
5. 7. 2 Interrupt priority level judgment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
5. 7. 3 Priority mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5. 7. 4 Pending interrupt report function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
5. 7. 5 In-service priority clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
5.8 Exception Handler Address Switching Function . . . . . . . . . . . . . . . . . 331
Chapter 6 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.1 V850E2/Fx4 DMA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.2 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.1 DMA controller (DMAC) function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.2 DMA trigger factor register (DTFR) function . . . . . . . . . . . . . . . . . . . . . . . . 335
6.3.3 DMA access memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.3.4 Prioritization of channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.3.5 Stand-by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.4 DMAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.4.2 DMAC setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.4.3 Enabling or disabling writing control registers. . . . . . . . . . . . . . . . . . . . . . . 344
6.5 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
6.5.1 DTRC0 – DMA transfer request control register . . . . . . . . . . . . . . . . . . . . . 345
6.5.2 DTRSn – DMA transfer request select register. . . . . . . . . . . . . . . . . . . . . . 346
6.5.3 DSAnL – DMA source address register L . . . . . . . . . . . . . . . . . . . . . . . . . . 347
6.5.4 DSAnH – DMA source address register H . . . . . . . . . . . . . . . . . . . . . . . . . 349
6.5.5 DSCn – DMA source chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . 350

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6.5.6 DNSAnL – DMA next source address register L. . . . . . . . . . . . . . . . . . . . . 351
6.5.7 DNSAnH – DMA next source address register H . . . . . . . . . . . . . . . . . . . . 352
6.5.8 DNSCn – DMA next source chip select register . . . . . . . . . . . . . . . . . . . . . 353
6.5.9 DDAnL – DMA destination address register L. . . . . . . . . . . . . . . . . . . . . . . 354
6.5.10 DDAnH – DMA destination address register H . . . . . . . . . . . . . . . . . . . . . . 356
6.5.11 DDCn – DMA destination chip select register. . . . . . . . . . . . . . . . . . . . . . . 357
6.5.12 DNDAnL – DMA next destination address register L . . . . . . . . . . . . . . . . . 358
6.5.13 DNDAnH –DMA next destination address register H . . . . . . . . . . . . . . . . . 359
6.5.14 DNDCn –DMA next destination chip select register . . . . . . . . . . . . . . . . . . 360
6.5.15 DTCn – DMA transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
6.5.16 DNTCn – DMA next transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . 362
6.5.17 DTCCn – DMA transfer count compare register . . . . . . . . . . . . . . . . . . . . . 363
6.5.18 DTCTn – DMA transfer control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
6.5.19 DTSn – DMA transfer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
6.6 DMAC Function Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.1 DMAC transfer setting flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.2 DMAC transfer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.6.3 DMAC channel priority control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.6.4 Valid DMA transfer request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
6.6.5 Next address function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
6.6.6 Aborting/resuming DMA transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
6.6.7 Error response support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.6.8 Stand-by support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.7 DTFR Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.8 DTFR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.8.1 DTFRn – DMA trigger factor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.8.2 DRQCLR – DMA request clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.8.3 DRQSTR – DMA request check register. . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Chapter 7 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
7.1 Code Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
7.1.1 Code flash memory features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
7.1.2 Code flash memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
7.1.3 Data flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
7.2 Code Flash Memory functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 387
7.2.1 Code flash memory erasure and rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . 390
7.3 Data Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.3.1 Data flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.3.2 Data flash reading and writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
7.4 Flash Programming with Flash Programmer . . . . . . . . . . . . . . . . . . . . . 392
7.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
7.4.2 Communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
7.4.3 Pin connection with flash programmer PG-FP5 . . . . . . . . . . . . . . . . . . . . . 394
7.4.4 Flash memory programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
7.5 Code Flash Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
7.5.1 Self-Programming enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
7.5.2 Self-Programming library functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
7.5.3 Self-Programming internal RAM occupancy . . . . . . . . . . . . . . . . . . . . . . . . 404

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7.5.4 Secure Self-Programming (boot cluster swapping). . . . . . . . . . . . . . . . . . . 405
7.5.5 Interrupt handling during flash Self-Programming. . . . . . . . . . . . . . . . . . . . 409
7.6 Flash Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
7.6.1 OPBT0 - Flash mask option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Chapter 8 Data CRC Function A (DCRA) . . . . . . . . . . . . . . . . . . . . . . . 412
8.1 V850E2/Fx4 DCRA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
8.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
8.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
8.4.1 DCRA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
8.4.2 DCRA registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Chapter 9 Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
9.1 Clock Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
9.2 General Description of Clock Generation and Control . . . . . . . . . . . 424
9.2.1 Clock generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
9.2.2 Clock selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
9.3 Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
9.3.1 Main Oscillator (MainOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . 431
9.3.2 Sub Oscillator (SubOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . 434
9.3.3 Low Speed Internal Oscillator (Low Speed IntOsc) clock generator. . . . . . 436
9.3.4 High Speed Internal Oscillator (High Speed IntOsc) clock generator . . . . . 437
9.3.5 Phase-Locked Loop (PLL) clock generators . . . . . . . . . . . . . . . . . . . . . . . . 440
9.4 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
9.4.1 Clock domains of Always–On–Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
9.4.2 Clock domains of Isolated–Area-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
9.4.3 Clock domains of Isolated–Area-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
9.5 Clock Domain Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
9.6 Frequency Output Function (FOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
9.6.1 FOUT Clock Divider (FOUTDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
9.7 Clock Monitor A (CLMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
9.7.1 V850E2/Fx4 CLMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
9.7.2 CLMA enable and start-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
9.7.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
9.7.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
9.7.5 Clock Monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
9.8 Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.2 Clock Controller registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.8.3 Clock generators registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
9.8.4 Clock selector control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Chapter 10 Stand-by Controller (STBC) . . . . . . . . . . . . . . . . . . . . . . . . . . 515
10.1 V850E2/Fx4 Stand-by Controller Features . . . . . . . . . . . . . . . . . . . . . . . 515
10.2 Stand-by Controller functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
10.2.1 Stand-by Controller signal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

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10.2.2 Stand-by modes control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
10.2.3 Stand-by modes overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
10.2.4 Clock generators in stand-by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
10.2.5 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
10.2.6 I/O buffer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
10.2.7 Mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
10.3 Stand-by mode entry and exit example flows . . . . . . . . . . . . . . . . . . . . 535
10.3.1 STOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
10.3.2 RUN mode (Isolated-Area-1 STOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
10.3.3 DEEPSTOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
10.3.4 RUN mode (Isolated-Area-1 DEEPSTOP) . . . . . . . . . . . . . . . . . . . . . . . . . 547
10.3.5 Precaution: Clock generators and early wake-up . . . . . . . . . . . . . . . . . . . . 551
10.3.6 Application hint: Handling of wake-up events during stand-by mode preparation
553
10.4 Stand-by Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
10.4.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
10.4.2 Stand-by Controller registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
10.4.3 Stand-by Controller control registers details . . . . . . . . . . . . . . . . . . . . . . . . 558
10.4.4 Wake-up factor controller registers details . . . . . . . . . . . . . . . . . . . . . . . . . 564
10.4.5 Oscillator wake-up mask registers details. . . . . . . . . . . . . . . . . . . . . . . . . . 567
Chapter 11 Code Protection and Security . . . . . . . . . . . . . . . . . . . . . . . 568
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
11.2 Flash Programmer and Self-Programming Protection . . . . . . . . . . . . 569
11.3 On-Chip Debug Interface Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
11.3.1 On-Chip Debug enable flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
11.3.2 On-Chip Debug ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
11.3.3 On-Chip Debug protection levels summary. . . . . . . . . . . . . . . . . . . . . . . . . 571
11.3.4 On-Chip Debug control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Chapter 12 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
12.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
12.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
12.2.1 Reset flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
12.2.2 Power-On Clear reset (POCRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
12.2.3 Low-Voltage Indicator (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
12.2.4 Very-Low-Voltage Indicator (VLVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
12.2.5 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
12.2.6 Watchdog Timers reset (WDTAnRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
12.2.7 Software reset (SWRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
12.2.8 Clock Monitors reset (CLMAnRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
12.2.9 Debugger reset (DBRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
12.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
12.3.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
12.3.2 Reset Controller registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
12.3.3 Reset Controller general control registers details . . . . . . . . . . . . . . . . . . . . 589
12.3.4 Software reset control registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
12.3.5 Low-Voltage Indicator reset control registers . . . . . . . . . . . . . . . . . . . . . . . 592

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12.3.6 Very-Low-Voltage flag control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Chapter 13 OS Timer (OSTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
13.1 V850E2/Fx4 OSTM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
13.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
13.3.1 Count clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
13.3.2 Interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
13.3.3 Starting and stopping the timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
13.3.4 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
13.3.5 Free-run compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
13.4 OS Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
13.4.1 OS Timer registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
13.4.2 OS Timer registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Chapter 14 Window Watchdog Timer A (WDTA) . . . . . . . . . . . . . . . . 611
14.1 V850E2/Fx4 WDTA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
14.2 WDTA Start-up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.2.1 V850E2/Fx4 WDTAn start modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
14.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.4.1 WDTA after reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.4.2 WDTA trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
14.4.3 Error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
14.4.4 75% interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
14.4.5 Window function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
14.5 Application hint: Evaluation of the Watchdog status . . . . . . . . . . . . . 626
14.6 WDTA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
14.6.1 WDTA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
14.6.2 WDTA registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Chapter 15 Timer Array Unit A (TAUA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
15.1 V850E2/Fx4 TAUA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
15.2 TAUA Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
15.2.1 TAUA0 input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
15.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
15.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
15.5 General Operating Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
15.6 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
15.7 Concepts of Synchronous Channel Operation . . . . . . . . . . . . . . . . . . . 652
15.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
15.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . . 654
15.8 Simultaneous Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
15.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
15.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
15.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . 658

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15.8.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
15.9 Channel Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
15.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . . 669
15.9.2 Channel output modes controlled independently by TAUAn signals . . . . . . 670
15.9.3 Channel output modes controlled synchronously by TAUAn signals. . . . . . 672
15.10 Start Timing of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
15.10.1 Interval Timer Mode, Judge Mode, Capture Mode, Up Down Count Mode. 677
15.10.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
15.10.3 All other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
15.11 TAUAnTTOUTm Output and INTTAUAnIm Generation when Counter
Starts or Restarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
15.12 Interrupt Generation upon Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
15.12.1 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
15.12.2 Capture and One Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
15.12.3 Count Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
15.12.4 Capture and Gate Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
15.13 TAUAnTTINm Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
15.14 Assigning DMA Window Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
15.15 Independent Channel Operation Functions . . . . . . . . . . . . . . . . . . . . . . 687
15.16 Independent Channel Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . . 687
15.16.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
15.16.2 TAUAnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . 695
15.16.3 Delay Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
15.16.4 One-Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
15.17 Independent Channel Signal Measurement Functions . . . . . . . . . . . 711
15.17.1 TAUAnTTINm Input Pulse Interval Measurement Function. . . . . . . . . . . . . 712
15.17.2 TAUAnTTINm Input Signal Width Measurement Function . . . . . . . . . . . . . 720
15.17.3 Overflow Interrupt Output Function
(During TAUAnTTINm Width Measurement). . . . . . . . . . . . . . . . . . . . . . . . 728
15.17.4 TAUAnTTINm Input Period Count Detection Function. . . . . . . . . . . . . . . . . 733
15.17.5 Overflow Interrupt Output Function
(During TAUAnTTINm Input Period Count Detection) . . . . . . . . . . . . . . . . . 739
15.17.6 TAUAnTTINm Input Pulse Interval Judgment Function. . . . . . . . . . . . . . . . 744
15.17.7 TAUAnTTINm Input Signal Width Judgment Function. . . . . . . . . . . . . . . . . 749
15.18 Independent Channel Real-Time Functions . . . . . . . . . . . . . . . . . . . . . . 754
15.18.1 Real-Time Output Function Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
15.18.2 Real-Time Output Function Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
15.19 Independent Channel Simultaneous Rewrite Functions . . . . . . . . . . 769
15.19.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . . 770
15.19.2 Simultaneous Rewrite Trigger Generation Function Type 2 . . . . . . . . . . . . 776
15.20 Independent Channel One-Phase PWM Function . . . . . . . . . . . . . . . . 782
15.20.1 One-Phase PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
15.21 Other Independent Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 790
15.21.1 External Event Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
15.21.2 Clock Divide Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
15.21.3 TAUAnTTINm Input Position Detection Function. . . . . . . . . . . . . . . . . . . . . 805
15.22 Synchronous Channel Operation Functions . . . . . . . . . . . . . . . . . . . . . 811
15.23 Synchronous PWM Signal Functions Triggered at Regular Intervals

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15.23.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
15.23.2 Trigger Start PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
15.23.3 Delay Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
15.23.4 AD Conversion Trigger Output Function Type 1 . . . . . . . . . . . . . . . . . . . . . 850
15.24 Synchronous PWM Signal Functions Triggered by an External Signal
852
15.24.1 One-Shot Pulse Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
15.24.2 Offset Trigger Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
15.25 Synchronous Triangle PWM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 875
15.25.1 Triangle PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
15.25.2 Triangle PWM Output Function with Dead Time . . . . . . . . . . . . . . . . . . . . . 887
15.25.3 AD Conversion Trigger Output Function Type 2 . . . . . . . . . . . . . . . . . . . . . 910
15.26 Synchronous Real-Time Output Functions . . . . . . . . . . . . . . . . . . . . . . 912
15.26.1 Synchronous Real-Time Output Function Type 1 . . . . . . . . . . . . . . . . . . . . 913
15.26.2 Synchronous Real-Time Output Function Type 2 . . . . . . . . . . . . . . . . . . . . 924
15.26.3 Synchronous Real-Time Output Function Type 3 . . . . . . . . . . . . . . . . . . . . 935
15.27 Synchronous Non-Complementary and Complementary Functions .
946
15.27.1 Non-Complementary Modulation Output Function Type 1 . . . . . . . . . . . . . 947
15.27.2 Non-Complementary Modulation Output Function Type 2 . . . . . . . . . . . . . 960
15.27.3 Complementary Modulation Output Function . . . . . . . . . . . . . . . . . . . . . . . 974
15.28 Other Synchronous Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . 992
15.28.1 Interrupt Culling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
15.29 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
15.29.1 TAUAn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
15.29.2 TAUAn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
15.29.3 TAUAn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
15.29.4 TAUAn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
15.29.5 TAUAn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1022
15.29.6 TAUAn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1023
15.29.7 TAUAn DMA window registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
15.29.8 TAUAn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Chapter 16 Timer Array Unit B (TAUB) . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
16.1 V850E2/Fx4 TAUB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
16.2 TAUB Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
16.2.1 TAUB1TTIN[7:0] input selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
16.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
16.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
16.5 General Operating Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
16.6 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
16.7 Concepts of Synchronous Channel Operation . . . . . . . . . . . . . . . . . . 1043
16.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
16.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1045
16.8 Simultaneous Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
16.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046

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16.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
16.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1049
16.8.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
16.9 Channel Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
16.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1058
16.9.2 Channel output modes controlled independently by TAUBn signals. . . . . 1059
16.9.3 Channel output modes controlled synchronously by TAUBn signals. . . . . 1060
16.10 Start Timing of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
16.10.1 Interval Timer Mode, Judge Mode, Capture Mode, Up Down Count Mode 1063
16.10.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
16.10.3 All other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
16.11 TAUBnTTOUTm toggle and INTTAUBnIm Generation when Counter
start is triggered (MD0-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
16.12 TAUBnTTINm Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
16.13 Independent Channel Operation Functions . . . . . . . . . . . . . . . . . . . . . 1068
16.14 Independent Channel Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . 1068
16.14.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
16.14.2 TAUBnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . 1077
16.14.3 One-Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
16.15 Independent Channel Signal Measurement Functions . . . . . . . . . . 1088
16.15.1 TAUBnTTINm Input Pulse Interval Measurement Function. . . . . . . . . . . . 1089
16.15.2 TAUBnTTINm Input Signal Width Measurement Function . . . . . . . . . . . . 1097
16.15.3 Overflow Interrupt Output Function
(During TAUBnTTINm Width Measurement). . . . . . . . . . . . . . . . . . . . . . . 1105
16.15.4 TAUBnTTINm Input Period Count Detection Function . . . . . . . . . . . . . . . 1110
16.15.5 Overflow Interrupt Output Function
(During TAUBnTTINm Input Period Count Detection). . . . . . . . . . . . . . . . 1116
16.15.6 TAUBnTTINm Input Pulse Interval Judgment Function. . . . . . . . . . . . . . . 1121
16.15.7 TAUBnTTINm Input Signal Width Judgment Function. . . . . . . . . . . . . . . . 1126
16.16 Independent Channel Simultaneous Rewrite Functions . . . . . . . . . 1131
16.16.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . 1132
16.17 Other Independent Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . 1138
16.17.1 External Event Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
16.17.2 Clock Divide Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
16.17.3 TAUBnTTINm Input Position Detection Function. . . . . . . . . . . . . . . . . . . . 1153
16.18 Synchronous Channel Operation Functions . . . . . . . . . . . . . . . . . . . . 1159
16.19 Synchronous PWM Signal Functions Triggered at Regular Intervals
1159
16.19.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
16.19.2 Delay Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
16.19.3 AD Conversion Trigger Output Function Type 1 . . . . . . . . . . . . . . . . . . . . 1187
16.20 Synchronous PWM Signal Functions Triggered by an External Signal
1189
16.20.1 One-Shot Pulse Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
16.21 Synchronous Triangle PWM Functions . . . . . . . . . . . . . . . . . . . . . . . . . 1202
16.21.1 Triangle PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
16.21.2 Triangle PWM Output Function with Dead Time . . . . . . . . . . . . . . . . . . . . 1214
16.21.3 AD Conversion Trigger Output Function Type 2 . . . . . . . . . . . . . . . . . . . . 1237

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16.22 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
16.22.1 TAUBn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
16.22.2 TAUBn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
16.22.3 TAUBn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
16.22.4 TAUBn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
16.22.5 TAUBn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1255
16.22.6 TAUBn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1256
16.22.7 TAUBn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
Chapter 17 Timer Array Unit C (TAUC) . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
17.1 V850E2/Fx4 TAUC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
17.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
17.2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
17.4 General Operating Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
17.5 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
17.6 Concepts of Synchronous Channel Operation . . . . . . . . . . . . . . . . . . 1271
17.6.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
17.6.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1273
17.7 Simultaneous Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
17.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
17.7.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
17.7.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1276
17.7.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
17.8 Channel Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
17.8.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1283
17.8.2 Channel output modes controlled independently by TAUCn signals. . . . . 1284
17.8.3 Channel output modes controlled synchronously by TAUCn signals . . . . 1285
17.9 Start Timing of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
17.9.1 Interval Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
17.9.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
17.10 TAUCnTTOUTm toggle and INTTAUCnIm Generation when Counter
start is triggered (MD0-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
17.11 Independent Channel Operation Functions . . . . . . . . . . . . . . . . . . . . . 1289
17.12 Independent Channel Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . 1289
17.12.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
17.13 Independent Channel Simultaneous Rewrite Functions . . . . . . . . . 1298
17.13.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . 1299
17.14 Synchronous PWM Signal Functions Triggered at Regular Intervals
1305
17.14.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
17.15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
17.15.1 TAUCn registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
17.15.2 TAUCn prescaler registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
17.15.3 TAUCn control registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320
17.15.4 TAUCn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
17.15.5 TAUCn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1326

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17.15.6 TAUCn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1327
17.15.7 TAUCn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Chapter 18 Timer Array Unit J (TAUJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
18.1 V850E2/Fx4 TAUJ Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
18.2 TAUJ Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335
18.2.1 TAUJ0/TAUJ1 input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335
18.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
18.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
18.5 General Operating Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
18.6 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
18.7 Concepts of Synchronous Channel Operation . . . . . . . . . . . . . . . . . . 1348
18.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
18.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1350
18.8 Simultaneous Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
18.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
18.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
18.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1353
18.8.4 Simultaneous rewrite procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
18.9 Channel Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
18.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1358
18.9.2 Channel output modes controlled independently by TAUJn signals . . . . . 1359
18.9.3 Channel output modes controlled synchronously by TAUJn signals. . . . . 1360
18.10 Start Timing of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
18.10.1 Interval Timer Mode, Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
18.10.2 Other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
18.11 TAUJnTTOUTm Output and INTTAUJnIm Generation when Counter
Starts or Restarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
18.12 Interrupt Generation upon Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
18.12.1 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
18.12.2 Capture and One Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
18.12.3 Count Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
18.12.4 Capture and Gate Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
18.13 TAUJnTTINm Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
18.14 Independent Channel Operation Functions . . . . . . . . . . . . . . . . . . . . . 1370
18.15 Independent Channel Interrupt Functions . . . . . . . . . . . . . . . . . . . . . . 1370
18.15.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
18.15.2 TAUJnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . 1378
18.16 Independent Channel Signal Measurement Fuctions . . . . . . . . . . . 1384
18.16.1 TAUJnTTINm Input Pulse Interval Measurement Function . . . . . . . . . . . . 1385
18.16.2 TAUJnTTINm Input Signal Width Measurement Function. . . . . . . . . . . . . 1392
18.16.3 Overflow Interrupt Output Function
(During TAUJnTTINm Width Measurement) . . . . . . . . . . . . . . . . . . . . . . . 1399
18.16.4 TAUJnTTINm Input Period Count Detection Function. . . . . . . . . . . . . . . . 1403
18.16.5 Overflow Interrupt Output Function
(During TAUJnTTINm Input Period Count Detection) . . . . . . . . . . . . . . . . 1409
18.17 Other Independent Channel Functions . . . . . . . . . . . . . . . . . . . . . . . . . 1414

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18.17.1 TAUJnTTINm Input Position Detection Function . . . . . . . . . . . . . . . . . . . . 1415
18.18 Synchronous PWM Signal Functions Triggered at Regular Intervals
1421
18.18.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
18.19 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
18.19.1 TAUJn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
18.19.2 TAUJn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
18.19.3 TAUJn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
18.19.4 TAUJn output registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
18.19.5 TAUJn simultaneous rewrite register details . . . . . . . . . . . . . . . . . . . . . . . 1450
18.19.6 TAUJn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
Chapter 19 Real-Time Clock (RTCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
19.1 V850E2/Fx4 RTCA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
19.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
19.3.1 Operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
19.3.2 Clock counter format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
19.3.3 Fixed interval interrupt function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
19.3.4 Alarm interrupt function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
19.3.5 Clock error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
19.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
19.4.1 RTCA registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
19.4.2 RTCA control registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
19.4.3 RTCA sub-counter registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471
19.4.4 RTCA clock counter and buffer registers details . . . . . . . . . . . . . . . . . . . . 1475
19.4.5 RTCA special counter and buffer registers details . . . . . . . . . . . . . . . . . . 1490
19.4.6 RTCA alarm setting registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
19.4.7 RTCA emulation register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
19.5 Procedures for Setup, Writing and Reading . . . . . . . . . . . . . . . . . . . . 1498
19.5.1 Initial setting of the RTCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
19.5.2 Updating clock counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
19.5.3 Reading clock counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
19.5.4 Reading RTCAnSRBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
19.5.5 Writing to RTCAnSUBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
19.5.6 Writing to RTCAnSCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
19.6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
19.6.1 Timing of RTCA counter start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
19.6.2 Timing of RTCA while counter is enabled . . . . . . . . . . . . . . . . . . . . . . . . . 1508
19.6.3 Timing of sub-counter buffer read while counter is enabled . . . . . . . . . . . 1509
Chapter 20 Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
20.1 Basic structure of motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
20.2 V850E2/Fx4 Timer Motor Control Function (TAPA) Features . . . . 1512
20.3 TAPA0 Hi-Z control input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
20.4 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
20.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
20.4.2 Peak and valley interrupts - Peak and valley of timer counter. . . . . . . . . . 1518

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
20.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
20.5.1 Registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
20.5.2 Registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
20.6 Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
20.6.1 Asynchronous Hi-Z control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
20.6.2 INT signal output selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
20.6.3 A/D conversion trigger selection function . . . . . . . . . . . . . . . . . . . . . . . . . 1533
20.7 Three-Phase PWM Output with Dead Time . . . . . . . . . . . . . . . . . . . . . . 1537
20.7.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
20.7.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
20.7.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
20.7.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
20.7.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1551
20.7.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
20.8 High-accuracy Triangle PWM Output with Dead Time . . . . . . . . . . . 1564
20.8.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
20.8.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
20.8.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568
20.8.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
20.8.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1583
20.8.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
20.9 Delay Pulse Output with Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
20.9.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
20.9.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
20.9.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
20.9.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
20.9.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1615
20.9.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
Chapter 21 Encoder Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
21.1 Basic structure of Encoder Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
21.2 V850E2/Fx4 Encoder Timer (ENCA) Features . . . . . . . . . . . . . . . . . . . 1630
21.3 ENCA Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
21.3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
21.3.2 Preliminary knowledge for understanding basic specifications. . . . . . . . . 1635
21.4 ENCA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
21.5 ENCA Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
21.5.1 Timer counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
21.5.2 Up/down control of timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
21.5.3 Timer counter clear control by encoder input . . . . . . . . . . . . . . . . . . . . . . 1653
21.5.4 Functions of ENCAnCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
21.5.5 Functions of ENCAnCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
21.6 ENCA Setting Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
21.6.1 Encoder timer setting procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
21.7 A/D Trigger Encoder Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
21.7.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
21.7.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
21.7.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.
21.7.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
21.7.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1664
21.7.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
21.8 Synchronized Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
21.8.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
21.8.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
21.8.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
21.8.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
21.8.5 Setting up operation functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
21.8.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
21.9 Trigger Pulse Width Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
21.9.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
21.9.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
21.9.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
21.9.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
21.9.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1681
21.9.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
Chapter 22 PWM Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
22.1 PWM Diagnostic functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
22.1.1 Basic concept and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
22.1.2 PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
22.1.3 Channel-to-channel delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
22.1.4 A/D Converter trigger delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
22.1.5 Synchronous PWM groups multiplexer and A/D Converter control. . . . . . 1694
22.1.6 A/D Converter conversion result memory transfer . . . . . . . . . . . . . . . . . . 1696
22.1.7 Diagnostic value evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
22.2 PWM Delay (DLYA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
22.2.1 DLYA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
22.2.2 PWM Delay (DLYA) bypass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
22.2.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
22.2.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
22.2.5 Procedure for Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
22.2.6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
22.3 PWM Diagnostic timing and trigger generation (PMCA) . . . . . . . . . 1711
22.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
22.3.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
22.3.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
22.3.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
22.3.5 Procedures for Setup, Writing and Reading . . . . . . . . . . . . . . . . . . . . . . . 1727
Chapter 23 Asynchronous Serial Interface E (URTE) . . . . . . . . . 1728
23.1 V850E2/Fx4 URTEn Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
23.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
23.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
23.4 URTE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
23.5 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
23.5.1 Transmission interrupt request INTUAEnTIT. . . . . . . . . . . . . . . . . . . . . . . 1751