Renesas RAA604S00 Installation and operating instructions

APPLICATION NOTE
R01AN4426EJ0100 Rev.1.00 Page 1 of 13
Dec 21, 2018
RAA604S00
Guidelines for two-layer board for RF part
Introduction
This document states guidelines to be observed when designing RF board with two-layer substrate.
Target Device
RAA604S00
Note: The contents of this document are provided as an example for reference and do not guarantee the signal quality in
systems. When implementing this example into an existing system, thoroughly evaluate the product in the overall
system and apply the contents of this document at your own responsibility.
Contents
1. Overview...........................................................................................................................2
2. Oscillator...........................................................................................................................3
3. External Circuit for DC-DC Converter ............................................................................4
4. RF Signal Lines................................................................................................................5
5. Digital Signal Lines..........................................................................................................6
6. Power Supply ...................................................................................................................7
7. Ground Pattern.................................................................................................................8
8. Circuit Diagram for Reference ........................................................................................9
9. List of Parts for Reference............................................................................................10
R01AN4426EJ0100
Rev.1.00
Dec 21, 2018

RAA604S00 Guidelines for two-layer board for RF part
R01AN4426EJ0100 Rev.1.00 Page 2 of 13
Dec 21, 2018
1. Overview
This document uses the pin names of the RAA604S00. Table 1 briefly describes the pins used in the RAA604S00.
Table 1 Description of the RAA604S00 Pins
1.1 Related Documents
The following document is related to this application note. Also refer to this document when using this application note.
•RAA604S00 User’s Manual: Hardware (R01UH0567EJ)
Pin
Number
Pin Name
I/O
Function
1 STANDBY Input Power down control input of the transceiver
2 OSCDRVSEL Input This signal is for switching the driving ability of the buffer for the 48-MHz
crystal oscillator.
3 SIN Input Serial input
4 SOUT Output Serial output
5 SCLK Input Serial input/output clock
6 SEN Input Serial enable
7 GPIO0 Input/output Transceiver I/O port 0 or CLKOUT
8 GPIO1/ANTSELOUT0 Input/output Transceiver I/O port 1 or ANTSELOUT0
9 INTOUT Output Transceiver interrupt output
10 GPIO2/ANTSELOUT1 Input/output Transceiver I/O port 2 or ANTSELOUT1
11 GPIO3 Input/output Transceiver I/O port 3
12 GPIO4/ANTSW Input/output Transceiver I/O port 4 or ANTSW
13 RFRESETB Input Reset
14 DON Input DC-DC converter enable
15 VREGO2 ―Stabilizing capacitor connection for VCO (1.1 V)
16 VREGO3 ―Power supply stabilizing capacitor connection for PLL (1.1 V)
17 MODE2 Input Mode switch 2
18 MODE1 Input Mode switch 1
19 RFIN ―Transceiver ground
20 RFIP Input RF input
21 AGNDRF1 ―Transceiver ground
22 RFOUT Output RF output
23 AGNDRF2 ―Transceiver ground
24 REXT ―External reference resistor connecting pin
25 VREGO1 ―Power supply stabilizing capacitor connection for the RF section (1.1 to
1.25 V)
26 XIN Input 48-MHz crystal resonator input
27 XOUT/REFCLKIN Input/output 48-MHz crystal resonator output or external clock input
28 VCCRF ―3-V power supply input (1.8 to 3.6 V)
29 REGIN ―Power supply input for the analog section (1.4 to 1.6 V), for external
connection with DDCOUT
30 VSSDDC ―DCDC converter ground
31 DDCOUT ―DCDC converter output (1.4 to 1.6 V), for external connection with
REGIN
32 VCCDDC ―DCDC converter power supply (1.8 to 3.6 V)
Reverse
side
DIEGND ―Ground

RAA604S00 Guidelines for two-layer board for RF part
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Dec 21, 2018
2. Oscillator
Note the following points for design in relation to the oscillator.
•Place the load capacitor close to the crystal resonator electrode.
•Separate the signal lines for the crystal resonator’s pins 26 (XIN) and 27 (XOUT) from those for pin 22 (RFOUT)
by at least 4.5 mm because a narrower separation may lead to an unacceptable level of intermodulation interference.
•We recommend not placing signal lines other than pin 26 (XIN) and pin 27 (XOUT) in the vicinity of the crystal
resonator.
•Separate the ground area for the crystal resonator and load capacitors C5 and C10 from the other ground areas on the
surface layer of the board.
•Connect the wiring between pins 26 (XIN) and 27 (XOUT) on the back of the board through the via holes.
•Before using a crystal resonator, contact the resonator manufacturer to determine its circuit constants.
•When using a neighboring channel of an integral multiple (864 MHz, 912 MHz) of the crystal frequency of 48 MHz,
or when if the distance between pin46(XIN) and pin 47 (XOUT) to pin 43 (RFOUT) can not be increased, insert
the inductor arbitrarily into R3 and R4 according to the clock spurious condition.
Figure 1 shows an example of how to connect a crystal resonator. Figure 2 shows an example of the layout pattern.
Figure 1 Example of How to Connect a Crystal Resonator
Figure 2 Example of Layout Pattern in the Vicinity of the Crystal Resonator
The constants of the load capacitors (C5 and C10) depend on the characteristics of the crystal resonator in use.
Evaluate the oscillation characteristics of the crystal resonator to determine the constants.
XIN
XOUT
C5
C10
X1
R3
(optional)
R4
(optional)
<Component surface>
<Solder surface>
XOUT
RFOUT
XIN
XOUT
R3
R4
X1
C10
C5
X1
4.5mm
XIN

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Dec 21, 2018
3. External Circuit for DC-DC Converter
Note the following points for design in relation to the feedback loop of the DC-DC converter.
•We recommend not placing signal lines in the vicinity of pins 29 (REGIN), 30 (VSSDDC), and 31 (DDCOUT).
•Keep the length of the wiring run between pins 29 (REGIN) and 31 (DDCOUT) as short as possible.
•Place C3 as close to pin 32 (VCCDDC) as is possible.
•C3 and C46 hold the positional relationship of this layout and arrange so that C46 does not get too close to C3.
•Place the board ground from Pin 50 (VSSDDC) in the loop of Pin 49 (REGIN) and Pin 51 (DDCOUT), and place
one or more via.
•Insert the ferrite beads (FB1) arbitrarily according to the noise condition caused by the DC-DC converter.
Figure 3 shows an example of the feedback loop circuit of the DC-DC converter. Figure 4 shows an example of the
layout pattern.
Figure 3 Example of the Feedback Loop Circuit of the DC-DC Converter
Figure 4 Example of the Layout Pattern of the Feedback Loop of the DC-DC Converter
DDCOUT
REGIN
L2
C46
C4
C3
VCCDDC
FB1
(optional)
C14
C46
C3
L2
REGIN
<Component surface>
FB1
VCCDDC
VSSDDC
DDCOUT
C56
C4

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Dec 21, 2018
4. RF Signal Lines
Note the following points for design in relation to the circuit in the vicinity of the RF signal lines.
•Design the RF signal lines as coplanar lines and also as having an impedance of 50 Ω.
•Place as many via holes around the coplanar lines as is possible. The areas around and between the coplanar lines
should be solid stretches of ground with no signal connections.
•The ground for C16, C17, and C18 should be isolated from those for pins 26 (XIN) and 27 (XOUT), so C16, C17
and C18 should be connected to the same stretch of ground as pin 21 (AGNDRF1) or 19 (RFIN). The ground of C15
should be taken from pin 23 (AGNDRF2) side.
•Pin 21 (AGNDRF1) should be connected to the board ground between pins 20 (RFIP) and 22 (RFOUT).
Figure 5 shows an example of the layout pattern in the vicinity of the RF signal lines.
Figure 5 Example of the Layout Pattern in the Vicinity of the RF Signal Lines
C15
C18
C17
AGNDRF1
<Component surface>
AGNDRF2
RFIN
C16
with RF switch
Direct Tie
SW
AGNDRF1
AGNDRF2
RFIN
RFOUT
RFIP
RFOUT
RFIP

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Dec 21, 2018
5. Digital Signal Lines
Note the following points for design in relation to the circuit in the vicinity of the digital signal lines.
•We recommend not placing wiring for pins 3 (SIN), 4 (SOUT), 5 (SCLK), 6 (SEN), and 9 (INTOUT) under the IC,
in the vicinity of the RF signal lines, or in the vicinity of pins 29 (REGIN), 30 (VSSDDC), 31 (DDCOUT), and 32
(VCCDDC).
•Keep the digital signal lines as short as possible to reduce digital noise. We recommend inserting series resistors as
required. In that case must be placed R16, R18, and R19 on the MCU side and R17 and R20 on the RAA604S00
side.
Figure 6 shows an example of the layout pattern in the vicinity of the digital signal lines.
Figure 6 Example of the Layout Pattern in the Vicinity of the Digital Signal Lines
<Component surface>
SIN
SOUT
SCLK
SEN
INTOUT
R16
R17
R18
R19
R20
MCU

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6. Power Supply
Note the following points for design in relation to the power supply circuit.
•Place the bypass capacitors on the surface layer of the board and as close as possible to the pins.
•Place the ground of C14, C56 as closely as possible to pin 23 (AGNDRF2).
•Separate the grounds for C26, C27, and C55 from the surface layer of the board and insert the slit from base of the
pins on the back layer, to avoid interference from the signal on pin 20 (RFIN). Place them as far as possible from the
RF signal lines.
•We recommend not placing signal lines in the vicinity of pins 28 (VCCRF) and 32 (VCCDDC).
•Make the wiring as thick as possible to keep the impedance low.
•Make sure that the RF GND is not divided by the wiring of the power supply line.
•Place a via hole for each bypass capacitor.
•We recommend not placing via holes between the IC and bypass capacitors.
Figure 7 shows an example of how to place the bypass capacitors.
Note: The level of generated noise depends on the implementation of the board. Add bypass capacitors as
required (this figure is merely an example).
Figure 7 Example of How to Place the Bypass Capacitors
C46
C6
C14
C27
C26
C55
C56
C3
C4
<
Component surface
>
VCCRF
VCCDDC
RFIN
<
Solder surface
>
AGNDRF2

RAA604S00 Guidelines for two-layer board for RF part
R01AN4426EJ0100 Rev.1.00 Page 8 of 13
Dec 21, 2018
7. Ground Pattern
Note the following points for design in relation to the ground pattern.
•Place as many via holes as possible to create short circuits with ground patterns in other layers. This helps keep the
impedance low.
•Connect pins 17 (MODE2), 18 (MODE1), 19 (RFIN), 21 (AGNDRF1), 23 (AGNDRF2), and 30 (VSSDDC) to the
die pad. Note that the via holes for the ground pattern should not be placed near pin 30 (VSSDDC).
•We recommend not placing signal lines under the die pad if the signals may be active during transmission and
reception.
Figure 8 shows an example of the layout pattern of the die pad.
Figure 8 Example of Layout Pattern of the Die Pad
VSSDDC
<Component surface>
MODE1
MODE2
RFIN
AGNDRF2
AGNDRF1

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Dec 21, 2018
8. Circuit Diagram for Reference
Figure 9 and Figure 10 are circuit diagram for reference.
Figure 9 Circuit diagram for direct tie
Figure 10 Circuit diagram with RF switch
1
2
3
4
A B C D E F G H
1
2
3
4
A B C D E F G H
X'tal
3G4
G
2X'tal 1
X1
R16
R17
R18
R19
R20
L4
L5
C17
C27
PAD5 PAD4
C4
C3 L2
C5
R4
R3
C26 C55
R10
P60
1
P61
2
P62
3
P63
4
P31
5
P74
7
P73
8
P72
9
P71
10
P70
11
P50 13
P51 14
P17 15
P16 16
P15 17
P14 18
P13 19
P12 20
P11 21
P10 22
P146 23
P147 24
P27 25 P26 26 P25 27 P24 28 P23 29 P22 30
P130 33
P01/RxD1 34 P00/TxD1 35
P140 36
P120
37
P41
38
P40/TOOL0
39
RESETB
40
P137
43
P122/X2
44
P121/X1
45
REGC
46
VSS
47
VDD
48
DieGND
49
P124/XT2
41
P123/XT1
42
P75
6P20/AVREFP 32
P21/AVREFM 31
P30/INTP3
12
R5F104GLANA
IC2
PAD6
2
3 4
6
8
9
42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
10 TXD
12 P72
14 P70
16 P60
20 P21
22 P62
24 P63
38 P120
40 P122
1
7
RESETB
11
RXD 13
P71
17
P20 19
P61 21
P75
25
P31 27
P140 23
P22
41
P121
28 P137
5
TOOL0
15
P23 18 P24
29
P147 31
P73 33
P74 35
P25 37
P27 39
P41
26 P26
30 P146
32 P50
34 P51
36 P17
CN1
R5 R6
C28
C29
X2
FB2
C1
C9
VDD
PAD12
GND
PAD11
PAD7 PAD8
R11
R7
C18
L6
1
2
34
5
6SAW1
C15
PAD3
PAD2 PAD1
C10
C6
1.STANDBY
1
2.OSCDRVSEL
2
3.SIN
3
4.SOUT
4
5.SCLK
5
6.SEN
6
7.GPIO0
7
8.GPIO1
8
9.INTOUT
9
10.GPIO2
10
11.GPIO3
11
12.GPIO4
12
13.RFRESETB
13
14.DON
14
15.VREGO2
15
16.VREGO3
16
17.MODE2 17
18.MODE1 18
19.RFIN 19
20.RFIP 20
21.AGNDRF1 21
22.RFOUT 22
23.AGNDRF2 23
24.REXT 24
25VREGO1 25
26.XIN 26
27.XOUT 27
28.VCCRF 28
29.REGIN 29
30.VSSDDC 30
31.DDCOUT 31
32.VCCDDC 32
DieGND
33
(RF)
(VCO)
(PLL)
RAA604S00
IC1
R9 C23
R8
J1
C7
C8
R2
R1
C14 C56
PAD9 PAD10
C45C46
FB1
1
2
3
4
A B C D E F G H
1
2
3
4
A B C D E F G H
R16
R18
R19
C27
PAD5 PAD4
C4
C3 L2 FB1
C26 C55
R10
P60
1
P61
2
P62
3
P63
4
P31
5
P74
7
P73
8
P72
9
P71
10
P70
11
P50 13
P51 14
P17 15
P16 16
P15 17
P14 18
P13 19
P12 20
P11 21
P10 22
P146 23
P147 24
P27 25 P26 26 P25 27 P24 28 P23 29 P22 30
P130 33
P01/RxD1 34 P00/TxD1 35
P140 36
P120
37
P41
38
P40/TOOL0
39
RESETB
40
P137
43
P122/X2
44
P121/X1
45
REGC
46
VSS
47
VDD
48
DieGND
49
P124/XT2
41
P123/XT1
42
P75
6P20/AVREFP 32
P21/AVREFM 31
P30/INTP3
12
R5F104GLANA
IC2
PAD6
2
3 4
6
8
9
42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
10 TXD
12 P72
14 P70
16 P60
20 P21
22 P62
24 P63
38 P120
40 P122
1
7
RESETB
11
RXD 13
P71
17
P20 19
P61 21
P75
25
P31 27
P140 23
P22
41
P121
28 P137
5
TOOL0
15
P23 18 P24
29
P147 31
P73 33
P74 35
P25 37
P27 39
P41
26 P26
30 P146
32 P50
34 P51
36 P17
CN1
R5 R6
C28
C29
X2
FB2
VDD
PAD12
PAD7 PAD8
R11
R9 C23
C22 1
2
3 4
5
6
Vdd
CTL
SW1
R7
R8
1
2
34
5
6SAW1
C1
C9
GND
PAD11
X'tal
3G4
G
2X'tal 1
X1
R4
R3
C6
R20
R17
C5
C21
C31
C16
R15
PAD3
PAD2 PAD1
C32
C24
R2R1
C10
C8
C7
J1
1.STANDBY
1
2.OSCDRVSEL
2
3.SIN
3
4.SOUT
4
5.SCLK
5
6.SEN
6
7.GPIO0
7
8.GPIO1
8
9.INTOUT
9
10.GPIO2
10
11.GPIO3
11
12.GPIO4
12
13.RFRESETB
13
14.DON
14
15.VREGO2
15
16.VREGO3
16
17.MODE2 17
18.MODE1 18
19.RFIN 19
20.RFIP 20
21.AGNDRF1 21
22.RFOUT 22
23.AGNDRF2 23
24.REXT 24
25VREGO1 25
26.XIN 26
27.XOUT 27
28.VCCRF 28
29.REGIN 29
30.VSSDDC 30
31.DDCOUT 31
32.VCCDDC 32
DieGND
33
(RF)
(PLL)
(VCO)
RAA604S00
IC1
L3
C14 C56
PAD9 PAD10
C46 C45

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R01AN4426EJ0100 Rev.1.00 Page 10 of 13
Dec 21, 2018
9. List of Parts for Reference
Table 2 lists parts for reference.
Table 2 List of Parts for Reference (1/2)
*1 with RF switch, *2 for ARIB, *3 for ETSI, *4 for FCC
Parts ID Description Parts number Remarks
C1 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C3 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C4 Not mounted Mounting a capacitor here is a way of reducing spurious emissions during
signal transmission.
Example value: 1 uF (self-resonance frequency of about 10 MHz)
C5,
C10 9pF →This provides a load capacitance for the crystal resonator and its value
depends on the parasitic capacitance of the combination of the crystal
resonator and the board on which it is mounted.
C6 4.7nF GRM155R71E472KA01D We recommend a tolerance of ± 10%.
C7,
C8 Not mounted →This provides a load capacitance for the crystal resonator and its value
depends on the parasitic capacitance of the combination of the crystal
resonator and the board on which it is mounted.
C9 10uF GRM188D71A106MA73 We recommend a tolerance of ± 10%.
C14 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C15 3.3pF*2
6.8pF*
3
GRM1553C1H3R3CZ01D
GRM1553C1H6R8CZ01D
We recommend a tolerance equivalent to ± 0.25 pF.
C16*16pF
4.7pF*
4
GRM1552C1H6R0CA01D
GRM1552C1H4R7CZ01D
We recommend a tolerance equivalent to ± 0.25 pF.
C17 4.7pF*2
5.6pF*
3
GRM1552C1H4R7CZ01D
GRM1552C1H5R6CZ01D
We recommend a tolerance equivalent to ± 0.25 pF.
C18 5.6pF*2
6.8pF*
3
GRM1552C1H5R6CA01D
GRM1552C1H6R8CA01D
We recommend a tolerance equivalent to ± 0.25 pF.
C21*147pF GRM1552C1H470JA01D DC blocking capacitor
C22*147pF
8.2nH*4GRM1552C1H470JA01D
LQW15AN8N2C10
DC blocking capacitor
Mounting an inductor here is a way of reducing harmonics during signal
transmission.
C23*147pF GRM1552C1H470JA01D DC blocking capacitor
C24 Not mounted
C26 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C27 Not mounted Mounting a capacitor here is a way of reducing noise in received signals.
Example value: 12 pF (self-resonance frequency of about 2.5 GHz)
C28 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C29 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C31*41000pF GRM1552C1H102JA01D Decoupling capacitor
C32*41000pF GRM1552C1H102JA01D Decoupling capacitor
C45 Not mounted Mounting a capacitor here is a way of reducing noise in received signals.
Example value: 47 pF (self-resonance frequency of about 1 GHz)
C46 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C55 1uF GRM155B31C105KA12D We recommend a tolerance of ± 10%.
C56 Not mounted Mounting a capacitor here is a way of reducing spurious emissions during
signal transmission.
Example value: 2.2 nF (self-resonance frequency of about 200 MHz)
CN1 Connector DF17(2.0)-60DP-0.5V(57)
PAD Test-pin 9-146278-0