Renesas IDT 89EBPES16T7 User manual

®
March 2007
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX:[phone]
Printed in U.S.A.
©2007 Integrated Device Technology,Inc.
IDT™89EBPES16T7
Evaluation Board Manual
(Eval Board: 18-610-000)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patentrights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
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Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unlessa specific written agreementpertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support orsustain life and whose failure to perform,
when properly used in accordance with instructions for use providedin the labeling, can be reasonably expected toresult in a significant injury to the user.
2.A criticalcomponentisanycomponentsof a lifesupportdeviceorsystemwhosefailuretoperformcanbe reasonablyexpected to cause the failure of the life supportdevice
or system, or to affect its safety or effectiveness.
IDT,the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
EB16T7 Eval Board Manual i March 30, 2007
Table of Contents
®
Description of the EB16T7 Eval Board
Introduction.....................................................................................................................................1-1
Board Features...............................................................................................................................1-2
Hardware................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB16T7 Eval Board
EB16T7 Installation.........................................................................................................................2-1
Hardware Description .....................................................................................................................2-1
Host System...........................................................................................................................2-1
Reference Clocks............................................................................................................................2-2
Power Sources................................................................................................................................2-3
External Power Source...........................................................................................................2-3
PCI Express Serial Data Transmit Termination Voltage Converter........................................2-4
PCI Express Digital Power Voltage Converter........................................................................2-4
PCI Express Analog Power Voltage Converter......................................................................2-4
Core Logic Voltage Converter................................................................................................2-4
3.3V I/O Power Module...........................................................................................................2-4
Power-up Sequence...............................................................................................................2-4
Required Jumpers..................................................................................................................2-4
Reset...............................................................................................................................................2-4
Fundamental Reset................................................................................................................2-5
Downstream Reset.................................................................................................................2-5
Boot Configuration Vector...............................................................................................................2-5
SMBus Interfaces............................................................................................................................2-7
SMBus Slave Interface...........................................................................................................2-7
SMBus Master Interface.........................................................................................................2-9
JTAG Header................................................................................................................................2-10
Attention Buttons...........................................................................................................................2-11
Miscellaneous Jumpers, Headers.................................................................................................2-11
LEDs.............................................................................................................................................2-12
PCI Express Connectors...............................................................................................................2-14
Locations of Connectors, Jumpers, and Switches........................................................................2-16
Software for the EB16T7 Eval Board
Introduction.....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics.....................................................................................................................................4-1

IDT Table of Contents
EB16T7 Eval Board Manual ii March 30, 2007
Notes

Notes
EB16T7 Eval Board Manual iii March 30, 2007
List of Tables
®
Table 2.1 Clock Source Selection .......................................................................................................2-2
Table 2.2 Clock Frequency Selection .................................................................................................2-3
Table 2.3 Clock Spread Spectrum Selection ......................................................................................2-3
Table 2.4 SMA Connectors - Onboard Reference Clock ....................................................................2-3
Table 2.5 External Power Connector - J1 ...........................................................................................2-4
Table 2.6 Downstream Reset Selection .............................................................................................2-5
Table 2.7 Boot Configuration Vector Signals ......................................................................................2-6
Table 2.8 Boot Configuration Vector Switches S5 & S6 (ON=0, OFF=1) ...........................................2-6
Table 2.9 Slave SMBus Interface Connector ......................................................................................2-7
Table 2.10 SMBus Slave Interface Address Configuration ...................................................................2-8
Table 2.11 PES16T7 SMBus Slave Interface Address Setting ............................................................2-8
Table 2.12 I/O Expander 0 Bus Address ..............................................................................................2-9
Table 2.13 I/O Expander 1 Bus Address ..............................................................................................2-9
Table 2.14 I/O Expander 2 Bus Address ..............................................................................................2-9
Table 2.15 I/O Expander 4 Bus Address ............................................................................................2-10
Table 2.16 EEPROM SMBus Address Setting ...................................................................................2-10
Table 2.17 JTAG Connector Pin Out ..................................................................................................2-11
Table 2.18 Attention Buttons ..............................................................................................................2-11
Table 2.19 Miscellaneous Jumpers, Headers .....................................................................................2-11
Table 2.20 LED Indicators ..................................................................................................................2-13
Table 2.21 PCI Express x16 Connector Pinout ..................................................................................2-14

IDT Table of Contents
EB16T7 Eval Board Manual iv March 30, 2007
Notes

Notes
EB16T7 Eval Board Manual v March 30, 2007
List of Figures
®
Figure 1.1 Function Block Diagram of the EB16T7 Eval Board ..........................................................1-1
Figure 2.1 SuperMicro X6DH8-G2 Motherboard .................................................................................2-2

IDT List of Figures
EB16T7 Eval Board Manual vi March 30, 2007
Notes

Notes
EB16T7 Eval Board Manual 1 - 1 March 30, 2007
®
Chapter 1
Description of the EB16T7
Eval Board
Introduction
The 89HPES16T7 switch (also referred to as PES16T7 in this manual) is a member of the IDT PCI
Express® standard (PCIe®) based line of products.It is a 16-lane, 7-port switch, with 4 serial lanes onthree
ports and 1 seriallane on fourports. Oneupstream port isprovided for connecting tothe rootcomplex (RC),
and up to six downstream ports are available for connecting to PCIe endpoints or to another switch. More
information on this device can be found in the 89HPES16T7 User Manual.
The 89EBPES16T7 Evaluation Board (also referred to as EB16T7 in this manual) provides an evalua-
tion platform for the PES16T7 switch. It is also a cost effective way to add a PCIe downstream port (x4 and
x1) to an existing system with a limited number of PCIe downstream ports. The EB16T7 eval board is
designed to function as an add-on card to be plugged into a x8 PCIe slot available on a motherboard
hosting an appropriate root complex, microprocessor(s), and five downstream ports. The EB16T7 is a
vehicle to test and evaluate the functionality of the PES16T7 chip. Customers can use this board to get a
headstart on software development prior to the arrival of their own hardware. The EB16T7 is also used by
IDT to reproducesystem-level hardware or software issues reported by customers. Figure 1.1illustrates the
functional block diagram representing the main parts of the EB16T7 board.
Figure 1.1 Function Block Diagram of the EB16T7 Eval Board
JTAG
Header
Main
Reset
I/O Expander
PCA9555
PCIe x8 Upstream Edge
EEPROM
24LC512
SMBUS
HEADER
PES16T7
PCI Express
Switch
External Power
PCIe x1 Downstream Slot
x8
x1
25 MHz
SSC Clock
Buffer
Clock
Fanout
SMBus
Voltages on board
+12V, +3.3V, +1.5V, +1.0V
Connector
Power
Module
PTH08T240
x1
x1 x1
PCIe x4 Downstream Slot
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
x4

IDT Description of the EB16T7 Eval Board
EB16T7 Eval Board Manual 1 - 2 March 30, 2007
Notes Board Features
Hardware
PES16T7 PCIe 7 port switch
– One x8 port, one x4 port, four x1 ports, 16 PCIe lanes
– PCIe Base Specification Revision 1.1 compliant
–8 GBps (64Gbps) aggregate switching capacity
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x8, x4, x2,x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a slot with at least x8 capable on a
host motherboard
– Five slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
One of these slot connectors are x16 mechanically but electronically connected as x4 only.
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates and spread spectrum settings
– Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES16T7 within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows2000, WindowsXP, Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES16T7
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is required to firmly hold in place two of the three endpoints plugged into the
EB16T7 board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB16T7 board for specific test points.

IDT Description of the EB16T7 Eval Board
EB16T7 Eval Board Manual 1 - 3 March 30, 2007
Notes Revision History
October 19, 2006: Initial publication of board manual.
November 13, 2006: In Tables 2.7 and 2.8, changed MSMSDDR to MSMBADDR and removed refer-
ences to P23MERGEN, P45MERGEN, and SWMODE[3].
March 30, 2007: In Figure 1.1, revised diagram to show a x4 connection from the PES16T7 device to
the x4 downstream slot.In Board Features section, revised firstline to clarify theboard has one x8port, one
x4 port, and four x1 ports.

IDT Description of the EB16T7 Eval Board
EB16T7 Eval Board Manual 1 - 4 March 30, 2007
Notes

Notes
EB16T7 Eval Board Manual 2 - 1 March 30, 2007
®
Chapter 2
Installation of the EB16T7
Eval Board
EB16T7 Installation
This chapter discusses the steps required to configure and install the EB16T7 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB16T7 board is shipped with all jumpers and switches configured to theirdefault settings. In most
cases, the board does not require further modification or setup.
Hardware Description
The PES16T7 is a 16-lane, 7-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers
and storage. It provides fan-out and switching functions between a PCI Express upstream port and up to 6
downstream ports or peer-to-peer switching between downstream ports.
The EB16T7 has five PCI Express downstream ports, accessible throughone x16 connector and fourx1
connectors. One specific port is capable of negotiating a x1, x2, or x4 link width and the remaining four
ports are capable of negotiating a x1 link width. All endpoint cards connected to the PES16T7 must support
at least one of these link widths.
Basic requirements for the board to run are:
–Host system with a PCI Express rootcomplex supporting x8 configuration through a PCI Express
x8 slot. (If your host system does not offer a x8 slot, please contact [email protected] for alterna-
tive solutions.)
–x1, x2, x4, or x8 PCI Express Endpoint Cards.
Host System
The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x8 configuration through a PCI Express x8 slot is required to take full
advantage of the PES16T7’s capabilities. One such system is the SuperMicro X6DH8-G2 motherboard
equipped with an Intel E7520 chipset which was introduced in 2004 to deploy dual-processor server chipset
technology. The board has three PCI Express slots. All slots have x8 connectors, but only two are electron-
ically connected for a x8 link width (J15 and J16). The remaining slots are electronically connected for a x4
link width configuration. Care must be taken to avoid using the EB16T7 in the x4 slot (J17). Figure 2.1
shows the proper connectors.

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 2 March 30, 2007
Notes
Figure 2.1 SuperMicro X6DH8-G2 Motherboard
Reference Clocks
The PES16T7 requires two differential reference clocks. The EB16T7 derives both of these clocks from
a common source which is user-selectable. The common source can be either the host system’sreference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1.
Clock Configuration Stuffing Option
Install Clock Source
R36, R37 Onboard Reference Clock – Use onboard clock generator
R34, R35 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 3 March 30, 2007
Notes The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB16T7 allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.
If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated
clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the
upstream reference clock should be used instead.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Power Sources
The upstream port consists of port 0 and port 1. The EB16T7 and all downstream ports are powered
from the upstream port slot power. If add-in cards require more power than the upstream slot can support,
an external source is required to supply this extra power via an auxiliary 4-pin power connector on the
board. Only downstream ports 2, 3,4, and 5can be poweredby this externalpower source throughjumpers
W45, W46, and W47 (see Table 2.19). Note that on the schematic pages in Chapter 4, port 2 is also
referred to as port F, port 3 as port E, port 4 as port D, and port 5 as port C.
External Power Source
If necessary, external power is supplied to the EB16T7 board through a4-pin auxiliary power connector
attached to J1. Theexternal power supply provides+12V to the EB16T7 as described in Table 2.5. The +5V
is unused.
Clock Frequency Switch - S2[2:1]
S2[2] S2[1] Clock Frequency
OFF OFF Reserved
OFF ON 125 MHz
ON OFF 100 MHz (Default)
ON ON <Reserved>
Table 2.2 Clock Frequency Selection
Clock Spread Spectrum Switch - S2[4:3]
S2[4] S2[3] Spread%
OFF OFF No Spread (Default)
OFF ON Down -0.75
ON OFF Down -0.50
ON ON Center ±0.25
Table 2.3 Clock Spread Spectrum Selection
Onboard Reference Clock Output (Differential) – J3, J2
J3 Positive Reference Clock
J2 Negative Reference Clock
Table 2.4 SMA Connectors - Onboard Reference Clock

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 4 March 30, 2007
Notes
PCI Express Serial Data Transmit Termination Voltage Converter
A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown
as VTTPE or VPETVTT) to the PES16T7.
PCI Express Digital Power Voltage Converter
A separate DC-DC converter (U3) provides a 1.0V PCI Express digital power voltage (VDDPE) to the
PES16T7.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (U7) provides a 1.0V PCI Express analog power voltage (shown as
VDDAPE or VDDPEA) to the PES16T7.
Core Logic Voltage Converter
A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES16T7.
3.3V I/O Power Module
A 12V to 3.3V power module (U5 or U26) provides the 3.3V I/O voltage (VDDIO) to the PES16T7.
Power-up Sequence
The power-up sequence must be as following:
1. VDDIO - 3.3V
2. VDDCORE, VDDAPE, VDDPE - 1.0V
3. VTTPE - 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the
sequence to ensure internal latch-up issues are avoided. There are no maximum limitations to the time to
valid power level requirements. To insure that the sequencing requirements are met, a 0.047µF is used at
the SOFTSTART cap on the VTTPE’s voltage converter (U6 pin 36) in the EB16T7.
Required Jumpers
To deliver power to the PES16T7 switch, the following jumpers must be shunted: W10 and W22—W25.
These jumpers were implemented so that the power consumption of the PES16T7 can be measured.
Reset
The PES16T7 supports two types of reset mechanisms as described in the PCI Express specification:
–Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES16T7, and the endpoints.
–Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES16T7
User Manual. The EB16T7 evaluation board provides seamless support for Hot Reset.
Pin Signal
1+12V
2GND
3GND
4+5V
Table 2.5 External Power Connector - J1

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 5 March 30, 2007
Notes Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB16T7 evaluation board:
–Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES16T7.
–Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
•Pressing a push-button switch (S1) located on EB16T7 board
•The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB16T7. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W1.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16T7 while power is on.
Downstream Reset
The PES16T7 provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.6.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES16T7
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S5 and S6 as defined in Table 2.8.
Port # Jumper Selection
6 W27 [1-2] Software controlled reset through GPIO11
[2-3] Fundamental reset PERST# (default)
5 W30 [1-2] Software controlled reset through GPIO10
[2-3] Fundamental reset PERST# (default)
4 W35 [1-2] Software controlled reset through GPIO01
[2-3] Fundamental reset PERST# (default)
3 W38 [1-2] Software controlled reset through GPIO9
[2-3] Fundamental reset PERST# (default)
2 W56 [1-2] Software controlled reset through GPIO0
[2-3] Fundamental reset PERST# (default)
Table 2.6 Downstream Reset Selection

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 6 March 30, 2007
Notes Signal Description
CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the SlotClock Configuration bit inall of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the down-
stream port’s PCIELSTS register. Default: 0x1
CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is
using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Default: 0x1
MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
P01MERGEN Port 0 and 1 Merge: When this pin is asserted (i.e. low), port 1 is merged with port 0 to
form a single x8 port. Default: 0x0
RSTHALT Reset Halt. When thissignal is asserted during a PCI Express fundamental reset, the
PES16T7 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
SWMODE[2:0] Switch Mode. These configuration pins determine the PES16T7 switch operating mode.
Default: 0x1
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0x4 - Reserved
0x5 - Global SerDes test mode
0x6 - Reserved
0x7 - PLL bypasstest mode
REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-
erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0] MasterSMBus Address. ThesepinsdeterminetheSMBus addressofthe serialEEPROM
from which configuration information is loaded. Default: 0x0
Table 2.7 Boot Configuration Vector Signals
Signal Description Default
S6[1] CCLKDS OFF
S6[2] CCLKUS OFF
S6[3] MSMBSMODE ON
S6[4] P01MERGEN ON
S6[5] Not Used OFF
S6[6] Not Used OFF
S6[7] Not Used OFF
Table 2.8 Boot Configuration Vector Switches S5 & S6 (ON=0, OFF=1) (Part 1 of 2)

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 7 March 30, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES16T7 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface.
The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all soft-
ware-visible registers. The Master SMBus interface provides connection to the external serial EEPROMs
used for initialization and the I/O expander used for hot-plug signals.
SMBus Slave Interface
On the PES16T7 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R202 and R203.
.
A fixed slave SMBus address specified by the SSMBADDR[5,3:1] pins is used.
For a fixed address, the SMBus address of the PES16T7 slave interface is 0b1110111 by default and is
configurable using jumpers W40, W41, W42, and W43 as described in Tables 2.10 and 2.11.
S6[8] RSTHALT OFF
S5[1] SWMODE[0] OFF
S5[2] SWMODE[1] ON
S5[3] SWMODE[2] ON
S5[4] Not Used ON
S5[5] REFCLKM ON
S5[6] MSMBADDR[0] ON
S5[7] MSMBADDR[1] ON
S5[8] MSMBADDR[2] ON
Slave SMBus Interface Connector
J10
Pin Signal
1N/C
2SCL
3GND
4SDA
Table 2.9 Slave SMBus Interface Connector
Signal Description Default
Table 2.8 Boot Configuration Vector Switches S5 & S6 (ON=0, OFF=1) (Part 2 of 2)

IDT Installation of the EB16T7 Eval Board
EB16T7 Eval Board Manual 2 - 8 March 30, 2007
Notes
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
–Byte and Word Write/Read
–Block Write/Read
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
40
5 SSMBUSADDR[5]
61
71
Table 2.10 SMBus Slave Interface Address Configuration
SMBUS Slave Interface Address Setting
W40
SSMBADDR[5] W41 SSMBADDR[3] W42 SSMBADDR[2] W43 SSMBADDR[1] Slave Interface Bus Address
OFF OFF OFF OFF 0b1110111 (Default)
OFF OFF OFF ON 0b1110110
OFF OFF ON OFF 0b1110101
OFF OFF ON ON 0b1110100
OFF ON OFF OFF 0b1110011
OFF ON OFF ON 0b1110010
OFF ON ON OFF 0b1110001
OFF ON ON ON 0b1110000
ON OFF OFF OFF 0b1100111
ON OFF OFF ON 0b1100110
ON OFF ON OFF 0b1100101
ON OFF ON ON 0b1100100
ON ON OFF OFF 0b1100011
ON ON OFF ON 0b1100010
ON ON ON OFF 0b1100001
ON ON ON ON 0b1100000
Table 2.11 PES16T7 SMBus Slave Interface Address Setting