Renesas RC32504A User manual

Evaluation Board Manual
RC32504A /
RC22504A
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
Page 1
© 2021 Renesas Electronics
The RC32504A / RC22504A evaluation board (EVB)
is designed to help users evaluate the RC32504A
and RC22504A Clock Generators, also known as
FemtoClock 2. The RC32504A supports Jitter
Attenuator and Synthesizer functionality, and the
RC22504A supports only Synthesizer functionality.
When the evaluation board (EVB) is connected via
USB to the user’s computer running the Renesas’
RICBox™ Software, FemtoClock 2 can be configured
and programmed to generate frequencies with best-
in-class performance. FemtoClock 2 has four output
pairs that can be programmed to CMOS style, LVDS
style, or HCSL style outputs.
Features
■Develop configurations with Renesas RICBox
software and upload to the EVB through USB
■Can be powered from the USB connection
■EVB is a combination evaluation with Renesas
Low Noise power supply regulators and Renesas
Low Noise fan-out buffer
■Clock output pairs are AC coupled and can be
connected directly to test equipment through coax
cables.
Board Contents
■Renesas RS32504A ultra-low noise synthesizer
and jitter attenuator
■Renesas RAA214020 low-noise power supply
regulators
■Renesas 8P34S1208I low-noise fan-out buffer
■FTDI FT232HQ USB-to-I2C bridge
Figure 1. RC32504A / RC22504A Board

RC32504A / RC22504A Evaluation Board Manual
R31UH0001EU0100 Rev.1.0
Apr 21, 2021
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Contents
1. Functional Description.................................................................................................................................. 3
1.1 Connecting the Board to a Computer.................................................................................................... 3
1.2 Board Power Supply.............................................................................................................................. 4
1.3 Differential Output Termination Selectors ............................................................................................. 4
1.4 Miscellaneous Selectors........................................................................................................................ 5
1.5 On-Board Crystal................................................................................................................................... 7
1.6 Bypassing the Fan-Out Buffer at OUT0................................................................................................. 7
1.7 Setup and Configuration........................................................................................................................ 8
2. Board Design................................................................................................................................................ 12
2.1 Schematic Diagrams............................................................................................................................ 15
2.2 Bill of Materials .................................................................................................................................... 17
3. Ordering Information................................................................................................................................... 19
4. Revision History .......................................................................................................................................... 19
Figures
Figure 1. RC32504A / RC22504A Board..................................................................................................................1
Figure 2. Power Source Selector Example...............................................................................................................4
Figure 3. Power Source Selector for VDDD.............................................................................................................4
Figure 4. Termination Bias Jumpers.........................................................................................................................5
Figure 5. Termination Bias Schematic......................................................................................................................5
Figure 6. OE Pin Control...........................................................................................................................................5
Figure 7. Lock Pin and SDA Pin Latch Control.........................................................................................................6
Figure 8. Buffer Input Select.....................................................................................................................................6
Figure 9. Crystal and XIN Input ................................................................................................................................7
Figure 10. OE Pin Control.........................................................................................................................................7
Figure 11. RC32504A / RC22504 EVB – Block Diagram.......................................................................................12
Figure 12. RC32504A / RC22504A Board – Top View ..........................................................................................13
Figure 13. RC32504A Evaluation Board Schematics – Page 1.............................................................................15
Figure 14. RC32504A Evaluation Board Schematics – Page 2.............................................................................16
Figure 15. RC32504A Evaluation Board Schematics – Page 3.............................................................................16
Figure 16. RC32504A Evaluation Board Schematics – Page 4.............................................................................17

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Apr 21, 2021
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1. Functional Description
1.1 Connecting the Board to a Computer
The evaluation board can be connected to a computer via the USB connector (see Figure 4). This board has a
USB-C type connector. The on-board USB-to-I2C bridge (FTDI chip) handles the data communication, and the
+5V in the USB bus powers the on-board regulators. Using a bench power supply with the VDD jacks is optional.
The board can fully function with just the USB cable to a computer.
Renesas’ RICBox Software can control the RC32504A on the board. RICBox is compatible with both the on-
board USB-to-I2C bridge and the Aardvark adapter. RICBox uses a software wizard for entering the overall
configuration and has several tools to fine tune the configuration (e.g., block diagram GUI).
The Bus Source connector J30 can be used to select the source of the communication bus. The bus will be I2C
for most communication but can also be SPI for specific tests. Pins 1 and 2 in J30 are SDA and SCL from the
FTDI chip. Pins 3 and 4 pass the SDA and SCL to the I2C level shifter. To use the on-board FTDI chip, install
jumpers on pins 1-3 and 2-4. The board will be shipped with these jumpers installed. Theoretically, any I2C
adapter can be connected to pins 3 and 4 for SDA and SCL. Pin 6 can be used as the ground connection for the
I2C connection. Pins 3, 4, 5, and 6 are arranged such that an Aardvark connector can be plugged onto pins 3, 4,
5, and 6 only (see Figure 5).
The Bus Type connector J33 is added to allow bypassing the I2C Level Shifter in case the connection type is
SPI. For default I2C operation, jumpers are installed on pins 1-3 and 2-4.
Figure 4. Communication Path Block Diagram
Figure 5. Connect Aardvark Adapter to J30
In Figure 14 the Aardvark adapter communicates with the RC32504A and the FTDI bridge chip is disconnected.
USB can still be used to power the board.

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1.2 Board Power Supply
The power source for each VDD pin can be selected with jumpers. The voltage for each pin, except one, is 1.8V.
The exception is VDDD, which can be powered with 1.8V or 3.3V.
The power source can be either an on-board voltage regulator or the VDD_J jack. Most power source selectors
have only two choices, 1.8V from the on-board 1.8V regulator or connect to the VDD_J J21 jack. The jack can
connect to a bench supply; this connection can be useful, for example, to measure supply current into pins.
In Figure 2 the source for the pin VDDXO is chosen to be the on-board 1.8V regulator. The two pins on the
bottom are both connected to the VDDXO pin through a power filter. The top left pin is connected to the on-
board 1.8V regulator and the top right pin is connected to the VDD_J jack. `
Figure 2. Power Source Selector Example
In Figure 3 the source for the pin VDDD is chosen to be the on-board 3.3V regulator. J25 allows three choices
for VDDD: 1.8V, 3.3V, or the VDD_J jack. The three pins on the right are all connected to the VDDD pin through
a power filter. The top left pin is connected to the on-board 3.3V regulator, the mid left pin is connected to the on-
board 1.8V regulator, and the bottom left pin is connected to the VDD_J Jack.
Figure 3. Power Source Selector for VDDD
1.3 Differential Output Termination Selectors
Each of the four differential output pairs can be programmed to LVDS, HCSL, or CMOS logic type. CMOS is a
single-ended logic type and the output pair will essentially be two CMOS outputs of the same frequency. HCSL
is the most versatile output because it can be customized. The HCSL driver is a current driver that simply turns a
current on and off. Standard HCSL turns 15mA on and off to make 750mVpp swing in 50Ωtermination.
The RC32504A HCSL driver can be programmed to drive 4mA to 19mA levels. When AC coupled, the HCSL
driver can be compatible with LVDS, CML, and LVPECL signal swing requirements. Because of the output
architecture, it needs a DC coupled termination to ground to drive the current into. The circuit at each output
splits the termination into a DC part and an AC coupled RF part. The RF part is connected to the SMA edge
connectors of each output and the DC part is controlled by the termination selectors.

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Figure 4. Termination Bias Jumpers
Figure 4 shows J36 for applying DC load to OUT0. When HCSL is selected and the on-chip termination is
disabled, a jumper must be placed to provide the required DC load to ground. No jumper is needed for LVDS or
LVCMOS, and when the on-chip termination is enabled with HCSL.
Separating DC load from AC coupled RF load helps increase the signal swing on the SMA connectors for better
noise measurements. This method can also be used in the end application when the receiver input has on-chip
termination, is AC coupled, and a large signal swing is required.
Figure 5. Termination Bias Schematic
1.4 Miscellaneous Selectors
Figure 6. OE Pin Control
J32 pins 2, 4, and 6 connect together to the OE pin of the RC32504A. Apply a jumper on pins 1 and 2 to pull the
OE pin high or on 5 and 6 to pull the OE pin low. The RC32504A can be programmed to pull high or low on the
chip so in most cases no jumpers are needed on J32.

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A pull-up or pull-down jumper can also be used to latch a specific programmed configuration at power up.
When experimenting with SPI, a jumper can be applied to pins 3 and 4 to pass the CS (Chip Select) signal from
the FTDI chip to the RC32504A.
Figure 7. Lock Pin and SDA Pin Latch Control
J34 can be used to latch a specific level on the LOCK pin at power up. J35 can be used to latch a specific level
on the SDA pin at power up.
Both are used to select a specific pre-programmed configuration. It is not needed to program OTP of the
RC32504A on the evaluation board. Every possible configuration can be set up with RICBox in volatile registers.
It is not recommended to attempt to program the OTP memory because of the risk that a mistake or error can
destroy the chip.
Figure 8. Buffer Input Select
J48 can be used to select the input source for the 8P34S1208I fan-out buffer. The CLK0 input pair on the buffer
is connected to OUT0 of the FemtoClock 2, and the CLK1 input pair is connected to SMAs J46 and J47. By
default, the jumper is on CLK0 for passing OUT0 of FC2 through the buffer. Changing the jumper to CLK1 and

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Apr 21, 2021
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another output can be passed through the buffer by connecting a pair of coax cables from that output to the
buffer input SMA pair.
The CLK0 input is DC coupled to OUT0 on FC2 to demonstrate a connection with minimum components. OUT0
on FC2 must be configured as LVDS for this to work properly. The 8P34S1208I is an LVDS fan-out buffer.
The CLK1 input is AC coupled, using the buffer VREF for DC bias, to make that input compatible with any
differential swing applied to the buffer input SMA pair.
1.5 On-Board Crystal
The evaluation board is assembled with a crystal. The default frequency for the crystal is 60MHz but Renesas
can ship the board with a different crystal frequency to better match the specific application where the
RC32504A will be used. The default 60MHz crystal is best suited for jitter attenuator applications. Synthesizer
applications with output frequencies like 156.25MHz or 312.5MHz work better with a 62.5MHz crystal, or even
better, with a 78.125MHz crystal. The crystal footprint U1 has a universal shape to allow assembly of
3.2 × 2.5 mm and 2.5 × 2.0 mm size crystals.
Figure 9. Crystal and XIN Input
1.6 Bypassing the Fan-Out Buffer at OUT0
Remove R60 and place at R59. Also remove R61 and place R58. The red rectangles are the new positions.
These two resistors are 0Ωand the change will route the OUT0 clock to the J4 and J6 SMA connectors as
opposed to the fan-out buffer input in the R60 and R61 positions.
When the fan-out buffer is not used, it is a good idea to remove jumper J49 (VDDFO) to remove power from the
fan-out buffer.
Figure 10. OE Pin Control

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Apr 21, 2021
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1.7 Setup and Configuration
Complete the following steps to set up the RC32504A / RC22504A EVB using I2C and start the configuration of
the board.
1. Connect J31 to a USB port of the user’s computer using the USB cable supplied with the board.
2. Launch Renesas’ RICBox Software according to the instructions in the FemtoClock 2 RICBox User Guide.
The software and guide are downloadable from the RC32504A product page.
3. Following the “Getting Started” steps in the RICBox Software, an I2C connection is established between the
GUI software and the RC32504A.
4. Open an existing settings file (click Browse) or start a new configuration (click New).
Configurations that were saved recently will show in the “Recent Files” box. Double-click on a file to load the
configuration.
5. When starting a new configuration, the software first needs to know what product family to load the “Virtual
Environment” for:
This screen shows only FemtoClock 2 but it is possible to install multiple Virtual Environments for various
product families. At item 1, select FemtoClock 2 then select the specific product at item 2 and click “OK”.

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6. Select the “Operation Mode”: Synthesizer or Jitter Attenuator.
On the right are explanations and instructions. Click “Next” to go to the next screen.
7. Screen 2 has a list of Jitter Attenuator settings.

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8. Screen 3 sets up the outputs.
a. Fill in the desired output frequencies. Leave blank unused outputs.
b. Click on “Advanced Settings” at the red arrow to select Logic Type and Signal Amplitude.
c. Click “Finish” to end the Wizard and enter the main configuration utility.
9. The main configuration utility.
The buttons on the top left are Control Panel (the above screen), Wizard, Configuration, Registers, and
Block Diagram.
For more information, see the FemtoClock 2 RICBox User Guide located on the RC32504A product page.