Renesas RTKA226110DE0040BU User manual

RTKA226110DE0040BU
Evaluation Board
X0115711 Rev.1.00 Page 1 of 25
Dec.7.20
User Manual
The RTKA226110DE0040BU is a gate drive evaluation board following the GS665XXX-EVBDB daughter board
style and uses the RAA226110 device. This evaluation board consists of two GaN Systems 650V GaN
Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half-bridge gate drivers, isolated
power supplies, and an optional heatsink to form a functional half-bridge power stage. It allows you to evaluate
the GaN E-HEMT performance in any half-bridge-based topology, either with the universal mother board
(GS665MB-EVB) or your own system design. The RTKA226110DE0040BU evaluation board provides a -3V
turn-off voltage solution. A 0V turn-off solution is easy to implement as there is no need for a negative power
supply rail. For Enhancement mode (E-mode) GaN devices, the VGS threshold voltage is 1.7V. To provide
additional noise margin for demanding applications, the RTKA226110DE0040BU board supplies -3V to the
RAA226110 gate driver. Although this increases the body diode reverse conduction voltage drop compared to a
design with a 0V pull-down, it can still be preferred in high power, high-speed gate drive applications.
Read the entire user manual and specifically, the warnings and restrictions notices before handling the product.
Persons handling the product(s) must have electronics training and observe good engineering practice standards.
Features
• Serves as a reference design and evaluation tool in addition to a deployment-ready solution for easy in-system
evaluation.
• Vertical mount style with a height of 35mm that fits in the majority of 1U designs and allows evaluation of a GaN
E-HEMT in traditional through-hole type power supply board
• Current shunt position for switching characterization testing
• Universal form factor and footprint for all products
Related Literature
For a full list of related documents, visit our website:
•RAA226110 device page
Ordering Information
Part Number Description
RTKA226110DE0040BU RAA226110 evaluation board
DANGER!
This evaluation board is designed for engineering evaluation in a controlled lab environment
and should be handled by qualified personnel ONLY. High voltage is exposed on the board
during the test and even brief contact during operation may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized, always wait until all
capacitors are discharged before touching the board.
CAUTION:
This product contains parts that are susceptible to damage by Electrostatic Discharge (ESD).
Always follow ESD prevention procedures when handling the product.

RTKA226110DE0040BU
X0115711 Rev.1.00 Page 2 of 25
Dec.7.20
Figure 1. RTKA226110DE0040BU Evaluation Board Block Diagram
VCC
ENABLE
PWMH
PWML Isolator
IL611-1E
Isolator
IL611-1E
Iso. DC/DC
Iso. DC/DC
RAA226110
Gate Driver
RAA226110
Gate Driver
Q1
Q2
VDC+
VSW
VDC-
C4-10
Shunt

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 3 of 25
Dec.7.20
1. Functional Description
1.1 Control and Power I/Os
The daughter board RTKA226110DE0040BU circuit diagram is shown in Figure 1. The control logic inputs on the
2x3 pin header J1 are listed in Tab le 1.
The three power pins are:
• VDC+: Input DC bus voltage
• VSW: Switching node output
• VDC-: Input DC bus voltage ground return. Note: Control ground 0V is isolated from VDC-
1.2 Using RTKA226110DE0040BU with Universal Mother Board GS665MB-EVB
GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold separately)
that can be used as the basic evaluation platform for all applicable daughter boards.
Table 1. Control Pins
Pin Description
ENABLE Enable input. It is internally pulled up to VCC, a logic low disables all the PWM gate drive outputs.
+5V +5V auxiliary power supply input for logic circuit and gate driver. On the daughter board there are two isolated 5V to 9V
DC/DC power supplies for top and bottom switches.
VDRV Not used. VDRV can be connected to VCC though R43. R43 is DNP by default.
PWMH_IN High-side PWM logic input for top switch Q1. It is compatible with 3.3V and 5V
PWML_IN Low-side PWM logic input for bottom switch Q2. It is compatible with 3.3V and 5V
0VLogic inputs and gate drive power supply ground return.
Figure 2. 650V Universal Mother Board GS665MB-EVB
12V INPUT
(+)
5V Power Supply
CIN
VSW
PWM control & dead
time circuit
Daughter Board
Probing point for VSW
For Ext.
12VDC Fan
Airflow direction
Optional Cout
VDC- VOUT
VDC-
VDC+

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 4 of 25
Dec.7.20
The universal 650V mother board evaluation kit includes following items:
• Mother board GS665MB-EVB
•12V
DC fan
1.2.1 12V Input
The board can be powered by 9V to 12V on J1. The on-board voltage regulator creates 5V for daughter board and
control logic circuits. J3 is used for the external 12VDC fan.
1.2.2 PWM Control Circuit
The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. You can
choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted, controlled
by J7 input) with dead time or external high-side/low-side drive signals from J5 (your own control board).
An on-board dead time generation circuit is included on the mother board. Dead time is controlled by two RC
delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally, two potentiometer
locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time if required.
Figure 3. PWM Control Input and Dead Time Circuit
Figure 4. On-Board Dead Time Generation Circuit
WARNING!
ALWAYS double check the jumper setting and PWM gate drive signals before applying power. Incorrect PWM inputs or
jumper settings may cause device failures
0V
D1 PMEG2005EB
SOD523
R6
1K00
TR12K C11
100pF
0V
R5
1K00
C10
1uF
C9
0.1uF
+5V
J7
112538 1
2 3 4 5
R4
100R
R1206
R2
100R
R1206
U2A
74VHC132
3
1
2
147
0V
R1
49R9
0V
D2 PMEG2005EB
SOD523
TR22K
C12
100pF
0V
U2B
74VHC132
4
5
6
U2C
74VHC132
9
10
8
U2D
74VHC132
12
13
11
TP7
TP8
DNP
DNP
PWM
OUTPUT
INVERTED
PWM OUTPUT
R3
49R9
DNP
DNP
R7
49R9

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 5 of 25
Dec.7.20
1.2.3 Test Points
Test points are designed in groups/pairs to facilitate probing.
1.2.4 Power Connections
The CON1-CON7 mounting pads are compatible with following mounting terminals:
• #10-32 Screw mount,
• Banana Jack PCB mount (Keystone P/N: 575-4)
• PC Mount Screw Terminal (Keystone P/N: 8191)
1.2.5 Output Passives (L and C14)
An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5) or
VDC+ (CON2/3) for double pulse test. You can choose your inductor size to meet the test requirement. Renesas
recommends using a power inductor with low inter-winding capacitance to obtain best switching performance. For
the double-pulse testing use 2x 60µH/40A inductor (CWS, HF467-600M-40AV) in series. C14 accommodates a
film capacitor as an output filter.
1.2.6 Double Pulse Test Mode
The double-pulse test allows evaluation of the device switching performance at high voltage/current without the
need of actually running at high power. It can also be used for switching loss (Eon/Eoff) measurement and other
switching characterization parameter tests.
Table 2. Test Points
Test points Name Description
TP1/TP2 +5V/0V 5V bias power
TP7/TP8 PWMIN/0V PWM input signal from J7
TP4/TP3/TP13 PWMH/PWML/0V High-side/low-side gate signals to daughter board
TP9/TP10 VDC+/VDC- DC bus voltage
TP11/TP12 VOUT/VDC- Output voltage
TP6/TP5 VSW/VDC- Switching node output voltage (for HV oscilloscope probe)
Figure 5. Double Pulse Test Setup
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
LOUT
400V DC
+
VDC+
CON7CON6
VSW
CON5
+5V
0V
PWM
Input
(J7)
VDS
IL
ISW
VGL
+6V
0VVDS
VGL
IL
t0 t1 t2 t3
TON1

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 6 of 25
Dec.7.20
The circuit configuration and operating principle is shown in Figure 5:
• The output inductor is connected to the VDC+.
• At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first pulse TON1
defines the switching current ISW = (VDS*TON1) / L.
• t1-t2 is the free wheeling period when the inductor current ILforces Q1 to conduct in reverse.
• t1 (turn-off) and t2 (turn-on) are of interest for this test because they are the hard switching transients for the
half-bridge circuit when Q2 is under high switching stress.
• Keep the second pulse t2-t3 short to limit the peak inductor current at t3.
The double-pulse signal is generated using a programmable signal generator or microcontroller/DSP board.
Because this test involves high switching stress and high current, Renesas recommends setting the double pulse
test gate signal as a single trigger mode or use long repetition period (for example >50ms-100ms) to avoid excess
stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or INT_INV) and
Q2 is set to INT (or EXT position if the PWM signal is from J5).
1.2.7 Buck/Standard Half-Bridge Mode
1.2.8 Boost Mode
WARNING!
Limit the maximum switching test current to 30A and ensure maximum drain voltage including ringing is below 650V for
pulse testing. Exceeding this limit may cause damage to the devices.
This is a standard half-bridge configuration that can be used in the
following circuits:
• Synchronous Buck DC/DC
• Single phase half-bridge inverter
• ZVS half-bridge LLC
• Phase leg for full bridge DC/DC or
• Phase leg for a 3-phase motor drive
Jumper setting:
• J4 (Q1): INT
• J6 (Q2): INT_INV
vWhen the output becomes the input and the load is attached between
VDC+ and VDC-, the board is converted into a boost mode circuit
and can be used for:
• Synchronous Boost DC/DC
• Totem pole bridgeless PFC
Jumper setting:
• J4 (Q1): INT_INV
• J6 (Q2): INT
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
OUT
400V DC
+
VDC+
CON7
CON6
VSW
CON5
C
OUT
R
Load
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
LIN
VDC+
CON7
CON6
VSW
CON5
INPUT
VIN

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 7 of 25
Dec.7.20
1.3 Using RTKA226110DE0040BU in System
The daughter board allows you to evaluate the GaN performance in your own systems. The footprint drawing of
RTKA226110DE0040BU is shown in Figure 6.
1.4 Quick Start Procedure – Pulses Test
The following equipment and components are required:
• Four-channel oscilloscope with 500MHz bandwidth or higher
• High bandwidth (500MHz or higher) passive probe
• High bandwidth (500MHz) high voltage probe (>600V)
• AC/DC current probe for inductor current measurement
• 12V DC power supply
• Signal generator capable of creating testing pulses
• High voltage power supply (0-400VDC) with current limit.
• External power inductor (recommend toroid inductor 50µH-200µH)
The following are the instructions to quickly get started with your evaluation of the GaN E-HEMT.
1. Check position E (Figure 10) on the daughter board RTKA226110DE0040BU.
2. Install RTKA226110DE0040BU on the mother board. Press all the way down until it clicks. Connect the probe
between TP8 (low-side GaN gate) and TP3 (low-side GaN source) for gate voltage measurement in the
daughter board.
3. Set up the mother board
a. Connect 12VDC bias supply to J1.
b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator, ensure the output
mode is High-Z mode.
c. Set J4 to OFF position and J7 to INT.
d. Set the High Voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect the HV supply
to CON2 and CON6.
e. Use the HV probe between TP6 and TP5 for VDS measurement.
f. Connect an external inductor between CON1 and CON3. Use the current probe to measure the inductor
current, (IL).
Figure 6. Recommended Footprint Drawing of Daughter Board GS665XXX-EVBDB
135
246
7
89
1. All units are in mm.
2. Pin 1-6: Dia. 1mm
3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312 -0-15-15-34-27-10-0.

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 8 of 25
Dec.7.20
4. Set up and check the PWM gate signal
a. Turn on the 12VDC power.
b. Check the two LEDs on the daughter board. They should be turned on indicating the isolated 9V is present.
c. Set up the signal generator as shown in Figure 5 to create the waveforms . Use equation ISW =(V
DS *T ON1)/L
to calculate the pulse width of the first pulse and ensure the ISW_MAX is ≤40A at 400VDC.
d. Set the operation mode to either Single Trigger or Burst mode with a repetition period of 100ms.
e. Turn on the PWM output and check on the oscilloscope to make sure the GaN gate drive voltage waveform
is present and matches the PWM input.
5. Power-on
a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up until it reaches
400VDC. During the ramping period, closely observe the voltage and current waveforms on the oscilloscope.
6. Power-off
a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the output. Then turn
off the 12V bias supply and signal generator output.
Figure 7. Pulses Test Setup Example
VDC+/VDC-
12VDC
PWN In
Inductor

RTKA226110DE0040BU 1. Functional Description
X0115711 Rev.1.00 Page 9 of 25
Dec.7.20
1.5 Test Results
Pulses test (VDS = 400V, IMAX = 33A, LP= 120µH, RG(ON) = 0Ω, IGSEL is connected to VDRV, gate driver current
is 0.3A, RG(OFF) = 1Ω, 8 pulses, period = 4µs, duty = 40%).
Figure 8 shows the hard switching on waveforms at 400V/33A. A VDS dip can be seen because of the rising drain
current (di/dt in the power loop ΔV = LP * di/dt, where LPis the total power loop inductance). After the drain current
reaches the inductor current, the VDS starts to fall. The VGS undershoot spike is caused by the Miller feedback
through Cgd under negative dv/dt.
Because of the low gate charge and small RG(OFF), the GaN E-HEMT gate has limited control on the turn-off
dv/dt. Instead, the VDS rise time is determined by how fast the turn-off current charges the switching node
capacitance (COSS).
The low COSS of the GaN E-HEMT and low parasitic inductance of the GaNPX™ package, together with
optimized PCB layout, enables a fast and clean turn-off. Even with dv/dt greater than 100V/ns, expect only 50V of
overshoot on the turn-off VDS waveform. The measured rise time is 4ns at 400V and 33A hard turn-off.
The OCP setpoint is 40A. Because of ringing on the current sensing signal, the actual OCP trigger point is 33A.
After the OCP occurs, the driver is locked with the Gate pulled low regardless of the PWM input.
Synchronous Buck Test (L = 120µH, VIN = 400V, VOUT = 80V, D = 20%, fSW = 100kHz, POUT = 300W).
Figure 8. 400V/33A Pulses Test Waveform
Figure 9. Buck Test Waveform (POUT = 300W)
Vds_low-side
I_inductor
V_gate
Vds_low Side
I_inductor
V_gate
Vds_L
I_inductor
PWM

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 10 of 25
Dec.7.20
2. PCB Layout Guidelines
2.1 RTKA226110DE0040BU Evaluation Board (Daughter Board)
Figure 10. RTKA226110DE0040BU Top
Figure 11. RTKA226110DE0040BU Bottom
• A: 2x GaN Systems 650V E-HEMT GS66516T, 60A/25mΩ
• B: Decoupling capacitors C14-C17 and C47-C54
• C: Signal isolator IL611-1E
• D: GaN driver RAA226110
• E: OCP shunt
• F: TP1 (gate) and TP4 (source) test points for bottom Q2 VGS
• G: 5V-12V isolated DC/DC gate drive power supply
AB
C
D
E
F
G
Heat Sink Location

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 11 of 25
Dec.7.20
2.1.1 GaN E-HEMTs
This daughter board includes two GaN Systems E-HEMT GS66516T, 60A/25mΩin a GaNPx™ B type package.
The large S pad serves as source connection and thermal pad. Pin 4 is the Kelvin source connection for gate
drive return.
2.1.2 Gate Driver Circuit
The Renesas RAA226110 low-side gate driver is chosen for this design. This driver provides 5.8V gate drive with
3.8V UVLO. It supports the 5.8V turn-on and -3V/0V turn-off. It has separated source and sink drive outputs that
eliminates the need for an additional diode. OCP is also integrated in the driver.
RAA226110 provides configurable source current (0.3A/0.75A/2A) to adjust the slew rate of GS66516T without gate
resistor to minimize the gate loop. The turn off speed can be directly controlled by the gate resistor RG(OFF) (R22).
2.1.3 Gate Drive Power Supply
5V to12V isolated DC/DC converters are used for gate drive. The RAA226110 accepts 4.5V to 18V VDD input voltage.
Figure 12. Package Outline of GS66516T
Figure 13. Gate Driver Circuit
Circuit Symbol
The thermal pad is internally connected to
Source (S pin 3) and substrate
Package Outline
TITLE:
ENGINEER: DATE:
RELEASED BY:
DRAW N
BY:
UPDATED BY: DATE:
DATE:
DATE:
05-27-2020
EVALUATION BOARD
TIM KLEMANN
RAA226110
TENY XU
VSW
VDC-
P
IN
IN
IN
IN
EP
U4
RAA226110
1
FLT
2
EN
3
INB
4
IN
5
IGSEL
6
IDSET
7
ISNSN
8
ISNSP
9
VEEL
10
OUTL
11
OUTH
12
VDRV
13
VEEH
14
VSSP
15
VSS
16
VDD
17
CON3
CON2
C13
1000PF
C16
1000PF 4.7UF
C10
TP10
4.7UF
C11
R22
3.3K
0
R20
0.1UF
TP1
10K R5
D
S
G
GS66516T
Q2
1
2
3
4
R13
5.6
R14
5.6
0.1UF
C7
R7
DNP
TP4
TP3
RSH1
.001
0
R10
.1
RS1
R12
1M
UNNAMED_1_GS66516T_I 229_4
UNNAMED_1_RAA226110_I453_1
UNNAMED_1_RAA226110_I 453_10
UNNAMED_1_RAA226110_I453_5
UNNAMED_1_RAA226110_I453_7 UNNAMED_1_RAA226110_I453_8
VDDLIN
VDRVL
VDRVL
VDRVL
VEELL

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 12 of 25
Dec.7.20
2.1.4 Current Shunt
• The board provides an optional current shunt position E (Figure 15) between the source of Q2 and power
ground return, allowing the drain current measurement for switching characterization tests such as Eon/Eoff
measurement.
• The current shunt also provides the OCP signal for the RAA226110 to trigger OCP. The OCP threshold voltage
40mV/80mV/120mV can be configured through the IDSET pin of RAA226110.
• If a current shunt is not used, position E must be shorted.
Figure 14. Gate Drive Power Supply
Figure 15. Current Shunt Position E
CAUTION:
Check the shunt position E before the first time use. To complete the circuit, position E needs to be either shorted or a current shunt must be
inserted before powering up.
A
A
A
A
A
A
HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
3.3K
R50
3
5
12
4
6
J1
4
2
3
5
6
1
CONN-1X6
J2
R43
DNP
4.7UF
C20
4.7UF
C19
+VO
0V
VIN
GND
NC
PES1-S5-S12-M
U6
1
2
4
5
8
+VO
0V
VIN
GND
NC
PES1-S5-S12-M
U5
1
2
4
5
8
3.3K
R28
3.3K
R29
D4 D3
3.3K
R31
3.3K
R30
4.7UF
C22
4.7UF
C21
1K
R33 D6
1K
R32 D5
C26
4.7UF 4.7UF
C25
4.7UF
C24 C23
4.7UF
TP7
TP5
TP6
TP8
EN
PWMH_IN
PWML_IN
UNNAMED_4_SMLED_I134_B
UNNAMED_4_ SMLED_ I185 _B
VCC
VDDHIN
VDDLIN
VDRV
VEELH
VEELL
Q2 Source
Shunt VDC-

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 13 of 25
Dec.7.20
2.1.5 Measurement with Current Shunt
• When measuring VSW with current shunt, ensure all channel probe grounds and the current shunt BNC output
case are all referenced to the source end of Q2 before the current shunt. The recommended setup of probes is
shown in Figure 16.
• The output of coaxial current shunt can be connected to oscilloscope through a 50Ωtermination impedance to
reduce the ringing.
• The measured current is inverted and can be scaled by using: ID= VID/RSHUNT.
2.1.6 Thermal Design
• GS66516T has a thermal pad on the top-side for heat dissipation.
• A heatsink (35x35mm size) can be attached to the top-side of the board for optimum cooling. Thermal Interface
Material (TIM) is needed to provide electrical insulation and conformance to the top of the GaN device surface.
The daughter board is shipped with a sample 35x35mm fin heatsink (not installed), although other heatsinks
can be used to fit your system design.
• A thermal tape type TIM (Berguist® Bond-Ply 100) is chosen for its easy assembly. The supplied heatsink has
the thermal tape pre-applied so simply peel off the protective film and attach the heatsink to the back of board
as marked in Figure 11.
• Two optional mounting holes as shown in Figure 17 are provided for mounting customized heatsink using screws.
• Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is ~9°C/W with
500LFM airflow.
• Forced air cooling is recommended for power testing.
Figure 16. Recommended Probe Connection with Current Shunt
Figure 17. Daughter Board with Heatsink Attached
CAUTION:
There is no on-board over-temperature protection. Device temperature must be closely monitored during testing. Never operate the board
with device temperature exceeding TJ_MAX (150°C).

RTKA226110DE0040BU 2. PCB Layout Guidelines X0115711 Rev.1.00 Page 14 of 25 Dec.7.20
2.2 RTKA226110DE0040BU Circuit Schematic
Figure 18. Schematic
TITLE:
ENGINEER: DATE:
RELEASED BY:
DRAW N
BY:
UPDATED BY: DATE:
DATE:
DATE:
05-27-2020
EVALUATION BOARD
TIM KLEMANN
RAA226110
TENY XU
VSW
VDC-
LOW VOLTAGE SECTION
HIGH VOLTAGE SECTION
HIGH VOLTAGE SECTION
LOW VOLTAGE SECTION
A
A
HV
HV
HV
HV
HV HV
HV
HV
HV
HV
HV
P
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
EP
U4
RAA226110
1
FLT
2
EN
3
INB
4
IN
5
IGSEL
6
IDSET
7
ISNSN
8
ISNSP
9
VEEL
10
OUTL
11
OUTH
12
VDRV
13
VEEH
14
VSSP
15
VSS
16
VDD
17
C15
0.1UF
C54
0.1UF
EP
U3
RAA226110
1
FLT
2
EN
3
INB
4
IN
5
IGSEL
6
IDSET
7
ISNSN
8
ISNSP
9
VEEL
10
OUTL
11
OUTH
12
VDRV
13
VEEH
14
VSSP
15
VSS
16
VDD
17
CON3
C17
0.1UF
CON2
CON1
C13
1000PF
R2
820
C16
1000PF
C2
16PF
R1
820
4.7UF
C10
C1
16PF
C4
16PF
4.7UF
C9
R4
820
TP10
C3
16PF
R3
820
4.7UF
C11
3.3K
R21
0
R19
GND
IN1+
IN1-
IN2+
IN2-
OUT2
OUT1
VDD
IL611-1E
U2
1
2
3
4 5
6
7
8
GND
IN1+
IN1-
IN2+
IN2-
OUT2
OUT1
VDD
IL611-1E
U1
1
2
3
4 5
6
7
8
4.7UF
C12
D2
RB751V40
D1
RB751V40
R22
3.3K
0
R20
TP9
C6
0.1UF
TP2
0.1UF
C5
TP1
D
S
G
Q1
GS66516T
1
2
3
4
10K R5
D
S
G
GS66516T
Q2
1
2
3
4
R13
5.6
R8 10K
R14
5.6
0.1UF
C7
TP11
R6
DNP
C47
0.1UF
R7
DNP
TP4
TP3
C48
0.1UF
1UF
DNP
C27
0.1UF
C8
C49
0.1UF
DNP
1UF
C14
R9
0
C50
0.1UF
RSH1
.001
0
R10
.1
RS1
DNP
1UF
C18
1M R11
C51
0.1UF
C52
0.1UF
R12
1M
C53
0.1UF
EN
EN
IGSEL1
PWMH_IN
PWML_IN
UNNAMED_1_GS66516T_I226_4
UNNAMED_1_GS66516T_I229_4
UNNAMED_1_I L611_I227_PIN2
UNNAMED_1_I L611_I227_PIN4
UNNAMED_1_I L611_I227_PIN6
UNNAMED_1_I L611_I227_PIN7
UNNAMED_1_I L611_I227_PIN8
UNNAMED_1_I L611_I228_PIN2
UNNAMED_1_I L611_I228_PIN4
UNNAMED_1_I L611_I228_PIN6
UNNAMED_1_I L611_I228_PIN7
UNNAMED_1_I L611_I228_PIN8
UNNAMED_1_RAA226110_I452_1
UNNAMED_1_RAA226110_I452_10
UNNAMED_1_RAA226110_I453_1
UNNAMED_1_RAA226110_I453_10
UNNAMED_1_RAA226110_I 453_5
UNNAMED_1_RAA226110_I453_7 UNNAMED_1_RAA226110_I453_8
VCC
VCC
VDC+
VDDHIN
VDDLIN
VDRVH
VDRVH
VDRVH
VDRVL
VDRVL
VDRVL
VDRVL
VEELH
VEELL

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 15 of 25
Dec.7.20
2.3 RTKA226110DE0040BU Bill of Materials
Qty Reference Designator Description Manufacturer Manufacturer Part
1 SEE LABEL-RENAME BOARD PWB-PCB, RTKA226110E0040BU, REVA,
ROHS
MTL (Multilayer
Pcb International
(HK) Co.LTD)
RTKA226110E0040BURVAPCB
8 C19, C20, C21, C22, C23, C24,
C25, C26
CAP-AEC-Q200, SMD, 0805, 4.7µF, 25V,
10%, X7R, ROHS
TDK CGA4J1X7R1E475K125AC
4 C9, C10, C11, C12 CAP, SMD, 0603, 4.7µF, 10V, 10%, X7S, ROHS Murata GRM188C71A475KE11D
2 C13, C16 CAP, SMD, 0603, 1000pF, 100V, 10%, X7R,
ROHS
Venkel C0603X7R101-102KNE
2 C7, C8 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R, ROHS Yageo CC0603KRX7R8BB104
4 C5, C6, C15, C17 CAP, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS AVX 06035C104KAT2A
4 C1, C2, C3, C4 CAP, SMD, 0603, 16pF, 50V, 5%, C0G/NP0,
ROHS
Yageo CC0603JRNPO9BN160
3 CON1-CON3 CONN-PC PIN, TH, 1.02mmDIA.,
9.04mmLENGTH, GOLD, ROHS
Mill-Max 3620-2-32-15-00-00-08-0
1 J2 CONN-HEADER, 1x6, BRKAWY 1x36,
2.54mm, ROHS
Berg/FCI 68000-236HLF
1 J1 CONN-HEADER, 2x3, BRKAWY, 2.54mm,
TIN, R/A, ROHS
Samtec TSW-103-08-T-D-RA
2 D5, D6 DIODE-ZENER, SMD, 2P, SOD-323, 9.1V, 2%,
300mW, 15Ω, ROHS
ON
Semiconductor
MM3Z9V1ST1G
2 D1, D2 DIODE-SCHOTTKY, SMD, SOD-323, 40V,
120mA, ROHS
Nexperia USA,
Inc
RB751V40,115
2 D3, D4 LED, SMD, 0603, GREEN CLEAR, 2V, 20mA,
574nm, 35mcd, ROHS
Liteon/Vishay LTST-C191KGKT
2 U1, U2 IC-DIGITAL ISOLATOR, SMD, 8P, MSOP, 2-
CHANNEL, 2500Vrms, ROHS
NVE
Corporation
IL611-1E
2 U3, U4 IC-LOW SIDE Gan DRIVER, 16P, QFN, 4x4,
ROHS
Renesas
Electronics
RAA2261104GNP#MA0
2 Q1, Q2 TRANSISTOR-MOS, N-CHNL, 650V, 60A,
SMD, GaNPX-4, ROHS
GaN Systems GS66516T-E02-MR
0 R6, R7, R43 RESISTOR, SMD, 0603, 0.1%, MF, DNP-
PLACE HOLDER
2 R13, R14 RES, SMD, 0603, 5.6Ω, 1/10W, 1%, TF, ROHS Panasonic ERJ-3RQF5R6V
4 R9, R10, R19, R20 RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS Venkel CR0603-10W-000T
2 R5, R8 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Venkel CR0603-10W-1002FT
2 R11, R12 RES, SMD, 0603, 1M, 1/10W, 1%, TF, ROHS Panasonic ERJ-3EKF1004V
2 R32, R33 RES, SMD, 0603, 200Ω, 1/10W, 1%, TF,
ROHS
Venkel CR0603-10W-2000FT
4 R1, R2, R3, R4 RES, SMD, 0603, 820Ω, 1/10W, 1%, TF,
ROHS
Venkel CR0603-10W-8200FT
7 R21, R22, R28, R29, R30, R31,
R50
RES-AEC-Q200, SMD, 0603, 3.3k, 1/10W,
1%, TF, ROHS
Rohm KTR03EZPF3301
1 RSH1 RES-AEC-Q200, SMD, 2512-WIDE, 0.001Ω,
2W, 5%, ROHS
Rohm PML100HZPJV1L0
1 RS1 RES-CURR.SENSE, TH, CYLYNDER, 1
7/8inch, 0.1Ω, 2W
T&M Research
Products Inc
SDN-10
1 HS1 (SEE ASSY
INSTRUCTIONS)
HEATSINK-FAN MNT, SMD, 34.6mm
SQ.x25.4mm, 2 MTG.HOLES, ROHS
Cool Innovations 3-141410UBFABLAN

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 16 of 25
Dec.7.20
2.4 RTKA226110DE0040BU Board Layout
2 HS1 (SEE ASSY
INSTRUCTIONS)
WASHER, 4-40, FLAT, 18-8 STAINLESS
STEEL, ROHS
McMaster-Carr 92141A005
2 HS1 (SEE ASSY
INSTRUCTIONS)
WASHER, 4-40, LOCK, INTERNAL TOOTH,
18-8 STAINLESS, ROHS
Building
Fasteners
INT LWSS 004
2 HS1 (SEE ASSY
INSTRUCTIONS)
NUT, 4-40, HEX, 18-8 STAINLESS STEEL,
ROHS
McMaster-Carr 91841A005
2 HS1 (SEE ASSY
INSTRUCTIONS)
SCREW, 4-40x3/8in, PAN, SS, PHILLIPS Building
Fasteners
PMSSS 440 0038 PH
2 HS1 (SEE ASSY
INSTRUCTIONS)
WASHER-SHOULDER, M3, METRIC,
3.51mm, NYLON, ROHS
Essentra
Components
WS0330A
1 Place assy in bag BAG, STATIC, 4x6, ZIPLOC, ROHS ULINE S-2261
1 HS1-Cut thermal sheet into 1.378
inch squares and place between
heat sink and PCB. Using 4-40
hardware and M3-Metric nylon
washer, attach heat sink to PCB.
Instructions for assembly. Renesas
Electronics
America
Assembly Instructions
1 HS1 (SEE ASSY
INSTRUCTIONS)
INSULATION-BOND-PLY 5mil ADHESIVE
TAPE, ROHS
Bergquist BP100-0.005-00-1112-NA
8 C47, C48, C49, C50, C51, C52,
C53, C54
CAP, SMD, 1812, 0.1µF, 1kV, 10%, X7R,
ROHS
Kemet C1812C104KDRAC7800
0 C14, C18, C27
(2220Y6300105KXTWS2)
DO NOT POPULATE OR PURCHASE
0 TP1-TP11 DO NOT POPULATE OR PURCHASE
2 U5, U6 PWR-SUPPLY, DC/DC CONVERT, SMD,
12.8x8.2, 12V, 1W, 84mA, ROHS
CUI, INC PES1-S5-S12-M-TR
Figure 19. Silkscreen Top
Qty Reference Designator Description Manufacturer Manufacturer Part

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 17 of 25
Dec.7.20
Figure 20. Assembly Top
Figure 21. Top Layer
Figure 22. Layer 2

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 18 of 25
Dec.7.20
Figure 23. Layer 3
Figure 24. Bottom Layer
Figure 25. Silk Screen Bottom

RTKA226110DE0040BU 2. PCB Layout Guidelines
X0115711 Rev.1.00 Page 19 of 25
Dec.7.20
Figure 26. Assembly Bottom

RTKA226110DE0040BU 3. Appendix A - GS665MB-EVB X0115711 Rev.1.00 Page 20 of 25 Dec.7.20
3. Appendix A - GS665MB-EVB
To ensure that you have the latest GS665MB-EVB information, visit the GaN systems Inc website.
3.1 GS665MB-EVB Circuit Schematic
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