Richtek RT8884B User manual

RT8884B
®
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Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Multi-Phase PWM Controller for CPU Core Power Supply
Applications
VR12.5 Intel Core Power Supply
Notebook/Desktop Computer/Servers Multi-phase CPU
Core Power Supply
AVP Step-Down Converter
General Description
The RT8884B is a 4/3/2/1 multi-phase synchronous Buck
controller designed to meet Intel VR12.5 compatible CPU
specification with a serial VID control interface. The
RT8884B adopts G-NAVPTM (Green Native AVP) which is
Richtek's proprietary topology derived from finite DC gain
of EA amplifier with current mode control, making it easy
to set the droop to meet all Intel CPU requirements of
AVP (Adaptive Voltage Positioning). Based on the G-
NAVPTM topology, the RT8884B also features a quick
response mechanism for optimized AVP performance
during load transient. The RT8884B supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8884B to
communicate with Intel VR12.5 compliant CPU. The
RT8884B supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. By utilizing
the G-NAVPTM topology, the operating frequency of the
RT8884B varies with VID, load current and input voltage
to further enhance the efficiency even in CCM. Besides
G-NAVPTM, the CCRCOT (Constant Current Ripple
Constant On Time) technology provides superior output
voltage ripple over the entire input/output range.
Features


Intel VR12.5 Serial VID Interface Compatible


4/3/2/1 Phase PWM Controller


G-NAVPTM Topology


0.5%DAC Accuracy


Differential Remote Voltage Sensing


Built-in ADC for Platform Programming


Accurate Current Balance


System Thermal Compensated AVP


Diode Emulation Mode at Light Load Condition for
Single Phase Operation


Fast Transient Response


VR Ready Indicator


Thermal Throttling


Current Monitor Output


OVP, UVP, OCP, NVP, UVLO


External No-Load Offset Setting


DVID Enhancement


Small 32-Lead WQFN Package


RoHS Compliant and Halogen Free
Simplified Application Circuit
VCORE
PWM3
PWM2
PWM1
RT8884B
PWM4
RT9624A
RT9624A
RT9624A
RT9624A
VR_RDY
VR_HOT
VCLK
VDIO
ALERT
To CPU
To PCH

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Pin Configurations
WQFN-32L 4x4
Ordering Information
Note :
Richtek products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
0F= : Product Code
YMDNN : Date Code
Package Type
QW : WQFN-32L 4x4 (W-Type)
RT8884B
Lead Plating System
G : Green (Halogen Free and Pb Free)
0F=YM
DNN
ISEN1P
ISEN4N
ISEN3N
ISEN3P
DVD
VCLK
TONSET
VR_RDY
VSEN
RGND
VCC
SET1
ISEN2N ISEN2P EN PWM2
IMON
ISEN4P
VDIO
ALERT
FB ISEN1N
SET2 PWM1
VREF VR_HOT
SET3 PWM3
IBIAS PWM4
COMP TSEN
33
24
23
22
21
1
2
3
4
10 11 12 13
31 30 29 28
20
19
5
6
9
32
14
27
18
7
15
26
16
25
17
8
GND
(TOP VIEW)

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Functional Pin Description
Pin No. Pin Name Pin Function
1, 30, 2, 5 ISEN [1:4] P Positive Current Sense Inputs of Channel 1, 2, 3 and 4.
32, 31, 3, 4 ISEN [1:4] N Negative Current Sense Inputs of Channel 1, 2, 3 and 4.
6 IMON CPU CORE Current Monitor Output. This pin outputs a voltage proportional to
the output current.
7 VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
output voltage of IMON pin. Connect a 0.47μF decoupling capacitor between
this pin and GND.
8 COMP CORE VR Compensation. This pin is an error amplifier output pin.
9 FB Negative Input of the Error Amplifier. This pin is for output voltage feedback to
controller.
10 VSEN VR Voltage Sense Input. This pin is connected to the terminal of VR output
voltage.
11 RGND Return Ground for VR. This pin is the negative node of the differential remote
voltage sensing.
12 VCC
Controller Power Supply. Connect this pin to 5V and place a minimum 2.2μF
decoupling capacitor. The decoupling capacitor should be placed to this pin as
close as possible.
13 SET1 1st Platform Setting. Platform can use this pin to set DVID time, RSET, DVID
width and OCS.
14 SET2 2nd Platform Setting. Platform can use this pin to set ICCMAX, QRTH and
QRSET.
15 SET3 3rd Platform Setting. Platform can use this to set output offset voltage.
16 IBIAS
Internal Bias Current Setting. Connect a 100kΩresistor from this pin to GND for
setting the internal current. Don’t connect a bypass capacitor from this pin to
GND.
17 TSEN Thermal Sense Input for CORE VR.
18 VR_HOT Thermal Monitor Output. (Active low).
19 VDIO VR and CPU Data Transmission Interface.
20 ALERT SVID Alert. (Active low)
21 VCLK Synchronous Clock from the CPU.
22 TONSET
On-time Setting. An on-time setting resistor is connected from this pin to input
voltage.
23 VR_RDY VR Ready Indicator.
24 DVD Divided Input Voltage Detection of CORE VR. Connect this pin to a voltage
divider from input voltage of power stage to detect input voltage.
27, 28, 26, 25 PWM [1:4] PWM Outputs for Channel 1, 2, 3 and 4.
29 EN VR Enable.
33
(Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.

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Function Block Diagram
IBIAS
FB
COMP
RGND
PWM4
PWM3
PWM2
PWM1
ISEN4N
Soft-Start & Slew
Rate Control VSET
OVP/UVP/NVP
ERROR
AMP
OCP
From Control Logic
Offset
Cancellation
ISEN4P
ISEN3N
ISEN3P
ISEN2N
ISEN2P
ISEN1N
ISEN1P
Current Balance
To Protection Logic
+
-
+
-
DAC
TON
GEN
+
-
Current mirror
IB1
Current mirror
IB2
Current mirror
IB3
Current mirror
IB4 +
-
OCS
OC
VSEN
IMON VREF
PWM
CMP
QR_TH
QRWIDTH
+
RSET
TONSET
SET2
Loop Control
Protection Logic
SVID Interface
Configuration Registers
Control Logic
UVLO
TON, QR_TH
QRWIDTH
ADC
SET1
IMONI
TSEN EN DVD VCC VR_RDY
GND
MUX
VCLK VDIO ALERT VR_HOT VSEN
+
-
+
-
+
-
To Protection Logic
RSETOCS
1/2
Ai
IB4IB3IB1 IB2
IMON Filter IMONI
SET3
DVID_TH,
DVID_WTH
DVID_TH,
DVID_WTH

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Operation
The RT8884B adoptsG-NAVPTM (Green Native AVP) which
is Richtek's proprietary topology derived from finite DC
gain of EA amplifier with current mode control, making it
easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
The RT8884B adopts the G-NAVPTM controller, which is
one type of current mode constant on-time control with
DC offset cancellation. The approach can not only improve
DC offset problem for increasing system accuracy but also
provide fast transient response. For the RT8884B, when
current feedback signal reaches COMP signal to generate
an on-time width to achieve PWM modulation.
TONGEN
Generate the PWM1 to PWM4 sequentially according to
the phase control signal from the Loop Control Protection
Logic.
SVID Interface/Configuration Registers/Control
Logic
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Loop Control Protection Logic
It controls the power on sequence, the protection behavior,
and the operational phase number.
Current Balance
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the DVD and VCC voltage and issue POR signal as
they are high enough.
DAC
Generate an analog signal according to the digital code
generated by Control Logic.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 0 0 0 0 0 0 00 0.000
0 0 0 0 0 0 0 1 01 0.500
0 0 0 0 0 0 1 0 02 0.510
0 0 0 0 0 0 1 1 03 0.520
0 0 0 0 0 1 0 0 04 0.530
0 0 0 0 0 1 0 1 05 0.540
0 0 0 0 0 1 1 0 06 0.550
0 0 0 0 0 1 1 1 07 0.560
0 0 0 0 1 0 0 0 08 0.570
0 0 0 0 1 0 0 1 09 0.580
0 0 0 0 1 0 1 0 0A 0.590
0 0 0 0 1 0 1 1 0B 0.600
0 0 0 0 1 1 0 0 0C 0.610
0 0 0 0 1 1 0 1 0D 0.620
0 0 0 0 1 1 1 0 0E 0.630
0 0 0 0 1 1 1 1 0F 0.640
0 0 0 1 0 0 0 0 10 0.650
0 0 0 1 0 0 0 1 11 0.660
0 0 0 1 0 0 1 0 12 0.670
0 0 0 1 0 0 1 1 13 0.680
0 0 0 1 0 1 0 0 14 0.690
0 0 0 1 0 1 0 1 15 0.700
0 0 0 1 0 1 1 0 16 0.710
0 0 0 1 0 1 1 1 17 0.720
0 0 0 1 1 0 0 0 18 0.730
0 0 0 1 1 0 0 1 19 0.740
0 0 0 1 1 0 1 0 1A 0.750
0 0 0 1 1 0 1 1 1B 0.760
0 0 0 1 1 1 0 0 1C 0.770
0 0 0 1 1 1 0 1 1D 0.780
0 0 0 1 1 1 1 0 1E 0.790
0 0 0 1 1 1 1 1 1F 0.800
0 0 1 0 0 0 0 0 20 0.810
0 0 1 0 0 0 0 1 21 0.820
0 0 1 0 0 0 1 0 22 0.830
0 0 1 0 0 0 1 1 23 0.840
0 0 1 0 0 1 0 0 24 0.850
0 0 1 0 0 1 0 1 25 0.860
0 0 1 0 0 1 1 0 26 0.870
0 0 1 0 0 1 1 1 27 0.880
Table 1. VR12.5 VID Code Table

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 1 0 1 0 0 0 28 0.890
0 0 1 0 1 0 0 1 29 0.900
0 0 1 0 1 0 1 0 2A 0.910
0 0 1 0 1 0 1 1 2B 0.920
0 0 1 0 1 1 0 0 2C 0.930
0 0 1 0 1 1 0 1 2D 0.940
0 0 1 0 1 1 1 0 2E 0.950
0 0 1 0 1 1 1 1 2F 0.960
0 0 1 1 0 0 0 0 30 0.970
0 0 1 1 0 0 0 1 31 0.980
0 0 1 1 0 0 1 0 32 0.990
0 0 1 1 0 0 1 1 33 1.000
0 0 1 1 0 1 0 0 34 1.010
0 0 1 1 0 1 0 1 35 1.020
0 0 1 1 0 1 1 0 36 1.030
0 0 1 1 0 1 1 1 37 1.040
0 0 1 1 1 0 0 0 38 1.050
0 0 1 1 1 0 0 1 39 1.060
0 0 1 1 1 0 1 0 3A 1.070
0 0 1 1 1 0 1 1 3B 1.080
0 0 1 1 1 1 0 0 3C 1.090
0 0 1 1 1 1 0 1 3D 1.100
0 0 1 1 1 1 1 0 3E 1.110
0 0 1 1 1 1 1 1 3F 1.120
0 1 0 0 0 0 0 0 40 1.130
0 1 0 0 0 0 0 1 41 1.140
0 1 0 0 0 0 1 0 42 1.150
0 1 0 0 0 0 1 1 43 1.160
0 1 0 0 0 1 0 0 44 1.170
0 1 0 0 0 1 0 1 45 1.180
0 1 0 0 0 1 1 0 46 1.190
0 1 0 0 0 1 1 1 47 1.200
0 1 0 0 1 0 0 0 48 1.210
0 1 0 0 1 0 0 1 49 1.220
0 1 0 0 1 0 1 0 4A 1.230
0 1 0 0 1 0 1 1 4B 1.240
0 1 0 0 1 1 0 0 4C 1.250
0 1 0 0 1 1 0 1 4D 1.260
0 1 0 0 1 1 1 0 4E 1.270
0 1 0 0 1 1 1 1 4F 1.280

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 0 1 0 0 0 0 50 1.290
0 1 0 1 0 0 0 1 51 1.300
0 1 0 1 0 0 1 0 52 1.310
0 1 0 1 0 0 1 1 53 1.320
0 1 0 1 0 1 0 0 54 1.330
0 1 0 1 0 1 0 1 55 1.340
0 1 0 1 0 1 1 0 56 1.350
0 1 0 1 0 1 1 1 57 1.360
0 1 0 1 1 0 0 0 58 1.370
0 1 0 1 1 0 0 1 59 1.380
0 1 0 1 1 0 1 0 5A 1.390
0 1 0 1 1 0 1 1 5B 1.400
0 1 0 1 1 1 0 0 5C 1.410
0 1 0 1 1 1 0 1 5D 1.420
0 1 0 1 1 1 1 0 5E 1.430
0 1 0 1 1 1 1 1 5F 1.440
0 1 1 0 0 0 0 0 60 1.450
0 1 1 0 0 0 0 1 61 1.460
0 1 1 0 0 0 1 0 62 1.470
0 1 1 0 0 0 1 1 63 1.480
0 1 1 0 0 1 0 0 64 1.490
0 1 1 0 0 1 0 1 65 1.500
0 1 1 0 0 1 1 0 66 1.510
0 1 1 0 0 1 1 1 67 1.520
0 1 1 0 1 0 0 0 68 1.530
0 1 1 0 1 0 0 1 69 1.540
0 1 1 0 1 0 1 0 6A 1.550
0 1 1 0 1 0 1 1 6B 1.560
0 1 1 0 1 1 0 0 6C 1.570
0 1 1 0 1 1 0 1 6D 1.580
0 1 1 0 1 1 1 0 6E 1.590
0 1 1 0 1 1 1 1 6F 1.600
0 1 1 1 0 0 0 0 70 1.610
0 1 1 1 0 0 0 1 71 1.620
0 1 1 1 0 0 1 0 72 1.630
0 1 1 1 0 0 1 1 73 1.640
0 1 1 1 0 1 0 0 74 1.650
0 1 1 1 0 1 0 1 75 1.660
0 1 1 1 0 1 1 0 76 1.670
0 1 1 1 0 1 1 1 77 1.680

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 1 1 1 0 0 0 78 1.690
0 1 1 1 1 0 0 1 79 1.700
0 1 1 1 1 0 1 0 7A 1.710
0 1 1 1 1 0 1 1 7B 1.720
0 1 1 1 1 1 0 0 7C 1.730
0 1 1 1 1 1 0 1 7D 1.740
0 1 1 1 1 1 1 0 7E 1.750
0 1 1 1 1 1 1 1 7F 1.760
1 0 0 0 0 0 0 0 80 1.770
1 0 0 0 0 0 0 1 81 1.780
1 0 0 0 0 0 1 0 82 1.790
1 0 0 0 0 0 1 1 83 1.800
1 0 0 0 0 1 0 0 84 1.810
1 0 0 0 0 1 0 1 85 1.820
1 0 0 0 0 1 1 0 86 1.830
1 0 0 0 0 1 1 1 87 1.840
1 0 0 0 1 0 0 0 88 1.850
1 0 0 0 1 0 0 1 89 1.860
1 0 0 0 1 0 1 0 8A 1.870
1 0 0 0 1 0 1 1 8B 1.880
1 0 0 0 1 1 0 0 8C 1.890
1 0 0 0 1 1 0 1 8D 1.900
1 0 0 0 1 1 1 0 8E 1.910
1 0 0 0 1 1 1 1 8F 1.920
1 0 0 1 0 0 0 0 90 1.930
1 0 0 1 0 0 0 1 91 1.940
1 0 0 1 0 0 1 0 92 1.950
1 0 0 1 0 0 1 1 93 1.960
1 0 0 1 0 1 0 0 94 1.970
1 0 0 1 0 1 0 1 95 1.980
1 0 0 1 0 1 1 0 96 1.990
1 0 0 1 0 1 1 1 97 2.000
1 0 0 1 1 0 0 0 98 2.010
1 0 0 1 1 0 0 1 99 2.020
1 0 0 1 1 0 1 0 9A 2.030
1 0 0 1 1 0 1 1 9B 2.040
1 0 0 1 1 1 0 0 9C 2.050
1 0 0 1 1 1 0 1 9D 2.060
1 0 0 1 1 1 1 0 9E 2.070
1 0 0 1 1 1 1 1 9F 2.080

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 0 1 0 0 0 0 0 A0 2.090
1 0 1 0 0 0 0 1 A1 2.100
1 0 1 0 0 0 1 0 A2 2.110
1 0 1 0 0 0 1 1 A3 2.120
1 0 1 0 0 1 0 0 A4 2.130
1 0 1 0 0 1 0 1 A5 2.140
1 0 1 0 0 1 1 0 A6 2.150
1 0 1 0 0 1 1 1 A7 2.160
1 0 1 0 1 0 0 0 A8 2.170
1 0 1 0 1 0 0 1 A9 2.180
1 0 1 0 1 0 1 0 AA 2.190
1 0 1 0 1 0 1 1 AB 2.200
1 0 1 0 1 1 0 0 AC 2.210
1 0 1 0 1 1 0 1 AD 2.220
1 0 1 0 1 1 1 0 AE 2.230
1 0 1 0 1 1 1 1 AF 2.240
1 0 1 1 0 0 0 0 B0 2.250
1 0 1 1 0 0 0 1 B1 2.260
1 0 1 1 0 0 1 0 B2 2.270
1 0 1 1 0 0 1 1 B3 2.280
1 0 1 1 0 1 0 0 B4 2.290
1 0 1 1 0 1 0 1 B5 2.300
1 0 1 1 0 1 1 0 B6 2.310
1 0 1 1 0 1 1 1 B7 2.320
1 0 1 1 1 0 0 0 B8 2.330
1 0 1 1 1 0 0 1 B9 2.340
1 0 1 1 1 0 1 0 BA 2.350
1 0 1 1 1 0 1 1 BB 2.360
1 0 1 1 1 1 0 0 BC 2.370
1 0 1 1 1 1 0 1 BD 2.380
1 0 1 1 1 1 1 0 BE 2.390
1 0 1 1 1 1 1 1 BF 2.400
1 1 0 0 0 0 0 0 C0 2.410
1 1 0 0 0 0 0 1 C1 2.420
1 1 0 0 0 0 1 0 C2 2.430
1 1 0 0 0 0 1 1 C3 2.440
1 1 0 0 0 1 0 0 C4 2.450
1 1 0 0 0 1 0 1 C5 2.460
1 1 0 0 0 1 1 0 C6 2.470
1 1 0 0 0 1 1 1 C7 2.480