Roland CR-5000 Operating and maintenance manual

DEC.8,1981 CR-5000/8000
CR-5000/8000 service notes
SPECIFICATIONS First Edition
Second Printing (July 12, 1983 E2)
OUTPUT IMPEDANCE Less than 6Kfi or less than 25Kft (Serial No. CR5000 091100-, CR8000 090900-)
TRIGGER OUT Level: +5 positive edge
Width: 44ms (typ) @TEMPO min./12ms (typ) @TEMPO max.
OUTPUT (max.) 4Vpp @VOICE LEVEL max./VOLUME max./ACCENT min. (16V p-p <g> ACCENT max.)
(into 100KS1) 2.5Vp-p @VOICE LEVEL mid./VOLUME mid./ACCENT mid.
(CR8000)
SYNC IN +15V(max.)
SYNC OUT +15V (Tempo clock -6.7ms-71ms)
POWER CONSUMPTION ...CR5000: 10W, CR8000: 12W
DIMENSIONS 331 (W) x278(D) x108(H)mm
WEIGHT '3.7kg
NOISE 0.3mV rms (-68dB) (OdB =0.775V)
(load lOOkH) (DIN 45405 wtd)
Button
N-523(2247052300)
Button
N-516( 2247051600)
Button
N-517(2247051700)
Buttons
*N-520(2247052000)
Switch
SRM1026K15
(13119508)
Knob
** CR-5000
*CR-8000
Switch
*SRM101CY15( 13H9806)
l*SRM1018K15( 13119704)
*7-segment LED
TLR312 (15029125)
Display window
2222030200
Pot
EVHRRA361B14 (13219229
)
Knob N-165(2247016500)
Panel
•2221027200
2221026000
Button N-517 (2247051700)
LED ***n
GL-3PG2 (15029112) ^0>
N-128(2247012800) ALL KEYBOARD SWITCHES: KEHlCf
rnnn Ti.in- .m*x huo

CR-5000/8000
.J !i
?*•: CIN
anx.
CIH
OUT
AMTI UD§
Of2,Ql3
BUFTB
CMO
BUFFS
Q9
«| vco
ICI6.0II
DIVIDER
ICI5
V
8UFFB!
Q5
T.FF-
ICI5
one
SHoT
OU.*49
ECI&
_T
8UfK»
gwS
BuffB<
QI5
CPU
CLOCK
16HH,)
auFfts
RJFW
03
0H£
SHOT
C47 RS9
1CI6
JT
4>"C
BufTER
IC7
icn
:ci2
T.
T,
X'TAL
DB
APDRESS
CPU
LC10
INT RD >-
WR >-
P27 —
PORT
RKET
PDWEK SUPPLY —•5
—-15
ADDRES5
6us ^r
HRam %
WE M>
DATA BUS
&
ttSET
Q1.02
^S
LATCH
IC 1
o
&i>
LATCI
IC2
V\Y \\
DECOCeR
re 6
RAM BACKUP
ji'l'lT^
CPU B0>
$»
CoN-
TKXLIft
337
V
GATE
G20 »BUFFtK
a18
BPF
ICI3 MPF
G22 (accent) '

(9 20 21 22 23 24 25 26 27 2B QDEC.8,1981
VBOARD CONTROL BOARD IfLED BOARD j
cose _^CW«fL
IC3I|D3l.g|
vcosc
LCOSC[_
IC9
/""CONQA
VLEVEo
MIA
IC8
[CB>— ENVELOPE
03 -i
I
CB0SC1
IC4
GATE
©4
I
1
CB 0SC2J
IC4
SATE
Q5
BPF
IC5 cCB. CLAVES N
LEVEL /
MIX
ACCENT
UKVCU
CR-8000
BLOCK
DIAGRAM

\h£>— HC OSC cwmK
021.32
\^>-
©H
MCOSC
:c<?
LCOSC
IC9
ILEVEL )
ENVELOPE
03I
--M^>-»<Th CBOSCt I&ATE _
US^ 1
IC4 IL*iJ L
GATE
©4
CB OSC?
IC4
X
SATE
Q5 LP BPF
ICS
ACC
001,025 "® (volume )
CU4VES
osc
aa.Q<?
cCB.CLAVES
LEVEL .
MIX
IC5
(accent)
icr
M'JTINlG
AM. 31. 32 /PROGRAM "\
VMODE )
&>~ REVERB
fNVELOPE
Q40.P4-I
ACCINT
HOLDER
SAWTOOTH
ewelope
Ki6,aJ3
GATE
*2<?
VCA <&
I00"
aINSTRUMENT
SELECTOR
/HCP \
ILEVEL J
VOICE GENERATOR BOARD
CR-80<
BLOCI
DIAGR

.8,1981
s
T
a
cpu re
cpu rd
A0
uWRITE U~LT READ i_r
CPU BOARD
IC1 LATCH CPU ROARD
IC2 LATCH COTROL BOARD
IC1, 2

CR-5000/8000
9
li? 20 21 22 23 24 25 26
CPU BOARD
aic2, pin 12 Inr
BCPU BOARD
IC10, Pin 8
CPU BOARD
-1 cycle -
IC6, Pin 5
uir
ur
CPU BOARD ._, ,_, „_,, ,„_
ic6 -^«^jTirinriTL
CPU BOARD
IC6, Pin 3
CPU BOARD
IC6, Pin 2iun
ur
CONDITION
PANEL CONTROLS
BANK 1LED "ON"
(ALL THE REMAINDERS "OFF")
(or PCWER ON, RHYTHM STOP)
Fig. 2
CIRCUIT DESCRIPTION
SWITCH SCANNING
CPU holds one of switch matrix rows low through LATCH IC1 and DECODER IC6.
Exp. When Sll closes while pin 4of IC6 (B in Fig. lj is held low, pin 14 of BUFFER
IC1 (A in Fig. 1) which is pulled up via Rl ,becomes low. This low is read by CPU
through data bus.
CPU continues this sequence for the remaining 7matrix rows ((|), Fig. 2).
Once rhythm starts, time interval between switch scanning varies to Tempo Clock rate.
LED DINAMIC SCANNING
To light LED that is on, CPU selects matrix row and column where the LED is connected
diagonally.
In the above example Dll has been on, CPU fires LED driver Ql through LATCH IC2 in
sympathy with low at B in Fig. 1((a) and (5) in Fig. 2.)
Lengths of lows and intervals between lows in Fig. 2ulso vary greatly with controls
setting and rhythm tempo.
VOICE TRIGGER SIGNAL
CPU delivers trigger signals (negative going") to individual VOICE Generators.
Trigger signal goes negative at the falling edge of tempo clock and stays low until
the next falling edge of the tempo clock. That is, width of trigger signal is equal
to period of one clock signal. The maxima trigger signal rate is 24 clocks :(J>
)
.
EXT TRIGGER Derived from LATCH IC1 on CPU board, "hey are also negative going
and the pulse width is equal to that of tempo clock.
RESTART
CPU reads INT terminal (not in use for interrupt application) every 3ms and ,when
INT is high, resets internal counter to revert to onset of ameasure.
Tf monost.able (1/6IC6. C47 and RS9) output is high for aperiod shorter than 3ms or

CR-
)E GENERATORS
tvoice generators are designed based on afashion
ilar to those detailed in the circuit description
the TR-808 Service Notes which is expected to be
srenced to as necessary. Exceptions are Cymbal and
Shot. Below brief comments on individual voices.
circuit consists of two bridged-T networks,
CB
Two oscillator outputs of
frequency are summed at B'.
gated at choppers.
HCP
HCP sound is accomplished
lating white noise with ss
waves derived from IC6.
ohas two bridged-T filters for drum sound, in
Ltion, noise generator for snare sound.
IT:
Iged-T networks in these stage include two diodes
:heir RC constant loop. The diode changes con-
sing rate in proportion to sound amplitude passing
)ugh the network, changing filter characteristic,
3shifts filter response curve (frequency) along
id contour. Pink noise is combined with this out-
to simulate reverbration.
1C. HC
)based on Bridged-T. HC output is clamped on D31
D32 to have multiple harmonics to emphasis highs.
)HH. CY
combined square waves from Shmitt triggers
are gated at choppers with the contour
oed by respective envelop generator outputs.
RAM
CR-8000 only
DB
ALE
ICIO
RS
P27
RESET
DATA BUS 81 1
<>^2
IC9
LATCH
IC8 IC1
1
JADDR2S3 1
t
_1
RAM
IC5 I/O
V."R CZ -
1. .
I,
K
•"Y >— L/3IC3
RESET
lg six Schmitt triggers, two are used which
reset by an RS trig fed through Q37. The
:t rising edge of two outputs are synchro-
id to each other to eliminate unsavory sound
;he very first of RS note.
NOTES:
P27 -high during RAK access iny
CE -high during power off

CR-5000/8000 DEC.8,1981
outputs of different
summed at BPF after
;rs.
:complished by modu-
>ise with sawthooth
'rom IC6.
ACCENT
Sounds passing through VCA IC7 are
accentuated simaltenously when an
accent pulse is applied to Q41 with
its amplitude determined by VR8
setting.
C(CLAVES)
The circuit is designed based on conventional R-C
phase oscillator.
-G-
8x
IC1
iJJ
I/O
I
CFO RD
CPU WR
RAK CE —
•1 0.5-0.6sec
uu
RAK VR .~LT
arrrox. Ies
"LT JZZZ
_jri ',—
'
L-<»-ii|«r-n
rower ON o
Power CFF
RESET
RAK accessing
power off
Storage for programmed rhythm patterns are provided
for the CR-8000. The memories are maintained by
backup batteries (three 1.5V dry cells).
The ten address bits are required to access to a
memory location on 1024 words by 4bit RAM uPD444;
8bits are latched into IC8 by ALE and 2bits into
IC1 (also used for switch scanning).

DEC.8,1981
//PD8049C/^PD8048C
SINGLE COMPONENT 8-BIT MICROCOMPUTER
Top View)
^>r
XTAL 2o-
RESET O-
SS O-
Int O-
£A ©-
RD O-
PSEN O
WR O
(OV) V,s o
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
-0 Vcc(*5V)
-O Tl
-O P27
-O P26
-O P25
8049
2Kx8 ROM
128x8 RAM
8048
1Kx8 ROM/EPROM
64 x8RAM
-5V)
-O PROG
-O P23
-O P2«
-O P21
-O P20
//PD8049C
BLOCK DIAGRAM
PIN NAME PIN NO. FUNCTION
T0 1TEMPO CLOCK IN
Tl 39 START/ST0F SIGNAL IN
IKT 6RESTART SIGNAL IN
DATA BUS 12-19 SWITCH SCANNING OUT/IN
LEDs LIGHT OUT
TEMPO LED, TRIG OUT
MEMORY READ/WRITE (CK-S000 only)
PORT 1TRIGGER OUT FOR VOICE GENERATOR
P10
Pll
P12
P13
P14
P15
P16
P17
27
28
29
30
31
32
33
34
CYMBAL
HI TOM
OPEN HI-HAT
LOW TOM
HI-HAT
SNARE DRUM
BASS DRUM
ACCENT
FORT 2TRIGGER OUT FOR VOICE GENERATOR
P20
P21
P22
P23
P24
P25
!??
21
22
23
24
35
36
37
HI CONGA
KIDDLE CONGA
LOW CONGA
COWBELL
CLAVES
RIM SHOT
HAND CLAP
8048
»4«wonos
PROGRAM
MfUOMV
7S
8049 WtttrOAOS
OAtA
MlMOAV
T>
\Z
»6lT
TiMCR/
IVINT COUNTCM
<z
UPD8049C-159
UPD8049C-232 (improved
version)
The following program bug
is eliminated in the -232
version.
Condition
SHUFFLE ON with alternate
rhythm patterns selected.
INTRO/FILL IN is pushed
after the termination of
first measure pattern.
When INTRO/FILL IN part
ends, CPU delivers rhythm
pattern data for the first
measure but replaces the
first step data only with
the one for the second
measure
.
This is perceptive in
RHUMBA. BEGUINE or

^PD8048C CR-8000only
PIN NAKE
T0
Tl
INT
DATA BUS
PIN NO.
39
PORT 1
?10
Pll
P12
P13
?14
P15
P16
?17
12
13
14
15
16-19
rUKCTION
NO APPLICATION (KEPT LOW)
TEMPO CLOCK IN
START/STOP SIGNAL IN
POST 2
P20-P23
P24
P25
?26
P27
27
28
29
30
31
32
33
34
KEPT HIGH
KEPT LOV
KEPT LOV
KEPT LOV
NO CONNECT ION
for Internal
program
initialization
21-24
35
36
37
35
7-SEGMENT LED LIGHT
SIGNAL OUTPUTS
NO CONNECTION
NO CONNECTION
(NOT IN USE)
7-SE3KENT LED
CONTROL SIGNAL
OUTPUT
CR-5000/8000
TEMPO DISPLAY (CR-8000 only)
UPD8048C IC3 on Control Brd counts
Tempo Clocks derived from Q9 on
CPU Brd whenever power is being
fed to the CR-8000.
Since 24 tempo clocks are made
equal to one J, actual tempo dis-
played is
clocks per minute
24
CPU performs an equivalent eq
.
in ashort period and drives
Q18-Q20 on Control Brd in syn-
chronous with drive signals for
7segments of display LEDs.
Upon rhythm running INT of CPU
IC3 goes and stays negative with
which CPU's internal count gate
is disabled, then re-started
at the first falling edge of the
next tempo clock. This count
break allows CPU to skip tran-
sitional tempo clock that is
reset by astart signal.
If INT remains high after
rhythm running, tempo display
varies temporarily.

i>
CONTROL BOARD
SYNC
IN /OUT
1.START/ STOP
2. Gnd
3. tempo clock
4. NC
5. NC
<&-@>
JK4
INTRO^
•'FU-UN,
JK2
START>
"STOP
JK3
RESTART
JK5
REGISTER
JK1
OUTPUT
""J
*
3JK6
TRIGGER
OUTPUT
100 V
117 V
220v.240v
240 v3P
FiF2
jumper
CEE tia CEE T4(X
CEET40C
REFER TO CR-500C CKT
FOR AC WIRINGS.
Y1
CPU BOARD GL 3125-060
IC 1.2.8: DM7ALS273
IC3.4 :HPI4023BP
ICI6: HP 14584 BP Q1.7.8.11 14 15 "2SA73.3CP)
Q2-6.9.10.12 13: 2SC9451P;
IC 7. 11.12 :HPI40.SO.BP Q16 :2SB596(o)
s^*/\r»<

CR-5000/8000
.0 21 22 23 24 25 26 27 26 29 DEC.8,1981
F2 F3
jmper
:E T400mA CEE T400mA
:E T400mA CEE T400mA
Sec. Wirings Ratings (DC) :+23V @120mA, 10V @700mA
CKT DIA
ICI3
7805
1000-.T- ~TC72 JC24-T- X"V/
*W l-'r 1-'»j 1^»
77
IC9 jal
,—Wv-
vr
f5
<s—
©
GND
fl5
A--®
V.G. BOARD
..-IS
IC8
LS273
i—Wv-
i—yw—
—W-
.JT At
<*" IC5
/« ?6
M
/U PD444C I
AgtoAi^ ;/ I
tS
R6i Irs
IOK> >IOK
>CK
S±$A •% re 4
IC1
LS273 V«:
cTK
IC2
LS273 «<:
'S /& ni
+s
GNDPIO
Cl
.
3,-V _R40 4.7k «8
€X5XIXzXaX2> CONTROL BOARD JL
later products 15V p-p
w/ slight modifications v 44>«S CTEMPO WIN)
l2mS(TEMPD MAXJ
I(P)
45(P) CR-8000 CPU

€C.8,1981
TEMPO

121 22 23 24 25 26 27 28 29 3G 3s
TEMPO ADJ.
2SC 745 P
2SA 733 P
0.1 rFCeramic
CZD O-V7Mylar
*._„„-> IS 2473
DS442 or ,51588
Posistor ERS-C33G561
CJCeramic Resonqtor
Resistor Array
R40, RA1 R52 R53
3QI6 O
JQI7 o
JIC13 O
CR-5000/8000
:>-r ^c -c-o
CR-8000
CPU BOARD
GL3125-060
(731250600)
(pcb 2291046401)
CHANGES IN COMPONENTS
Ensure trigger outputs
at IC1 when low Vqh
LS273 is used.
R47 47k to 10k
R48 47k to D6
Rl 10k to 27k
R61 10k to 27k
R60 10k to 27k
IQOv .I17v

567691C n\2 12 14 15
CONTROL BOARD GL31 25-090 (731 2509008) (pcb 2291
n
.****
*»*!*
LED BOARD
(7312511001)
(pcb 2291046600)
®©
M*x (nny
I5.3
I-8-
LED BOARD
on early products
pcb 2291046600
r
without underscore
Pattern cuts. Jumpers

CR-5000/8000
21 22 23 24 25 26 27 28 29 30 i
1046501) Ser'al Number 14265 and higher
(Viewed from the rear)
DEC.8,1981
>Vj «JJ
Refoer to p.16 for
pcb 2291046500:
surface mounting
jumper wire.
CE3C '.II mr-yl£-—"-»y
CR-8000
ns3°
J—US31
VJ^^« .« .* i
AD1
rr
ANODE
-(E> :PS 44-2 or \SIS8S .1S24-73
Q:2SA733P »r 2SA1QISGR
QD :2SA937 Q
CD :2SC2021 R
CJLU :CERAMIC RESONATOR (6. MHz) FCR-6
(<D) :LED GL-3PR2 CRED)
LED GL-3PQ2 CQRM)

2O*y 1U n\jl \o l<+ 10 IC i/ 10
B
w
1
DB7 47 o
o
DBS 4.Q oi
\3
n
o
Q
R
T
Tl
53^
50°-
49°,
48;
33°
34 o
35o
37 <^
36
\
ci
lZk
46
-39 XR3
10 k
REGISTER J°"£7 L
ic
Z^J-
:P-
i±_
I3_
.';( :!;i :
:;! hi
o
.o
o
±*
*.7kX8
1!
3
Cwio mil
w>o <n'i
2I
^'ttt:: :: ::
64 Q-
57
5p
*id ujid «; id r~id Mid jid Ojd —.<,
RHYTHM BANK
^* in ^o r-
QQOQ
GDOIX® GDQGDGDQQQ0 (
PRESET
CO or O—
——cw oi
Qoaa
b4ZU RI7 4
v*. 1
—
Yi /
'—• BIB IN—J.
CONTROL BOARD
GL3125-090
4*+iRI8
33 K-& TEMPO LAMP
470 RI4
-Wt-
(O
R2I
IOU i*•<:
J+sv
IST3. 100/6.5
C7
D3I 1»
BEAT LAMP
CLOCK >
START/STOP 5-
1C1.1C2. :HDI4-S03BP
VR II0k8
(TEMPO
CONTROL
10
11
0.1 —aio
:
2SA733-P ot- 2SAI0I5-&R
0.11 ~ai7
:
2SA<?37-&
0I8~ 0-20: 25C202I-R
LED Dl~ D30.32 :(RED) GL-3AR2
led: 031 :(GRN) (JL-3PG2
D33--D83 :IS24-73 or (SIS88 or DS-442
-1_ CERAMIC RESONATOR :(6.0MHi) FCR-6/TDK.
CPU BOARD
CHANGES IN RESISTANCE With Serial Number 090900 and up
The changes eliminates possible dim lighting of LEDs due to insuffi
at IC1 or IC2 on CPU board:
R38-R45: 27k to 10k R17, R19: 47k to 10k
Resistor Array R46: 27k to 3- 3k R18, R20: 47k to 3

19 20 21 22 23 24 25 26 27 CR-5000/8000
29 30 o»o<.
:: :r .
j* Si* Sc scsf
*rt »o */i "o v> 1,
OhjO 00
:: ::
w> *o w> 'o U) •'
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PR06RAM
if in
rn rg
aOS
QDin ,o
aa
>000Q0QQQ Q00000Q0 0'
lO UJlo Irt lo
r- oi ir 2
aoaa
:r:::^::r:::!::
4in 4r< et g* o
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01
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56
^
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CD
<
CD
CO
OC
O
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as.
CD
UJ
o
CD
£
LED BOARD
0P3125-110
"ficient Hlevel output
33k CR-8000 CONTROL

VOICE GENERATOR £