Ronetix PEEDI User manual

PEEDI
Powerful Embedded Ethernet Debug Interface
User’s Manual
Version 3.0

February, 2019
Ronetix has made every attempt to ensure that the information in this document is accurate and
complete. However, Ronetix assumes no responsibility for any errors, omissions, or for any
conse uences resulting from the use of the information included herein or the e uipment it
accompanies. Ronetix reserves the right to make changes in its products and specifications at any
time without notice. Any software described in this document is furnished under a license or non-
disclosure agreement. It is against the law to copy this software on magnetic tape, disk, or other
medium for any purpose other than the licensee’s personal use.
Ronetix Development Tools GmbH
Hirschstettner Str.19/Z110
1220 Vienna
Austria
Tel: [phone]
Fax: [phone]
Web: www.ronetix.at
E-Mail: [email protected]
Acknowledgments:
ARM, ARM7, ARM9, ARM11, Cortex-M, Cortex-A and Thumb are trademarks of ARM Ltd.
PowerPC and ColdFire are trademarks of Freescale Ltd.
Blackfin is trademark of Analog Devices Ltd.
Windows, Win32, Windows CE are trademarks of Microsoft Corporation.
Ethernet is a trademark of XEROX.
MIPS is a trademark of MIPS Technologies.
AVR32 is a trademark of Atmel.
All other trademarks are trademarks of their respective companies.
Copyright© 2005-2021 Ronetix Development Tools GmbH

Table of Contents
PEEDI...................................................................................................................................................1
Powerful Embedded Ethernet Debug Interface....................................................................................1
1 Introduction......................................................................................................................................11
1.1 PEEDI in the development process.........................................................................................12
1.1.1 Single developer environment.........................................................................................12
1.1.2 Multiple developers environment....................................................................................13
1.2 PEEDI in the manufacturing process.......................................................................................13
1.2.1 PEEDI as a standalone FLASH programmer...................................................................14
1.2.2 PEEDI as a device tester..................................................................................................15
1.2.3 High productivity with the Multi Program feature..........................................................15
2 Installation.......................................................................................................................................15
2.1 Hardware installation...............................................................................................................16
2.1.1 Connection instructions....................................................................................................16
2.2 Software installation................................................................................................................18
3 Using PEEDI...................................................................................................................................18
3.1 PEEDI interface.......................................................................................................................18
3.2 Setup with RedBoot.................................................................................................................19
3.2.1 RedBoot Configuration....................................................................................................20
3.3 Firmware update procedure.....................................................................................................21
3.3.1 Update via RS232............................................................................................................22
3.3.2 Update via Ethernet..........................................................................................................22
3.4 RedBoot commands used with PEEDI....................................................................................24
update...................................................................................................................................24
config....................................................................................................................................25
memtest................................................................................................................................25
3.5 Configure PEEDI.....................................................................................................................26
3.5.1 Network configuration.....................................................................................................26
3.5.2 Target configuration file...................................................................................................26
Section LICENSE.................................................................................................................27
Section DEBUGGER...........................................................................................................27
PROTOCOL....................................................................................................................27
REMOTE_PORT.............................................................................................................28
FLASHn...........................................................................................................................28
Section TARGET..................................................................................................................28
PLATFORM....................................................................................................................28
Section PLATFORM_xxx - parameters for all targets with JTAG interface.......................29
JTAG_CHAIN.................................................................................................................29
JTAG_TDO_DELAY......................................................................................................29
TRST_TYPE...................................................................................................................29
RESET_TIME.................................................................................................................30
RESET_TYPE.................................................................................................................30
WAKEUP_TIME.............................................................................................................31
TIME_AFTER_RESET...................................................................................................31
DBGREQ_OUTPUT.......................................................................................................31
COREn.............................................................................................................................31
COREn_STARTUP_MODE............................................................................................32
COREn_INIT...................................................................................................................32
COREn_FLASHm...........................................................................................................32
COREn_ENDIAN...........................................................................................................33
COREn_BREAKMODE.................................................................................................33

COREn_WORKSPACE..................................................................................................34
COREn_DATASPACE....................................................................................................34
COREn_PATH.................................................................................................................34
COREn_FILE..................................................................................................................34
COREn_LOCKOUT_RECOVERY................................................................................35
COREn_OS.....................................................................................................................36
Section PLATFORM_ARM and PLATFORM_ARM11.....................................................36
COREn.............................................................................................................................36
COREn_VECTOR_CATCH_MASK..............................................................................36
COREn_DCC_PORT......................................................................................................37
COREn_USE_FAST_DOWNLOAD..............................................................................37
COREn_BREAK_PATTERN..........................................................................................37
Section PLATFORM_Cortex & Section PLATFORM_Cortex_SWD................................38
COREn.............................................................................................................................38
COREn_APSEL..............................................................................................................38
COREn_DEBUG_ADDR...............................................................................................39
COREn_DAPPC..............................................................................................................39
COREn_PERIODIC_TASK............................................................................................39
COREn_SWO..................................................................................................................40
COREn_PROFILING......................................................................................................40
Section PLATFORM_XSCALE...........................................................................................41
COREn.............................................................................................................................41
COREn_USE_FAST_DOWNLOAD..............................................................................41
COREn_DEBUG_HANDLER_ADDR..........................................................................41
COREn_VECTOR/RELOCATED_UNDEF/SWI/PABORT/DABORT/RES/IRQ/FIQ.42
Section PLATFORM_MPC5200..........................................................................................43
COREn.............................................................................................................................43
COREn_BOOT_ADDR..................................................................................................43
COREn_MEMDELAY....................................................................................................43
Section PLATFORM_MPC5500..........................................................................................43
COREn.............................................................................................................................44
COREn_NEXUS3_ACCESS..........................................................................................44
MPC5XXX_AUX_TAP_CMD, COREn_AUX_TAP_CMD.........................................44
Section PLATFORM_MPC8300..........................................................................................44
COREn.............................................................................................................................45
COREn_BOOT_ADDR..................................................................................................45
COREn_RCW.................................................................................................................45
COREn_MMU_PTBASE................................................................................................45
Section PLATFORM_MPC8500..........................................................................................46
COREn.............................................................................................................................46
COREn_MMU_TRANS.................................................................................................46
COREn_MMU_PTBASE................................................................................................46
Section PLATFORM_QorIQ_P...........................................................................................47
COREn.............................................................................................................................47
COREn_REGLIST..........................................................................................................47
COREn_MMU_TRANS.................................................................................................47
COREn_MMU_PTBASE................................................................................................48
COREn_PMEM_BASE...................................................................................................48
Section PLATFORM_PPC400.............................................................................................48
COREn.............................................................................................................................48
Section PLATFORM_COLDFIRE.......................................................................................49
BDM_CLOCK.................................................................................................................49

CORE...............................................................................................................................49
CORE_MEMMAP..........................................................................................................49
Section PLATFORM_BLACKFIN......................................................................................50
COREn.............................................................................................................................50
COREn_VMEM..............................................................................................................51
COREn_VMEM_WINDOW...........................................................................................51
COREn_VMEM_PINS...................................................................................................51
CORE_MEMMAP..........................................................................................................52
Section PLATFORM_MIPS.................................................................................................52
COREn.............................................................................................................................52
Section PLATFORM_AVR32..............................................................................................53
COREn.............................................................................................................................53
COREn_BLOCK_ACCESS............................................................................................53
Section INIT.........................................................................................................................53
Section FLASH....................................................................................................................54
NOR FLASH programming............................................................................................55
I2C Programming............................................................................................................55
SPI FLASH programming...............................................................................................56
NAND FLASH programming.........................................................................................57
OneNAND FLASH programming...................................................................................59
MMC/SD card programming...........................................................................................59
Atmel SAM3/SAM4 programming.................................................................................59
Atmel AVR32UC3 programming....................................................................................59
Freescale Kinetis programming.......................................................................................60
TI/Luminary LM3S programming...................................................................................60
NXP LPC2000 programming..........................................................................................60
Nordic Semiconductor nRF51 ans nRF52 programming................................................62
Freescale MAC7100 programming.................................................................................63
Freescale ColdFire V2 programming..............................................................................63
Freescale MPC5000 programming..................................................................................64
ST STM32 programming.................................................................................................64
ST STR7 programming....................................................................................................64
ST STR9 programming....................................................................................................65
TI TMS570 programming................................................................................................65
TI TMS470 programming................................................................................................65
PIC32, SmartFusion A2F, ADuC, EFM32 programming................................................66
CHIP................................................................................................................................67
CHECK_ID.....................................................................................................................67
PART_ID.........................................................................................................................67
PARTITION.....................................................................................................................68
BANK..............................................................................................................................68
ACCESS_METHOD.......................................................................................................68
CHIP_WIDTH.................................................................................................................69
CHIP_COUNT................................................................................................................69
CHIP_SIZE......................................................................................................................69
BASE_ADDR..................................................................................................................69
FILE.................................................................................................................................70
SPI_MODE......................................................................................................................70
AUTO_ERASE................................................................................................................70
AUTO_LOCK.................................................................................................................70
CPU_CLOCK..................................................................................................................71
SECURE_FLASH...........................................................................................................71

SET_VECTORS_CHECKSUM......................................................................................71
DATA_BANK..................................................................................................................72
BANK_SIZE...................................................................................................................72
F2F4_PSIZE....................................................................................................................72
PROTECTION_KEY0 – PROTECTION_KEY3...........................................................72
ALLOW_ZERO_KEYS..................................................................................................73
CPU.................................................................................................................................73
SPI_DIV..........................................................................................................................74
nSPI.................................................................................................................................74
nCS..................................................................................................................................74
SPI_SPCK, SPI_MISO, SPI_MOSI, SPI_CS.................................................................74
CMD_BASE....................................................................................................................75
DATA_BASE...................................................................................................................75
ADDR_BASE..................................................................................................................75
CS_ASSERT/RELEASE.................................................................................................76
ALE_ASSERT/RELEASE..............................................................................................76
CLE_ASSERT/RELEASE..............................................................................................76
BAD_BLOCK_TABLE...................................................................................................76
BAD_BLOCKS...............................................................................................................77
ERASE_BAD_BLOCKS................................................................................................77
SWAP_BI.........................................................................................................................77
OOB_INFO.....................................................................................................................77
DAVINCI_UBL_DESCIPTOR_MAGIC........................................................................79
DAVINCI_UBL_DESCIPTOR_ENTRY_POINT..........................................................79
DAVINCI_UBL_DESCIPTOR_LOAD_ADDR.............................................................80
DAVINCI_UBL_MAX_IMAGE_SIZE..........................................................................80
NUM_ECC......................................................................................................................80
HEADER.........................................................................................................................80
IPS_BASE.......................................................................................................................81
SPIFI_BASE....................................................................................................................81
NCB_DATA.....................................................................................................................81
LDLB_DATA..................................................................................................................81
SERIAL_NUM................................................................................................................82
I2C_ADDR......................................................................................................................83
I2C_DELAY....................................................................................................................83
SDA_SET/CLR, SDA_IN/OUT, SDA_READ, SCL_SET/CLR....................................83
CS_ASSERT/RELEASE, SCLK_SET/CLR, MOSI_SET/CLR, MISO_READ............83
Section OS............................................................................................................................84
ITEM...............................................................................................................................84
Section SERIAL...................................................................................................................85
BAUD..............................................................................................................................85
STOP_BITS.....................................................................................................................85
PARITY...........................................................................................................................85
TCP_PORT......................................................................................................................86
Section TELNET..................................................................................................................86
PROMPT.........................................................................................................................86
BACKSPACE..................................................................................................................87
Section DISPLAY................................................................................................................87
VOLUME........................................................................................................................87
Section ACTIONS................................................................................................................87
3.6 CPU specific considerations....................................................................................................88
3.6.1 Philips LPC2000 family...................................................................................................88

3.6.2 ST STM32 family............................................................................................................88
3.6.3 Intel XScale family..........................................................................................................89
3.6.4 Freescale PowerQUICC II Pro MPC83XX family..........................................................90
3.6.5 Analog Devices Blackfin family......................................................................................91
3.7 Boot se uence..........................................................................................................................91
3.8 Multiple core support...............................................................................................................94
3.9 Script execution using the front panel interface......................................................................96
3.10 Serial Interface.......................................................................................................................98
3.11 ARM DCC Interface..............................................................................................................98
3.12 Working with gdb..................................................................................................................99
3.13 Debugging Linux kernel......................................................................................................101
3.14 Target OS thread awareness.................................................................................................102
3.15 Working with CLI (Command Line Interface)....................................................................105
3.15.1 File path convention.....................................................................................................106
3.15.2 CLI commands.............................................................................................................108
help.....................................................................................................................................108
transfer................................................................................................................................109
type.....................................................................................................................................109
wait.....................................................................................................................................110
core.....................................................................................................................................110
clock....................................................................................................................................111
run.......................................................................................................................................111
go........................................................................................................................................112
gm.......................................................................................................................................112
step......................................................................................................................................113
execute................................................................................................................................114
set........................................................................................................................................114
halt......................................................................................................................................115
reset.....................................................................................................................................115
reboot..................................................................................................................................116
echo.....................................................................................................................................117
jtag......................................................................................................................................117
beep.....................................................................................................................................117
target...................................................................................................................................118
uit......................................................................................................................................118
info......................................................................................................................................119
Info flash.............................................................................................................................119
info registers.......................................................................................................................119
info target............................................................................................................................120
info config..........................................................................................................................120
info ice................................................................................................................................121
info cp15, info cp14............................................................................................................121
info spr................................................................................................................................123
info ctrl...............................................................................................................................123
info breakpoint...................................................................................................................124
memory...............................................................................................................................124
memory read.......................................................................................................................125
memory write.....................................................................................................................125
memory or..........................................................................................................................126
memory and........................................................................................................................127
memory crc.........................................................................................................................128
memory load.......................................................................................................................128

memory multi load.............................................................................................................129
memory verify....................................................................................................................130
memory dump.....................................................................................................................130
memory management.........................................................................................................131
memory test........................................................................................................................132
flash....................................................................................................................................132
flash set...............................................................................................................................133
flash blank..........................................................................................................................133
flash erase...........................................................................................................................133
flash lock............................................................................................................................134
flash unlock........................................................................................................................135
flash uery..........................................................................................................................135
flash program......................................................................................................................136
flash multi erase..................................................................................................................136
flash multi blank.................................................................................................................137
flash multi program............................................................................................................138
flash verify..........................................................................................................................139
flash multi verify................................................................................................................139
flash dump..........................................................................................................................140
flash read............................................................................................................................141
flash info.............................................................................................................................141
flash find.............................................................................................................................142
flash test..............................................................................................................................142
flash area.............................................................................................................................143
flash this.............................................................................................................................144
flash this hidden..................................................................................................................144
flash this markbad..............................................................................................................145
flash this nvmbit.................................................................................................................145
flash this secure..................................................................................................................145
flash this option..................................................................................................................146
flash this option..................................................................................................................146
flash this write....................................................................................................................147
flash this part......................................................................................................................147
flash this prot......................................................................................................................148
flash this prot read..............................................................................................................148
flash this prot program.......................................................................................................149
flash this ppb......................................................................................................................149
flash this isc_erase..............................................................................................................150
flash this isc_conf_write.....................................................................................................150
flash this isc_conf_read......................................................................................................151
flash this isc_conf_boot_bank............................................................................................151
flash this isc_conf_lock......................................................................................................151
breakpoint...........................................................................................................................152
breakpoint add....................................................................................................................152
breakpoint list.....................................................................................................................153
breakpoint delete................................................................................................................154
card.....................................................................................................................................154
card cd................................................................................................................................155
card rd.................................................................................................................................155
card dir................................................................................................................................155
card copy............................................................................................................................156
card type.............................................................................................................................156

card delete...........................................................................................................................157
card rename........................................................................................................................157
eeprom................................................................................................................................158
eeprom dir...........................................................................................................................158
eeprom copy.......................................................................................................................158
eeprom type........................................................................................................................159
eeprom delete.....................................................................................................................159
eeprom rename...................................................................................................................160
eeprom format....................................................................................................................160
eeprom alias........................................................................................................................161
test......................................................................................................................................161
amp.....................................................................................................................................162
3.15.3 Working with the FLASH programmer.......................................................................162
3.16 Multiple FLASH support.....................................................................................................164
3.17 Working with a MMC/SD memory card.............................................................................164
3.18 JTAG cable adapters............................................................................................................165
3.19 PEEDI licenses....................................................................................................................166
4 Specifications................................................................................................................................167
4.1 JTAG Target connector signals..............................................................................................168
4.2 RS232 Connector (DB9F, female).........................................................................................170
4.3 Schematics.............................................................................................................................170
5 Warranty........................................................................................................................................170
6 PEEDI Package contents...............................................................................................................171
7 FAQ...............................................................................................................................................171
8 Glossary.........................................................................................................................................176

Table of Figures
Figure 1.1: Single developer environment.........................................................................................12
Figure 1.2: Multiple developers environment....................................................................................13
Figure 1.3: FLASH programmer with PC..........................................................................................14
Figure 1.4: FLASH programmer without PC.....................................................................................14
Figure 1.5: Multi board programming................................................................................................15
Figure 2.1: PEEDI Front Panel...........................................................................................................16
Figure 2.2: PEEDI Rear Panel............................................................................................................16
Figure 2.3: Direct host connection.....................................................................................................17
Figure 2.4: LAN connection...............................................................................................................17
Figure 2.5: Target connection.............................................................................................................17
Figure 3.1: Front panel interface........................................................................................................18
Figure 3.2: Rear panel interface.........................................................................................................19
Figure 3.3: MMU_PTBASE...............................................................................................................91
Figure 3.4: PEEDI Boot Se uence.....................................................................................................93
Figure 3.5: Multi Target connection...................................................................................................94
Figure 3.6: Adapter JTAG cable.......................................................................................................165
Figure 3.7: JTAG Adapter PEEDI-4xARM20..................................................................................165
Figure 4.1: PEEDI JTAG connector.................................................................................................167
Figure 4.2: RS232 connector............................................................................................................169

Introduction
1 Introduction
PEEDI (Powerful Embedded Ethernet Debug Interface) is an EmbeddedICE solution that enables
you to debug software running a wide variety of processor cores via the JTAG port. JTAG is an
IEEE standardized protocol that enables full control of the CPU core, giving the opportunity to
debug embedded software. The PEEDI will help to reduce Time-To-Market and increase the uality
of the end product.
PEEDI is a debugging and development tool that provides the ability to see what is taking place in
the target system and control its behavior. PEEDI provides the services needed to perform all
debugging operations. It receives command packets over the communication link and translates
them into JTAG operations that are needed to provide the specific service. It can control the
operation of the target processor and target system, start and stop the processor's execution; it can
set breakpoints in a program, examine and store values in the processor’s registers, and examine
and store program code or data in the target system’s memory. PEEDI can work in cooperation with
a host computer or autonomously using a MMC/SD card.
PEEDI User’s Manual 11 www.ronetix.at

Introduction
1.1 PEEDI in the de elopment process
In the development process PEEDI can be used mainly as a debugger JTAG interface and FLASH
programmer.
Two major configurations are possible here:
•Single developer environment
•Multiple developers environment
1.1.1 Single de eloper en ironment
Using the developer’s PC as a host computer - this is suitable for small projects. Here all necessary
tools for compiling and debugging the project must be installed on the developers PC, including file
server (TFTP, FTP or HTTP) allowing PEEDI to retrieve configuration files or executable images.
In this (Figure 1) configuration the developer’s PC must be connected to PEEDI in a common LAN
using crossover patch cable or by Ethernet via hub/switch.
PEEDI User’s Manual 12 www.ronetix.at
Figure 1.1: Single developer environment

Introduction
1.1.2 Multiple de elopers en ironment
Dedicated server with all the necessary development tools installed is used for a host. The developer
uses a PC only as a graphical terminal to logon to the server. No specific software is installed on the
developer’s PC, so it is very easy to set another working environment for a new developer for the
project - just add a new user on the server and make a copy of the project source and make files in
the user’s home directory. Of course any source control tool, such as CVS or Visual Source Safe,
can be used for synchronizing the project files. In this configuration (Figure 2) all devices (the
server, the developers’ PCs and all PEEDIs) must be connected in a common LAN.
Figure 1.2: Multiple developers environment
1.2 PEEDI in the manufacturing process
PEEDI can be used in the manufacturing process as a tool for testing the device after it is assembled
and as a FLASH programmer to program the device firmware. In both scenarios the host computer
is not re uired because all the operations can be formed as script files and executed using the
PEEDI’s front panel interface. If all the necessary files are stored on the MMC/SD card the Ethernet
connection is not re uired as well.
PEEDI User’s Manual 13 www.ronetix.at

Introduction
1.2.1 PEEDI as a standalone FLASH programmer
PEEDI can be used as a FLASH programmer in two ways:
•The first way ( Figure 1.3: FLASH programmer with PC) is to connect to PEEDI via telnet
and execute FLASH command and script files from the command line interface (CLI). This
method enables users to see all the status messages in an easy, understable format i.e.
warnings and errors and therefore, maybe the preferred method.
Figure 1.3: F ASH programmer with PC
•The second way (Figure 1.4: FLASH programmer without PC) is to use the front panel
interface to choose, start and observe the status of scripts, which invokes the desired FLASH
commands. Here you can define an AUTORUN script to be executed every time a target is
connected; this way there is no need to start the script manually – very useful and time
saving when large volumes of target boards need to be programmed.
Figure 1.4: F ASH programmer
without PC
PEEDI User’s Manual 14 www.ronetix.at

Introduction
1.2.2 PEEDI as a de ice tester
Here the PEEDI can be used in the same manner as in the previous section - making telnet
connection or through the front panel interface.
Depending on the specifics of what is to be tested two options can be applied:
•Execute commands that directly make some sort of test i.e. flash verify , memory test , etc.
•Download executable code into target, which will perform the desired test and set a CPU
register or memory on exit to a value showing the result of the test. This option is often
preferred because there are virtually no limits to test examples a user can create.
1.2.3 High producti ity with the Multi Program feature
With the “Multi Program” feature users can increase productivity by working on upto four boards
simultaneously using a single PEEDI. The boards must be chained using a multi-core adapter
(Figure 1.5: Multi board programming) available from Ronetix.
Figure 1.5: Multi board programming
2 Installation
This chapter will explain how to connect PEEDI to the target and how to configure all the tools
necessary for development. Two major steps must be followed in order to set up a working PEEDI:
•Connect all re uired cables, this includes a power cord, target cable and if necessary an
Ethernet cable, which will provide connection to a host computer or file server.
This is explained in subsection 2.1.Hardware installation
PEEDI User’s Manual 15 www.ronetix.at

Installation
•Install and configure insight/gdb debugger.
This is explained in subsection 2.2.Software installation
2.1 Hardware installation
JTAG Target
connector
MMC/SD
card slot
ETH STAT
PWR TPW
START
SELECT TARGET
Figure 2.1: PEEDI Front Panel
RS232 port Power
connector
thernet
port
RS232 5V / 1A RST thernet
Figure 2.2: PEEDI Rear Panel
2.1.1 Connection instructions
To connect the PEEDI interface unit to your host and to the target hardware:
•Connect the host computer to an Ethernet network or directly to the PEEDI as re uired:
◦Direct host connection
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Installation
Figure 2.3: Direct host connection
◦LAN connection
•Connect the PEEDI interface unit to the target hardware, using the supplied JTAG adapter
and cable. The JTAG adapter must be on the PEEDI side of the JTAG cable. If your target
JTAG port pinout is not standard, you may need to make your own target cable considering
the PEEDI JTAG connector pinout.
Refer to subsection 4.1 JTAG Target connector signals for the PEEDI JTAG connector pinout.
•Power up the target hardware.
•Connect the external power supply to the PEEDI and apply power.
PEEDI User’s Manual 17 www.ronetix.at
Figure 2.4: AN connection
Figure 2.5: Target connection

Installation
•When PEEDI boots, if you have a terminal connected to the RS232 port of PEEDI you will
see various status messages.
2.2 Software installation
See ’Cross development with GNU toolchain and Eclipse’:
http://download.ronetix.at/toolchains/arm/arm_cross_development_guide.pdf
3 Using PEEDI
This chapter will explain PEEDI’s operating modes, PEEDI’s interface and the basic steps of
configuring the software tools for working with PEEDI.
To start using PEEDI you need to:
•configure network settings
•make target configuration file
3.1 PEEDI interface
1
3
6 8
5
47
2
9
ETH STAT
PWR TPW
START
SELECT TARGET
Figure 3.1: Front panel interface
PEEDI User’s Manual 18 www.ronetix.at

Using PEEDI
12
11 1310
RS232 5V / 1A RST thernet
Figure 3.2: Rear panel interface
Table 3.1: PEEDI Interface
Pos. Description
1 Power LED
2 Target power LED
3 Ethernet connect/activity LED
4 Target connect/activity LED
5 Script number/status LED display
6 Next script button
7 Start script button
8 Target connector
9 MMC/SD card slot
10 RS232 port
11 Power supply
12 Reset button
13 Ethernet port
3.2 Setup with RedBoot
RedBoot is a bootstrap loader, which during normal boot-up is used to load and launch PEEDI’s
executable image. RedBoot is also used to update PEEDI’s firmware and to configure network
PEEDI User’s Manual 19 www.ronetix.at

Using PEEDI
settings, which are later used by PEEDI. RedBoot has some useful testing facilities like ping and
memtest .
3.2.1 RedBoot Configuration
RedBoot and PEEDI share the same network settings. To set the network you need to connect a
simple terminal application set to 115200, 8, N, 1 (for example HyperTerminal) to the PEEDI’s
RS232 port using a serial straight-through cable with DB9M (male) and DB9F (female) connectors
on each end. Next step is to restart PEEDI by pressing the RESET button while holding both front
panel buttons in. This will tell RedBoot not to load and launch the PEEDI executable if available,
but to wait for connection on RS232 or Ethernet. While rebooting RedBoot should output some
diagnostic information on the serial port which you should see. When RedBoot is ready to accept
commands, it will show the command line prompt ’RedBoot> ’. Now you can use the fconfig
command to set and save to FLASH all the parameters. When asked for different parameters please
enter the following:
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Use DHCP for network configuration: yes /[no][ENTER]
Gateway IP a ress: X.X.X.X
Local IP a ress: X.X.X.X
Local IP a ress mask: X.X.X.X
Default server IP a ress, use by Re Boot an PEEDI: X.X.X.X
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Next you will be asked for the path of the configuration file:
Target config file path:
Accepted paths for the different protocols are:
PEEDI User’s Manual 20 www.ronetix.at