Samsung HT-DL200 User manual

DVD RECEIVER AMP
HT-DL200
SERVICEManual
DVD RECEIVER AMP SYSTEM CONTENTS
V I D E O
Function
Volume
Phones
1. Alignment and Adjustments
2. Exploded Views and Parts List
3. Electrical Parts List
4. Block Diagrams
5. PCB Diagrams
6. Wiring Diagram
7. Schematic Diagrams
8. IC block Diagrams
9.Troubleshooting

ELECTRONICS
© Samsung Electronics Co.,Ltd. FEB. 2002
Printed in Korea
Code no. AH68-00664Y

Samsung Electronics 8-1
8. IC Block Digrams
8-1 Main
1. 74CX244
LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
ORDER CODES :
74LCX244M 74LCX244T
M
(Micro Package)
■5VTOLERANTINPUTSAND OUTPUTS
■HIGHSPEED:
tPD =6.5ns(MAX.)atVCC =3V
■POWER-DOWNPROTECTIONON INPUTS
ANDOUTPUTS
■SYMMETRICALOUTPUTIMPEDANCE:
|IOH|=IOL = 24mA(MIN)
■PCIBUSLEVELSGUARANTEED AT24mA
■BALANCEDPROPAGATIONDELAYS:
tPLH ≅tPHL
■OPERATINGVOLTAGERANGE:
VCC (OPR)= 2.0Vto3.6V (1.5VDataRetention)
■PINANDFUNCTIONCOMPATIBLEWITH
74SERIES244
■LATCH-UPPERFORMANCE EXCEEDS500mA
■ESDPERFORMANCE:
HBM >2000V;MM > 200V
DESCRIPTION
The LCX244 is a low voltage CMOS OCTAL BUS
BUFFER (NON-INVERTED) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low
power and high speed 3.3V applications; it can
be interfaced to 5V signal environment for both
T
(TSSOPPackage)
inputsandoutputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
This device is designed to be used with 3 state
memoryaddressdrivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS

8-2 Samsung Electronics
2. 74VHC244
74VHC244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHC244 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC244 is a non-inverting 3-STATE buffer hav-
ing two active-LOW output enables. These devices are
designed to be used as 3-STATE memory address drivers,
clock drivers, and bus oriented transmitter/receivers.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
■High Speed: tPD =3.9ns (typ) at VCC =5V
■High noise immunity: VNIH =VNIL =28% VCC (min)
■Power down protection is provided on all inputs
■Low noise: VOLP =0.6V (typ)
■Low power dissipation: ICC =4 µA (max) @ TA=25°C
■Pin and function compatible with 74HC244
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ìXî to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC244M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300î Wide
74VHC244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300î Wide
Pin Names Description
OE1, OE23-STATE Output Enable Inputs
I0ñI7Inputs
O0ñO73-STATE Outputs

Samsung Electronics 8-3
74VHCT244A
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHCT244A is an advanced high speed CMOS octal
bus transceiver fabricated with silicon gate CMOS technol-
ogy. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHCT244A is a non-inverting 3-
STATE buffer having two active-LOW output enables. This
device is designed to be used as 3-STATE memory
address drivers, clock drivers, and bus oriented transmitter/
receivers.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. These circuits prevent device destruction
due to mismatched supply and input/output voltages. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery back up.
Note 1: Outputs in OFF-State
Features
■High Speed: tPD =5.9 ns (typ) at VCC =5V
■Power down protection is provided on inputs and
outputs
■Low power dissipation: ICC =4 µA (max) @ TA=25°C
■Pin and function compatible with 74HCT244
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ìXîto the ordering code.
Logic Symbol Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHCT244AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHCT244ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT244AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT244AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OE1, OE23-STATE Output Enable Inputs
I0ñI7Inputs
O0ñO73-STATE Outputs
3. 74VHCT244A

8-4 Samsung Electronics
4. CS4228
5. CS49300

Samsung Electronics 8-5
6. CS8415A

8-6 Samsung Electronics
7.LC75275A
Pin Functions
Pin Pin No. Function I/O Handling when unused
VFL 1, 13 Driver block power supply connection. (Both pins must be connected.) — —
VDD 60 Logic block power supply connection. Provide a voltage between 4.5 and 5.5 V. — —
VSS 57 Power supply connection. Connect to the ground. — —
OSCI 59 Oscillator connection. An oscillator circuit is formed by connecting an external resistor I GND
OSCO 58 and capacitor to these pins. O OPEN
Display off control input.
BLK 61 BLK = Low (VSS) ... Display off. (S1 to S43 and G1 to G11 at VFL level.) I GND
BLK = High (VDD) ... Display on.
Note that serial data can be transferred while the display is turned off.
CL 63
DI 64 I GND
CE 62
G1 to G11 2 to 12 Digit outputs. These pins are P-channel open drain outputs with pull-down resistors. O OPEN
S1 to S43 56 to 14 Segment outputs for displaying the display data transferred by serial data input. These pins O OPEN
are P-channel open drain outputs with pull-down resistors.
Serial data transfer inputs. These pins must be connected to the system microcontroller.
CL: Synchronization clock
DI: Transfer data
CE: Chip enable

Samsung Electronics 8-7
Publication Release Date: June 1999
-1 - Revision A2
FEATURES
•High speed access time:High speed access time:
120/150 nS (max.)120/150 nS (max.)
•Read operating current: 10 mA (max.)Read operating current: 10 mA (max.)
•Erase/ rogramming operating current:Erase/ rogramming operating current:
30 mA (max.)30 mA (max.)
•Standby current: 20 Standby current: 20 µA (max.)A (max.)
•Low voltage power supply range, 3.0V to 3.6VLow voltage power supply range, 3.0V to 3.6V
•+14V erase/+12V programming voltage+14V erase/+12V programming voltage
•Fully static operationFully static operation
•All inputs and outputs directly TTL/CMOS All inputs and outputs directly TTL/CMOS
compatiblecompatible
•Three-state outputs
•AvailableAvailable packages: 32-pin 600 mil DI , 450packages: 32-pin 600 mil DI , 450
mil mil SO and LCCSO and LCC
PIN CONFIGURATIONS
A6A6
A5A5
A4A4
A3A3
A2A2
A1A1
A0A0
Q0Q0
5
6
7
8
9
1010
1111
1212
1313
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4 3 2 1 3
2
3
13
0A14A14
A13A13
A8A8
A9A9
OEOE
A11A11
Q7Q7
2929
2828
2727
2626
2525
2424
2323
2222
2121
32-pin LCC32-pin LCC
G
N
D
1
5
1
6
1
7
1
8
1
9
2
0
N
C
V
c
c
CECE
A10A10
Q5Q5
OEOE
A10A10
Q7Q7
Q6Q6
A13A13
A8A8
A9A9
A11A11
GMGM
NCNC
Q0Q0
A0A0
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A12A12
A15A15
A16A16
A14A14
A1A1
VccVcc
Vpp
A
1
5
A
1
6
1
2
3
4
5
6
7
8
9
1010
1111
1212
1313
1414
1515
1616
3030
3131
3232
2525
2626
2727
2828
2929
2020
2121
2222
2323
2424
1919
1818
1717 Q3Q3
Q4Q4
GNDGND
Q2Q2
CECE
Q1Q1
Q
3
A7A7
A
1
2
V
p
p
/
G
M
32-pin DI32-pin DI
BLOCK DIAGRAM
CONTROL OUTPUT
BUFFER
DECODER CORE
ARRAY
Q0Q0
Q7Q7
.
.
CECE
OEOE
A0A0
.
.
V
GNDGND
CCCC
A16A16
GMGM
V
PIN DESCRIPTION
SYMBOLSYMBOL DESCRIPTIONDESCRIPTION
A0A0−A16A16 Address InputsAddress Inputs
Q0Q0−Q7Q7 Data Inputs/OutputsData Inputs/Outputs
CE
CE
Chip EnableChip Enable
OE
OE
Output EnableOutput Enable
GM
GM
rogram Enablerogram Enable
Vrogram/Erase Supply Voltagerogram/Erase Supply Voltage
VCCCC ower Supplyower Supply
GNDGND GroundGround
NCNC No ConnectionNo Connection
8.W271010

8-8 Samsung Electronics
8-2 DVD
1. ZIVA- 5 DVD CONTROLER
Figure 1 ZiVA-5 controller Pinout (208-pin PQFP)
Table 1 ZiVA-5 controller Pin List
Pin No. Pin Name I/O Voltage I/O Type
1 VDDP 3.3V ó
2 HA1 3.3V* I/O
3 HA15 3.3V* I/O
4 HA14 3.3V* I/O
5 HA13 3.3V* I/O
6 HA12 3.3V* I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD_3.3
HA1
HAD15 HAD14 HAD13 HAD12 HAD11 HAD10
HAD9 HAD8 HAD7
VDD_3.3
VSS
HAD6 HAD5 HAD4 HAD3 HAD2 HAD1
VDD_3.3
VSS
HAD0
HDTACK/WAIT
HIRQ0
UDS/UWE
LDS/LWE
R/W
IRRX1
VSS
VDDC
VSS
VDD_3.3
MADDR9 MADDR8 MADDR7 MADDR6 MADDR5 MADDR4 MADDR3 MADDR2 MADDR1 MADDR0
VSS
VDD_3.3
MADDR10 MADDR11
BA1 BA0
MCS0
MCS1
MRAS
MCAS
DA-IEC958 DA-DATA3 DA-DATA2 VSS VDD_3.3 DA-DATA1 DA-DATA0 DA-BCK DA-LRCK DA-XCK VSS VDDC A_VSS1 A_VDD1 A_VDD2 A_VSS2 XVDD XTAL/VCLK216BP XTAL XVSS VSS_RREF VDAC_RREF VDD_RREF VDAC_DVDD VDAC_DVSS VDAC_0 VDAC_VDD0 VDAC_0B VDAC_1 VDAC_VDD1 VDAC_1B VDAC_2 VDAC_VDD2 VDAC_2B VDAC_3 VDAC_VDD3 VDAC_3B VDAC_4 VDAC_VDD4 VDAC_4B HSYNC/IRQ2
VDATA0 VDATA1 VDATA2 VSS VDD_3.3 VDATA3 VDATA4 VDATA5 VDATA6 VDATA7 VCLK
DAI-DATA
DAI-BCK/SYSCLKBP
DAI-LRCK/IEC958BP
I2C_CL
I2C_DA
RTS1
RXD1
TXD1
CTS1
VSS
VDD_3.3
SD-DATA7
SD-DATA6
SD-DATA5
SD-DATA4
VSS
VDDC
SD-DATA3
SD-DATA2
SD-DATA1
SD-DATA0
SD-REQ
SD-EN
VSS
VDD_3.3
SD-ERROR
SD-CLK
VSYNC/HIRQ1
RTS2/SPI_CLK
RXD2/SPI_MISO
TXD2/SPI_MOSI
CTS2/SPI_CS
VDD_5
HCS4
HCS3
HCS2
HCS1
HCS0
VSS
VDD_3.3
TRST
TDO
TDI
TMS
TCK
RESET
ALE
VSS
VDDC
HAD3
HAD2
VSS
ZiVA-5 Controller
Top View
VDD_3.3
VSS
MDATA31
MDATA30
MDATA29
MDATA28
VDD_3.3
MDQM3
VSS
MDATA27
MDATA26
MDATA25
MDATA24
MDATA23
MDATA22
MDATA21
MDATA20
VDD_3.3
MDQM2
VSS
MDATA19
MDATA18
MDATA17
MDATA16
VDDC
VSS
MDATA15
MDATA14
MDATA13
MDATA12
VDD_3.3
MDQM1
VSS
MDATA11
MDATA10
MDATA9
MDATA8
MDATA7
MDATA6
MDATA5
MDATA4
VDD_3.3
MDQM0
VSS
MDATA3
MDATA2
MDATA1
MDATA0
MCLK
VDD_3.3
VSS
MWE

Samsung Electronics 8-9
7 HA11 3.3V* I/O
8 HA10 3.3V* I/O
9 HA9 3.3V* I/O
10 HA8 3.3V* I/O
11 HA7 3.3V* I/O
12 VDDP 3.3V ó
13 GNDP GROUND ó
14 HA6 3.3V* I/O
15 HA5 3.3V* I/O
16 HA4 3.3V* I/O
17 HA3 3.3V* I/O
18 HA2 3.3V* I/O
19 HA1 3.3V* I/O
20 VDDP 3.3V ó
21 GNDP GROUND ó
22 HA0 3.3V* I/O
23 HDTACK/WAIT 3.3V* I/OD
24 HIRQ0 3.3V* I/O
25 HUDS/UWE 3.3V* I/O
26 HLDS/LWE 3.3V* I/O
27 HREAD 3.3V* I/O
28 IRRX1/GPIO[0] 3.3V* I
29 GND GROUND ó
30 VDD 1.8V ó
31 GND25 GROUND ó
32 VDD25 3.3V ó
33 MA9 3.3V O
34 MA8 3.3V O
35 MA7 3.3V O
36 MA6 3.3V O
37 MA5 3.3V O
38 MA4 3.3V O
39 MA3 3.3V O
40 MA2 3.3V O
41 MA1 3.3V O
42 MA0 3.3V O
43 GND25 GROUND ó
44 VDD25 3.3V ó
45 MA10 3.3V O
46 MA11 3.3V O
47 BA1 3.3V O
48 BA0 3.3V O
49 MCS0 3.3V O
50 MCS1 3.3V O
51 MRAS 3.3V O
52 MCAS 3.3V O
53 MWE 3.3V O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
Confid
Advance Pr
54 GND25 GROUND ó
55 VDD25 3.3V ó
56 MCLK O
57 MD0 3.3V I/O
58 MD1 3.3V I/O
59 MD2 3.3V I/O
60 MD3 3.3V I/O
61 GND25 GROUND ó
62 MDQM0 3.3V O
63 VDD25 3.3V ó
64 MD4 3.3V I/O
65 MD5 3.3V I/O
66 MD6 3.3V I/O
67 MD7 3.3V I/O
68 MD8 3.3V I/O
69 MD9 3.3V I/O
70 MD10 3.3V I/O
71 MD11 3.3V I/O
72 GND25 GROUND ó
73 MDQM1 3.3V O
74 VDD25 3.3V ó
75 MD12 3.3V I/O
76 MD13 3.3V I/O
77 MD14 3.3V I/O
78 MD15 3.3V I/O
79 GND GROUND ó
80 VDD 1.8V ó
81 MD16 3.3V I/O
82 MD17 3.3V I/O
83 MD18 3.3V I/O
84 MD19 3.3V I/O
85 GND25 GROUND ó
86 MDQM2 3.3V O
87 VDD25 3.3V ó
88 MD20 3.3V I/O
89 MD21 3.3V I/O
90 MD22 3.3V I/O
91 MD23 3.3V I/O
92 MD24 3.3V I/O
93 MD25 3.3V I/O
94 MD26 3.3V I/O
95 MD27 3.3V I/O
96 GND25 GROUND ó
97 MDQM3 3.3V O
98 VDD25 3.3V ó
99 MD28 3.3V I/O
100 MD29 3.3V I/O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type

8-10 Samsung Electronics
101 MD30 3.3V I/O
102 MD31 3.3V I/O
103 GND25 GROUND ó
104 VDD25 3.3V ó
105 VCLK 3.3V* I/O
106 VDATA7/GPIO[1] 3.3V* I/O
107 VDATA6/GPIO[2] 3.3V* I/O
108 VDATA5/GPIO[3] 3.3V* I/O
109 VDATA4/GPIO[4] 3.3V* I/O
110 VDATA3/GPIO[5] 3.3V* I/O
111 VDDP 3.3V ó
112 GNDP GROUND ó
113 VDATA2/GPIO[6] 3.3V* I/O
114 VDATA1/GPIO[7] 3.3V* I/O
115 VDATA0/GPIO[8] 3.3V* I/O
116 HSYNC/HIRQ2/GPIO[9] 3.3V* I/O
117 VDAC_4B ANALOG O
118 VDAC_VDD4 3.3VANALOG ó
119 VDAC_4 ANALOG O
120 VDAC_3B ANALOG O
121 VDAC_VDD3 3.3VANALOG ó
122 VDAC_3 ANALOG O
123 VDAC_2B ANALOG O
124 VDAC_VDD2 3.3VANALOG ó
125 VDAC_2 ANALOG O
126 VDAC_1B ANALOG O
127 VDAC_VDD1 3.3VANALOG ó
128 VDAC_1 ANALOG O
129 VDAC_0B ANALOG O
130 VDAC_VDD0 3.3VANALOG ó
131 VDAC_0 ANALOG O
132 VDAC_DVSS GROUND
133 VDAC_DVDD 3. 3V
134 VAC_REFVDD 3.3V
135 VDAC_REF ANALOG I
136 VDAC_REFVSS GROUND
137 XVSS GROUND
138 XOUT ANALOG
139 XIN/bypassclk_216 ANALOG
140 XVDD 3.3V
141 AVSS2 GROUND
142 AVDD2 3.3V
143 AVDD1 3.3V
144 AVSS1 GROUND
145 VDD 1.8V ó
146 GND GROUND ó
147 XCK 3.3V* I/O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
148 LRCK 3.3V* O
149 BCK 3.3V* O
150 ADATA0/GPIO[10] 3.3V* O
151 ADATA1/GPIO[11] 3.3V* O
152 VDDP 3.3V ó
153 GNDP GROUND ó
154 ADATA2/GPIO[12] 3.3V* O
155 ADATA3/GPIO[13] 3.3V* O
156 IEC958/GPIO[14] 3.3V* O
157 DAI_DATA/GPIO[15] 3.3V* I
158 DAI_BCK/bypass_sysclk/
GPIO[16] 3.3V* I
159 DAI_LRCK/iec958bp/GPIO[17] 3.3V* I
160 I2C_CL/GPIO[18] 3.3V* I/OD
161 I2C_DA/GPIO[19] 3.3V* I/OD
162 RTS1/GPIO[20] 3.3V* O
163 RXD1/GPIO[21] 3.3V* I
164 TXD1/GPIO[22] 3.3V* O
165 CTS1/GPIO[23] 3.3V* I
166 GNDP GROUND ó
167 VDDP 3.3V ó
168 SDDATA7/VDATA2[7]/
HDMARQ/GPIO[24] 3.3V I
169 SDDATA6/VDATA2[6]/HXCVR_
EN/
GPIO[25]
3.3V* I
170 SDDATA5/VDATA2[5]/
HDMACK/GPIO[26] 3.3V* I
171 SDDATA4/VDATA2[4]/GPIO[27] 3.3V* I
172 GND GROUND ó
173 VDD 1.8V ó
174 SDDATA3/VDATA2[3]/GPIO[28] 3.3V* I
175 SDDATA2/VDATA2[2]/GPIO[29] 3.3V* I
176 SDDATA1/VDATA2[1]/GPIO[30] 3.3V* I
177 SDDATA0/VDATA2[0]
/GPIO[31] 3.3V* I
178 SDREQ/GPIO[32] 3.3V* O
179 SDEN/GPIO[33] 3.3V* I
180 GNDP GROUND ó
181 VDDP 3.3V ó
182 SDERROR/GPIO[34] 3.3V* I
183 SDCLK/GPIO[35] 3.3V* I
184 VSYNC/HIRQ1/GPIO[36] 3.3V* I/O
185 RTS2/SPI_CLK/GPIO[37] 3.3V* O
186 RXD2/SPI_MISO/GPIO[38] 3.3V* I
187 TXD2/SPI_MOSI/GPIO[39] 3.3V* O
188 CTS2/SPI_CS/GPIO[40] 3.3V* I
189 VNW 5V ó
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type

Samsung Electronics 8-11
Note:TheZiVA-5coreoperatesat1.8V±10%.MostI/Ointerfacepinscanbeinterfacedwith3.3-Vor5-Vdevicesdepending onthevoltageappliedtotheVDDpinsassociated
with them. Refer to the Application Note for more information.
190 HCS4/GPIO[41] 3.3V* I
191 HCS3/GPIO[42] 3.3V* I
192 HCS2/GPIO[43] 3.3V* I
193 HCS1 3.3V* I/O
194 HCS0 3.3V* I/O
195 GNDP GROUND ó
196 VDDP 3.3V ó
197 TRST 3.3V* I
198 TDO 3.3V* O
199 TDI/GPI[0] 3.3V* I
200 TMS/GPI[1] 3.3V* I
201 TCK 3.3V* I
202 RESET 3.3V* I
203 ALE 3.3V* I/O
204 GND GROUND ó
205 VDD 1.8V ó
206 HA3 3.3V* I
207 HA2 3.3V* I
208 GNDP GROUND ó
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
13.5 MHz Crystal
Bus Interface Unit
IR IDC
SPARC
Microprocessor
Phase
Lock
Loop
ATAPI
SDRAM Controller
System Control Bus
Audio
Output
Unit
GPIO SPI
UART1& 2
ZiVA
A/V Core
Audio
Input Unit
Decryption
Track Buffer
Processor Interlaced/
ProgProgressive
Video
Encoder
Five 10-bit
Video
DACs
Graphics
Engine
CCIR 656
ASYNC BUS
32-128Mbit

8-12 Samsung Electronics
BLOCK DIAGRAM
DQ0DQ0
DQ31DQ31
DQM0~3DQM0~3
CLKCLK
CKECKE
A10A10
CLOCKCLOCK
BUFFERBUFFER
COMMANDCOMMAND
DECODERDECODER
ADDRESSADDRESS
BUFFERBUFFER
REFRESHREFRESH
COUNTERCOUNTER COLUMNCOLUMN
COUNTERCOUNTER
CONTROLCONTROL
SIGNALSIGNAL
GENERATORGENERATOR
MODEMODE
REGISTERREGISTER
COLUMN DECODERCOLUMN DECODER
SENSE AMPLIFIERSENSE AMPLIFIER
CELL ARRAYCELL ARRAY
BANK #2BANK #2
COLUMN DECODERCOLUMN DECODER
SENSE AMPLIFIERSENSE AMPLIFIER
CELL ARRAYCELL ARRAY
BANK #0BANK #0
COLUMN DECODERCOLUMN DECODER
SENSE AMPLIFIERSENSE AMPLIFIER
CELL ARRAYCELL ARRAY
BANK #3BANK #3
DATA CONTROLDATA CONTROL
CIRCUITCIRCUIT DQDQ BUFFERBUFFER
COLUMN DECODERCOLUMN DECODER
SENSE AMPLIFIERSENSE AMPLIFIER
CELL ARRAYCELL ARRAY
BANK #1BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW DECODERROW DECODER ROW DECODERROW DECODER
ROW DECODERROW DECODERROW DECODERROW DECODER
A0A0
A9A9
BS0BS0
BS1BS1
CSCS
RASRAS
CASCAS
WEWE
2.W986432DH

Samsung Electronics 8-13
3. M6759 ; 8BIT MTP micro controller
4. M5701/M5705 ; DVD ROM controller
M5701/M5705

8-14 Samsung Electronics
Pin Assignments
Pin Definitions
Internal Block Diagram
Pin Number Pin Name I/O Pin Function Description
1 GND - Ground
2V
O1 O Output 1
3V
CTL I Motor speed control
4V
IN1 I Input 1
5V
IN2 I Input 2
6SV
CC - Supply voltage (Signal)
7 V
CC - Supply voltage ( ower)
8V
O2 O Output 2
1
2
5
6
7
8
GND
VO1
VCTL
VIN1 VIN2
SVCC
VCC
VO2
3
4
FAN8082
DRIVER OUT
LOGIC SWITCH
1
2
5
6
7
8
GND
VO1
VCTL
VIN1 VIN2
SVCC
VCC
VO2
3
4
TSD
RE DRIVER
BIAS
5. FAN8082

Samsung Electronics 8-15
6. M11B416256A

8-16 Samsung Electronics
Y-Decoder
I/O Buffers and Data Latches
360 ILL B1.1
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
EEPROM
Cell Array
Control Logic
FUNCTIONAL BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
360 ILL F01.2
Standard Pinout
Top View
Die Up
SST39LF200A/400A/800A
SST39VF200A/400A/800A
SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF400A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF800A SST39LF/VF200A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
SST39LF/VF400A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
SST39LF/VF800A
7. SST39LF800A ; Multi Purpose Flash

1-1Samsung Electronics
1. Alignment and Adjustments
1-1Tuner
FM THD Adjustment
Output
Output 28 dB( dB)
60 dB
Minumum Distortion (0.4% below)
(Figure 1-1)
SSG FREQ.
Adjustment
point
(FD)
98 MHz
FM DETECTOR COIL
FM Search Level Adjustment
Adjust SVR1 so that “TUNED” of FLT
is lighted (Figure 1-2)
Figure1-2 FM Auto Search Level Adjustment
*Adjust FM S.S.G level to 28dB
Figure1-1 IF CENTER and THD Adjustment
SSG FREQ.
Adjustment
point
(SVR3)
98 MHz
BEACON
SENSITIVITY
SEMI-VR(20K ) FM S.S.G GND
28 dB
FM S.S.G
Output
GND
Speaker
Terminal
FM
Antenna
Terminal
Distortion Meter
Input
SET
Input
output
Oscilloscope
FM IN
FM Antenna
SET
20 k
OUTPUT
AM SSG
450KHZ
INPUT
AM ANT
IN
Speaker Terminal
60cm
AM IF
VTVM Oscilloscope
AM(MW) I.F Adjustment
Maximum output (Figure 1-3)
SSG FREQ.
Frequency
Adjustment
point
450 kHz
522 kHz
AA
Figure1-3 AM I.F Adjustment
OUTPUT
* Adjustment Location of Tuner PCB
AM(MW) OSC
Adjustment
Output 1~7.0 V
Received FREQ.
Adjustment
point
522~1611 KHz
MO
AM(MW) RF
Adjustment
ITEAM
594 KHz
MA
Maximum
Output(Fig1-4)
TESTER
MAIN
PCB VT GND
LW OSC
Adjustment
146~290 KHz
LO
2~7.0 V
AM(MW) RF
Adjustment
150 KHz
LA
Maximum
Output(Fig1-4)

Samsung Electronics 9-1
9.TroubleShooting
9-1 Main