Samsung HT-DM150 User manual
DVD RECEIVER AMP
HT-DM150
HT-DM150J
HT-DM550
SERVICEManual
DVD RECEIVER AMP SYSTEM CONTENTS
1. Alignment and Adjustments
2. Exploded Views and Parts List
3. Electrical Parts List
4. Block Diagrams
5. PCB Diagrams
6.Wiring Diagram
7. Schematic Diagrams
8. IC block Diagrams
9.Troubleshooting
- Confidential -
* NOTE !
HT-DM150J (SAMSUNG) = SAMSUNG HT-DM150 DVD Receiver AMP + JBL Speaker System
So, Service of HT-DM150J Speaker System must be performed by JBL Service Center.
Samsung Electronics 8-1
8. IC Block Diagrams
8-1 Main
1. AK4355
GENERAL
GENERAL
DESCRIPTION
ESCRIPTION
The AK4355 offers the perfect mix for cost and performance based multi-channel
The AK4355 offers the perfect mix for cost and performance based multi-channel
audio systems. AKM's
audio systems. AKM's
advanced multi-bit architecture delivers a ide dynamic range
advanced multi-bit architecture delivers a ide dynamic range
and lo outband noise. The AK4355 has
lo outband noise. The AK4355 has
full differential SCF outputs, removing the need for AC coupling capacitors and
full differential SCF outputs, removing the need for AC coupling capacitors and
increasing performance
increasing performance
for systems ith excessive clock jitter. The 24 Bit ord length and 192kHz sampl
for systems ith excessive clock jitter. The 24 Bit ord length and 192kHz sampl
ing rate make this part
ing rate make this part
ideal for a ide range of application including DVD-Audio.
ideal for a ide range of application including DVD-Audio.
FEATURES
FEATURES
Sampling Rate: 8kHz to 92kHz
Sampling Rate: 8kHz to 92kHz
24Bit 8 times Digital Filter with Slow roll-off option
24Bit 8 times Digital Filter with Slow roll-off option
THD+N:
THD+N:
-90dB
-90dB
DR, S/N:
DR, S/N:
06dB
06dB
High Tolerance to Clock Jitter
High Tolerance to Clock Jitter
Low Distortion Differential Output
Low Distortion Differential Output
Digital De-emphasis for 32, 44. & 48kHz sampling
Digital De-emphasis for 32, 44. & 48kHz sampling
Zero Detect Pin
Zero Detect Pin
Channel Independent Digital Attenuator with soft-transition
Channel Independent Digital Attenuator with soft-transition
Soft Mute
Soft Mute
I/F format: 24-Bit MSB justified, 24/20/ 6-Bit LSB
I/F format: 24-Bit MSB justified, 24/20/ 6-Bit LSB
justified or I
justified or I
2S
Master Clock
Master Clock
Normal Speed: 256fs, 384fs, 5 2fs or 768fs
Normal Speed: 256fs, 384fs, 5 2fs or 768fs
Double Speed:
Double Speed:
28fs, 92fs, 256fs or 384fs
28fs, 92fs, 256fs or 384fs
Quad Speed:
Quad Speed:
28fs, 92fs
Power Supply:
Power Supply:
4.75 to 5.25V
4.75 to 5.25V
28pin VSOP Package
28pin VSOP Package
SCF DAC DATT
DZF
LOUT1+
LOUT1-
SCF DAC DATT
ROUT1+
ROUT1-
SCF DAC DATT
LOUT2+
LOUT2-
SCF DAC DATT
ROUT2+
ROUT2-
SCF DAC DATT
LOUT3+
LOUT3-
SCF DAC DATT
ROUT3+
ROUT3-
Audio
I/F
Control
Register
AK4355
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
CSN
CCLK
CDTI
92kHz 24-Bit 6ch DAC for DVD-Audio
AK4355
8-2 Samsung Electronics
2.TDA7440D
TDA7440D
TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUTMULTIPLEXER
- 4 STEREO INPUTS
- SELECTABLEINPUT GAINFOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUMECONTROL IN 1.0dB STEPS
TWOSPEAKER ATTENUATORS:
- TWOINDEPENDENTSPEAKERCONTROL
IN 1.0dBSTEPS FOR BALANCEFACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIALBUS
DESCRIPTION
The TDA7440D is a volume tone (bass and
treble) balance (Left/Right) processor for quality
audio applicationsin Hi-Fisystems.
Selectable input gain is provided. Control of all
the functionsis accomplishedby serialbus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained
[
0/30dB
0/30dB
2dB STEP
MUXOUTL INL
VOLUME
VOLUME
TREBLE
TREBLE
TREBLE(L)
MUXOUTR INR TREBLE(R)
BOUT(L)
SPKR
ATT
ATT
LEFT LOUT
SCL
SDA
DIG_GND
ROUT
D98AU883
D98AU883
I2CBUS DECODER + LATCHES
100K
100K
100K
100K
G
L-IN1
L-IN2
L-IN3
L-IN4
100K
100K
100K
100K
R-IN1
R-IN2
R-IN3
R-IN4
G
INPUT
MULTIPLEXER
MULTIPLEXER
+ GAIN
BASS
BIN(L)
BASS SPKR
ATT
ATT
RIGHT
BOUT(R)BIN(R)
SUPPLY
CREF
AGND
VS
27
4
5
6
7
3
2
1
28
21
22
20
26
24
25
10 11 19 12 13 23
8 9 18 14 15
RB
RB
VREF
REF
BLOCK DIAGRAM
ORDERING NUMBER: TDA7440D
SO28
Samsung Electronics 8-3
TDA7449L
LOW COST
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUTMULTIPLEXER
- 2 STEREO INPUTS
- SELECTABLEINPUT GAINFOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES
ONE STEREO OUTPUT
VOLUMECONTROL IN 1.0dB STEPS
TWOSPEAKER ATTENUATORS:
- TWOINDEPENDENTSPEAKERCONTROL
IN 1.0dBSTEPS FOR BALANCEFACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIALBUS
DESCRIPTION
The TDA7449L is a volume control and balance
(Left/Right) processor for quality audio applica-
tions in TV systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
[
0/30dB
2dB STEP
MUXOUTL
VOLUME
VOLUME
MUXOUTR
SPKR ATT
LEFT LOUT
SCL
SDA
DIG_GND
ROUT
D98AU868
I2CBUS DECODER + LATCHES
100K
100K G
L-IN1
L-IN2
100K
100K
R-IN1
R-IN2 G
INPUT
MULTIPLEXER
MULTIPLEXER
+ GAIN
SPKR ATT
RIGHT
SUPPLY
CREF
AGND
VS
5
8
9
7
6
19
20
18
4
2
3
11 1
10
VREF
REF
BLOCK DIAGRAM
ORDERING NUMBER: TDA7449L
DIP20
3.TDA7449L
8-4 Samsung Electronics
4. M62463AFP
Samsung Electronics 8-5
8-6 Samsung Electronics
8-2 DVD
1. ZIVA- 5 DVD CONTROLER
Figure 1 ZiVA-5 controller Pinout (208-pin PQFP)
Table 1 ZiVA-5 controller Pin List
Pin No. Pin Name I/O Voltage I/O Type
1 VDDP 3.3V ó
2 HA1 3.3V* I/O
3 HA15 3.3V* I/O
4 HA14 3.3V* I/O
5 HA13 3.3V* I/O
6 HA12 3.3V* I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD_3.3
HA1
HAD15
HAD14
HAD13
HAD12
HAD11
HAD10
HAD9
HAD8
HAD7
VDD_3.3
VSS
HAD6
HAD5
HAD4
HAD3
HAD2
HAD1
VDD_3.3
VSS
HAD0
HDTACK/WAIT
HIRQ0
UDS/UWE
LDS/LWE
R/W
IRRX1
VSS
VDDC
VSS
VDD_3.3
MADDR9
MADDR8
MADDR7
MADDR6
MADDR5
MADDR4
MADDR3
MADDR2
MADDR1
MADDR0
VSS
VDD_3.3
MADDR10
MADDR11
BA1
BA0
MCS0
MCS1
MRAS
MCAS
DA-IEC958
DA-DATA3
DA-DATA2
VSS
VDD_3.3
DA-DATA1
DA-DATA0
DA-BCK
DA-LRCK
DA-XCK
VSS
VDDC
A_VSS1
A_VDD1
A_VDD2
A_VSS2
XVDD
XTAL/VCLK216BP
XTAL
XVSS
VSS_RREF
VDAC_RREF
VDD_RREF
VDAC_DVDD
VDAC_DVSS
VDAC_0
VDAC_VDD0
VDAC_0B
VDAC_1
VDAC_VDD1
VDAC_1B
VDAC_2
VDAC_VDD2
VDAC_2B
VDAC_3
VDAC_VDD3
VDAC_3B
VDAC_4
VDAC_VDD4
VDAC_4B
HSYNC/IRQ2
VDATA0
VDATA1
VDATA2
VSS
VDD_3.3
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7
VCLK
DAI-DATA
DAI-BCK/SYSCLKBP
DAI-LRCK/IEC958BP
I2C_CL
I2C_DA
RTS1
RXD1
TXD1
CTS1
VSS
VDD_3.3
SD-DATA7
SD-DATA6
SD-DATA5
SD-DATA4
VSS
VDDC
SD-DATA3
SD-DATA2
SD-DATA1
SD-DATA0
SD-REQ
SD-EN
VSS
VDD_3.3
SD-ERROR
SD-CLK
VSYNC/HIRQ1
RTS2/SPI_CLK
RXD2/SPI_MISO
TXD2/SPI_MOSI
CTS2/SPI_CS
VDD_5
HCS4
HCS3
HCS2
HCS1
HCS0
VSS
VDD_3.3
TRST
TDO
TDI
TMS
TCK
RESET
ALE
VSS
VDDC
HAD3
HAD2
VSS
ZiVA-5 Controller
Top View
VDD_3.3
VSS
MDATA31
MDATA30
MDATA29
MDATA28
VDD_3.3
MDQM3
VSS
MDATA27
MDATA26
MDATA25
MDATA24
MDATA23
MDATA22
MDATA21
MDATA20
VDD_3.3
MDQM2
VSS
MDATA19
MDATA18
MDATA17
MDATA16
VDDC
VSS
MDATA15
MDATA14
MDATA13
MDATA12
VDD_3.3
MDQM1
VSS
MDATA11
MDATA10
MDATA9
MDATA8
MDATA7
MDATA6
MDATA5
MDATA4
VDD_3.3
MDQM0
VSS
MDATA3
MDATA2
MDATA1
MDATA0
MCLK
VDD_3.3
VSS
MWE
Samsung Electronics 8-7
7 HA11 3.3V* I/O
8 HA10 3.3V* I/O
9 HA9 3.3V* I/O
10 HA8 3.3V* I/O
11 HA7 3.3V* I/O
12 VDDP 3.3V ó
13 GNDP GROUND ó
14 HA6 3.3V* I/O
15 HA5 3.3V* I/O
16 HA4 3.3V* I/O
17 HA3 3.3V* I/O
18 HA2 3.3V* I/O
19 HA1 3.3V* I/O
20 VDDP 3.3V ó
21 GNDP GROUND ó
22 HA0 3.3V* I/O
23 HDTACK/WAIT 3.3V* I/OD
24 HIRQ0 3.3V* I/O
25 HUDS/UWE 3.3V* I/O
26 HLDS/LWE 3.3V* I/O
27 HREAD 3.3V* I/O
28 IRRX1/GPIO[0] 3.3V* I
29 GND GROUND ó
30 VDD 1.8V ó
31 GND25 GROUND ó
32 VDD25 3.3V ó
33 MA9 3.3V O
34 MA8 3.3V O
35 MA7 3.3V O
36 MA6 3.3V O
37 MA5 3.3V O
38 MA4 3.3V O
39 MA3 3.3V O
40 MA2 3.3V O
41 MA1 3.3V O
42 MA0 3.3V O
43 GND25 GROUND ó
44 VDD25 3.3V ó
45 MA10 3.3V O
46 MA11 3.3V O
47 BA1 3.3V O
48 BA0 3.3V O
49 MCS0 3.3V O
50 MCS1 3.3V O
51 MRAS 3.3V O
52 MCAS 3.3V O
53 MWE 3.3V O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
Confid
Advance Pr
54 GND25 GROUND ó
55 VDD25 3.3V ó
56 MCLK O
57 MD0 3.3V I/O
58 MD1 3.3V I/O
59 MD2 3.3V I/O
60 MD3 3.3V I/O
61 GND25 GROUND ó
62 MDQM0 3.3V O
63 VDD25 3.3V ó
64 MD4 3.3V I/O
65 MD5 3.3V I/O
66 MD6 3.3V I/O
67 MD7 3.3V I/O
68 MD8 3.3V I/O
69 MD9 3.3V I/O
70 MD10 3.3V I/O
71 MD11 3.3V I/O
72 GND25 GROUND ó
73 MDQM1 3.3V O
74 VDD25 3.3V ó
75 MD12 3.3V I/O
76 MD13 3.3V I/O
77 MD14 3.3V I/O
78 MD15 3.3V I/O
79 GND GROUND ó
80 VDD 1.8V ó
81 MD16 3.3V I/O
82 MD17 3.3V I/O
83 MD18 3.3V I/O
84 MD19 3.3V I/O
85 GND25 GROUND ó
86 MDQM2 3.3V O
87 VDD25 3.3V ó
88 MD20 3.3V I/O
89 MD21 3.3V I/O
90 MD22 3.3V I/O
91 MD23 3.3V I/O
92 MD24 3.3V I/O
93 MD25 3.3V I/O
94 MD26 3.3V I/O
95 MD27 3.3V I/O
96 GND25 GROUND ó
97 MDQM3 3.3V O
98 VDD25 3.3V ó
99 MD28 3.3V I/O
100 MD29 3.3V I/O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
8-8 Samsung Electronics
101 MD30 3.3V I/O
102 MD31 3.3V I/O
103 GND25 GROUND ó
104 VDD25 3.3V ó
105 VCLK 3.3V* I/O
106 VDATA7/GPIO[1] 3.3V* I/O
107 VDATA6/GPIO[2] 3.3V* I/O
108 VDATA5/GPIO[3] 3.3V* I/O
109 VDATA4/GPIO[4] 3.3V* I/O
110 VDATA3/GPIO[5] 3.3V* I/O
111 VDDP 3.3V ó
112 GNDP GROUND ó
113 VDATA2/GPIO[6] 3.3V* I/O
114 VDATA1/GPIO[7] 3.3V* I/O
115 VDATA0/GPIO[8] 3.3V* I/O
116 HSYNC/HIRQ2/GPIO[9] 3.3V* I/O
117 VDAC_4B ANALOG O
118 VDAC_VDD4 3.3VANALOG ó
119 VDAC_4 ANALOG O
120 VDAC_3B ANALOG O
121 VDAC_VDD3 3.3VANALOG ó
122 VDAC_3 ANALOG O
123 VDAC_2B ANALOG O
124 VDAC_VDD2 3.3VANALOG ó
125 VDAC_2 ANALOG O
126 VDAC_1B ANALOG O
127 VDAC_VDD1 3.3VANALOG ó
128 VDAC_1 ANALOG O
129 VDAC_0B ANALOG O
130 VDAC_VDD0 3.3VANALOG ó
131 VDAC_0 ANALOG O
132 VDAC_DVSS GROUND
133 VDAC_DVDD 3. 3V
134 VAC_REFVDD 3.3V
135 VDAC_REF ANALOG I
136 VDAC_REFVSS GROUND
137 XVSS GROUND
138 XOUT ANALOG
139 XIN/bypassclk_216 ANALOG
140 XVDD 3.3V
141 AVSS2 GROUND
142 AVDD2 3.3V
143 AVDD1 3.3V
144 AVSS1 GROUND
145 VDD 1.8V ó
146 GND GROUND ó
147 XCK 3.3V* I/O
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
148 LRCK 3.3V* O
149 BCK 3.3V* O
150 ADATA0/GPIO[10] 3.3V* O
151 ADATA1/GPIO[11] 3.3V* O
152 VDDP 3.3V ó
153 GNDP GROUND ó
154 ADATA2/GPIO[12] 3.3V* O
155 ADATA3/GPIO[13] 3.3V* O
156 IEC958/GPIO[14] 3.3V* O
157 DAI_DATA/GPIO[15] 3.3V* I
158 DAI_BCK/bypass_sysclk/
GPIO[16] 3.3V* I
159 DAI_LRCK/iec958bp/GPIO[17] 3.3V* I
160 I2C_CL/GPIO[18] 3.3V* I/OD
161 I2C_DA/GPIO[19] 3.3V* I/OD
162 RTS1/GPIO[20] 3.3V* O
163 RXD1/GPIO[21] 3.3V* I
164 TXD1/GPIO[22] 3.3V* O
165 CTS1/GPIO[23] 3.3V* I
166 GNDP GROUND ó
167 VDDP 3.3V ó
168 SDDATA7/VDATA2[7]/
HDMARQ/GPIO[24] 3.3V I
169 SDDATA6/VDATA2[6]/HXCVR_
EN/
GPIO[25]
3.3V* I
170 SDDATA5/VDATA2[5]/
HDMACK/GPIO[26] 3.3V* I
171 SDDATA4/VDATA2[4]/GPIO[27] 3.3V* I
172 GND GROUND ó
173 VDD 1.8V ó
174 SDDATA3/VDATA2[3]/GPIO[28] 3.3V* I
175 SDDATA2/VDATA2[2]/GPIO[29] 3.3V* I
176 SDDATA1/VDATA2[1]/GPIO[30] 3.3V* I
177 SDDATA0/VDATA2[0]
/GPIO[31] 3.3V* I
178 SDREQ/GPIO[32] 3.3V* O
179 SDEN/GPIO[33] 3.3V* I
180 GNDP GROUND ó
181 VDDP 3.3V ó
182 SDERROR/GPIO[34] 3.3V* I
183 SDCLK/GPIO[35] 3.3V* I
184 VSYNC/HIRQ1/GPIO[36] 3.3V* I/O
185 RTS2/SPI_CLK/GPIO[37] 3.3V* O
186 RXD2/SPI_MISO/GPIO[38] 3.3V* I
187 TXD2/SPI_MOSI/GPIO[39] 3.3V* O
188 CTS2/SPI_CS/GPIO[40] 3.3V* I
189 VNW 5V ó
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
Samsung Electronics 8-9
Note:TheZiVA-5coreoperatesat1.8V±10%.MostI/Ointerfacepinscanbeinterfacedwith3.3-Vor5-VdevicesdependingonthevoltageappliedtotheVDDpinsassociated
with them. Refer to the Application Note for more information.
190 HCS4/GPIO[41] 3.3V* I
191 HCS3/GPIO[42] 3.3V* I
192 HCS2/GPIO[43] 3.3V* I
193 HCS1 3.3V* I/O
194 HCS0 3.3V* I/O
195 GNDP GROUND ó
196 VDDP 3.3V ó
197 TRST 3.3V* I
198 TDO 3.3V* O
199 TDI/GPI[0] 3.3V* I
200 TMS/GPI[1] 3.3V* I
201 TCK 3.3V* I
202 RESET 3.3V* I
203 ALE 3.3V* I/O
204 GND GROUND ó
205 VDD 1.8V ó
206 HA3 3.3V* I
207 HA2 3.3V* I
208 GNDP GROUND ó
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
13.5 MHz Crystal
Bus Interface Unit
IR IDC
SPARC
Microprocessor
Phase
Lock
Loop
ATAPI
SDRAM Controller
System Control Bus
Audio
Output
Unit
GPIO SPI
UART1& 2
ZiVA
A/V Core
Audio
Input Unit
Decryption
Track Buffer
Processor Interlaced/
Prog
Prog
ressive
Video
Encoder
Five 10-bit
Video
DACs
Graphics
Engine
CCIR 656
ASYNC BUS
32-128Mbit
8-10 Samsung Electronics
BLOCK DIAGRAM
DQ0
DQ0
DQ31
DQ31
DQM0~3
DQM0~3
CLK
CLK
CKE
CKE
A10
A10
CLOCK
CLOCK
BUFFER
BUFFER
COMMAND
COMMAND
DECODER
DECODER
ADDRESS
ADDRESS
BUFFER
BUFFER
REFRESH
REFRESH
COUNTER
COUNTER
COLUMN
COLUMN
COUNTER
COUNTER
CONTROL
CONTROL
SIGNAL
SIGNAL
GENERATOR
GENERATOR
MODE
MODE
REGISTER
REGISTER
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #2
BANK #2
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #0
BANK #0
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #3
BANK #3
DATA CONTROL
DATA CONTROL
CIRCUIT
CIRCUIT
DQ
DQ
BUFFER
BUFFER
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #1
BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
A0
A0
A9
A9
BS0
BS0
BS1
BS1
CS
CS
RAS
RAS
CAS
CAS
WE
WE
2.W986432DH
Samsung Electronics 8-11
3. M6759 ; 8BIT MTP micro controller
4. M5701/M5705 ; DVD ROM controller
M5701/M5705
8-12 Samsung Electronics
Pin Assignments
Pin Definitions
Internal Block Diagram
Pin Number Pin Name I/O Pin Function Description
1 GND - Ground
2V
O1 O Output 1
3V
CTL I Motor speed control
4V
IN1 I Input 1
5V
IN2 I Input 2
6SV
CC - Supply voltage (Signal)
7PV
CC - Supply voltage (Po er)
8V
O2 O Output 2
1
2
5
6
7
8
GND
VO1
VCTL
VIN1 VIN2
SVCC
PVCC
VO2
3
4
FAN8082
DRIVER OUT
LOGIC SWITCH
1
2
5
6
7
8
GND
VO1
VCTL
VIN1 VIN2
SVCC
PVCC
VO2
3
4
TSD
PRE DRIVER
BIAS
5. FAN8082
Samsung Electronics 8-13
6. M11B416256A
8-14 Samsung Electronics
Y-Decoder
I/O Buffers and Data Latches
360 ILL B1.1
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
EEPROM
Cell Array
Control Logic
FUNCTIONAL BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
360 ILL F01.2
Standard Pinout
Top View
Die Up
SST39LF200A/400A/800A
SST39VF200A/400A/800A
SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF400A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF800A SST39LF/VF200A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
SST39LF/VF400A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
SST39LF/VF800A
7. SST39LF800A ; Multi Purpose Flash
Samsung Electronics 8-15
8-3. HT-DM150/550 MICOM PORT ASSIGNMENT
1-1Samsung Electronics
1. Alignment and Adjustments
1.Tuner
FM THD Adjustment
Output
Output 28 dB(±2dB)
60 dB
Minumum Distortion (0.4% below)
(Figure 1-1)
SSG FREQ.
Adjustment
point
(FM DET)
98 MHz
FM DETECTOR COIL
FM Search Level Adjustment
Adjust SVR1 so that “TUNED” of FLT is
lighted (Figure 1-2)
Figure1-2 FM Auto Search Level Adjustment
*Adjust FM S.S.G level to 28dB
Figure1-1 IF CENTER and THD Adjustment
SSG FREQ.
Adjustment
point
(SVR1)
98 MHz
BEACON
SENSITIVITY
SEMI-VR(10KΩ)FM S.S.G GND
28 dB
FM S.S.G
Output
GND
Speaker
Terminal
FM
Antenna
Terminal
Distortion Meter
Input
SET
Input
output
Oscilloscope
FM IN
FM Antenna
SET
10 kΩ
OUTPUT
AM SSG
450KHZ
INPUT
AM ANT
IN
Speaker Terminal
60cm
AM IF
VTVM Oscilloscope
AM(MW) I.F Adjustment
Maximum output (Figure 1-3)
SSG FREQ.
Frequency
Adjustment
point
450 kHz
522 kHz
AM IF
Figure1-3 AM I.F Adjustment
OUTPUT
* Adjustment Location of Tuner PCB
AM(MW) OSC
Adjustment
Output 1~7.0 V
Received FREQ.
Adjustment
point
522~1611 KHz
MO
AM(MW) RF
Adjustment
ITEAM
594 KHz
MA
Maximum
Output (Fig1-4)
Fig 1-4 OSC Voltage
AM(MW) RF
Adjustment
150 KHz
LA
Maximum
Output (Fig1-4)
Samsung Electronics 9-1
9.TroubleShooting
9-1-1 Main; HT-DM150
9-2 Samsung Electronics
Samsung Electronics 9-3
Other manuals for HT-DM150
7
This manual suits for next models
2
Table of contents
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