Samsung SAM88RCRI S3C9442 User manual

S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW
1-1
1PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9442/C9444/C9452/C9454 MICROCONTROLLER
The S3C9442/C9444/C9452/C9454 single-chip 8-bit microcontroller is designed for useful A/D converter , SIO
application field. The S3C9442/C9444/C9452/C9454 uses powerful SAM88RCRI CPU and
S3C9442/C9444/C9452/C9454 architecture. The internal register file is logically expanded to increase the on-
chip register space.
The S3C9442/C9444/C9452/C9454 has 2K/4K bytes of on-chip program ROM and 208 bytes of RAM. The
S3C9442/C9444/C9452/C9454 is a versatile general-purpose microcontroller that is ideal for use in a wide range
of electronics applications requiring simple timer/counter, PWM. In addition, the S3C9442/C9444/C9452/C9454’s
advanced CMOS technology provides for low power consumption and wide operating voltage range.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
—Three configurable I/O ports (18 pins)
—Four interrupt sources with one vector and one interrupt level
—One 8-bit timer/counter with time interval mode
—Analog to digital converter with nine input channels and 10-bit resolution
—One 8-bit PWM output
The S3C9442/C9444/C9452/C9454 microcontroller is ideal for use in a wide range of electronic applications
requiring simple timer/counter, PWM, ADC. S3C9452/C9454 is available in a 20/16-pin DIP and a 20-pin SOP
package. S3C9452/C9454 is available in a 8-pin and a 8-pin SOP package.
MTP
The S3F9444/F9454 is an MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454
microcontroller. The S3F9444/F9454 has on-chip 4-Kbyte multi-time programmable flash ROM instead of
masked ROM. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in
D.C. electrical characteristics and in pin configuration.

PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454
1-2
FEATURES
CPU
•SAM88RCRI CPU core
•The SAM88RCRI core is low-end version of the
current SAM87 core.
Memory
•2/4-Kbyte internal program memory
•208-byte general purpose register area
Instruction Set
•41 instructions
•The SAM88RCRI core provides all the SAM87
core instruction except the word-oriented
instruction, multiplication, division, and some
one-byte instruction.
Instruction Execution Time
•400 ns at 10 MHz fOSC (minimum)
Interrupts
•4 interrupt sources with one vector
•One interrupt level
General I/O
•Three I/O ports (Max 18 pins)
•Bit programmable ports
8-bit High-speed PWM
•8-bit PWM 1-ch (Max: 156 kHz)
•6-bit base + 2-bit extension
Built-in reset Circuit
•Low voltage detector for safe reset
Timer/Counters
•One 8-bit basic timer for watchdog function
•One 8-bit timer/counter with time interval modes
A/D Converter
•Nine analog input pins
•10-bit conversion resolution
Oscillation Frequency
•1 MHz to 10 MHz external crystal oscillator
•Maximum 10 MHz CPU clock
•Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in
VDD = 5 V
Operating Temperature Range
•– 40°C to + 85°C
Operating Voltage Range
•2.0 V (LVR Level) to 5.5 V
Smart Option
Package Types
•S3C9452/C9454:
–20-DIP-300A
–20-SOP-375
–16-DIP-300A
•S3C9442/C9444
–8-DIP-300
–8-SOP-225

S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
88RCRI
SAMRI CPU
Port I/O and
Interrupt Control
2 KB ROM
4 KB ROM 208 Byte Register file
Timer 0
ADC
PWM
X IN
X OUT
OSC
Basic
Timer
ADC0-ADC8
P0.6/PWM
Port 0
Port 2
Port 1
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
P0.7/ADC7
...
P1.0
P1.1
P1.2
P2.0/T0
P2.1
P2.6
...
NOTE: P1.2 is used as input only
Figure 1-1. Block Diagram

PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454
1-4
PIN ASSIGNMENTS
S3C9452/C9454
(20-DIP-300A/
20-SOP-375)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VSS
XIN/P1.0
XOUT/P1.1
RESET /P1.2
P2.0/T0
P2.1
P2.2
P2.3
P2.4
P2.5
VDD
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
P0.3/ADC3
P0.4/ADC4
P0.5/ADC5
P0.6/ADC6/PWM
P0.7/ADC7
P2.6/ADC8/CLO
Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP Package)

S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW
1-5
S3C9452/C9454
(16-DIP-300A)
VDD
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
P0.3/ADC3
P0.4/ADC4
P0.5/ADC5
P0.6/ADC6/PWM
16
15
14
13
12
11
10
9
VSS
XIN/P1.0
XOUT/P1.1
RESET /P1.2
P2.0/T0
P2.1
P2.2
P2.3
1
2
3
4
5
6
7
8
Figure 1-3. Pin Assignment Diagram (16-Pin DIP Package)
S3C9442/C9444
(8-DIP-300
8-SOP-225)
VDD
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
8
7
6
5
VSS
XIN/P1.0
XOUT/P1.1
RESET /P1.2
1
2
3
4
Figure 1-4. Pin Assignment Diagram (8-Pin DIP/SOP Package)

PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454
1-6
PIN DESCRIPTIONS
Table 1-1. S3C9452/C9454 Pin Descriptions
Pin
Name In/Out Pin Description Pin Type Share Pins
P0.0–P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or
push-pull output. Pull-up resistors are assignable by
software. Port0 pins can also be used as A/D converter
input, PWM output or external interrupt input.
E-1 ADC0–ADC7
INT0/INT1
PWM
P1.0–P1.1 I/O Bit-programmable I/O port for Schmitt trigger input or
push-pull, open-drain output. Pull-up resistors or pull-down
resistors are assignable by software.
E-2 XIN, XOUT
P1.2 ISchmitt trigger input port BRESET
P2.0–P2.6 I/O Bit-programmable I/O port for Schmitt trigger input or
push-pull, open-drain output. Pull-up resistors are
assignable by software.
E
E-1
–
ADC8/CLO
T0
XIN, XOUT –Crystal/Ceramic, or RC oscillator signal for system clock. P1.0–P1.1
RESET IInternal LVR or External RESET BP1.2
VDD, VSS –Voltage input pin and ground –
CLO OSystem clock output port E-1 P2.6
INT0–INT1 IExternal interrupt input port E-1 P0.0, P0.1
PWM O8-Bit high speed PWM output E-1 P0.6
T0 OTimer0 match output E-1 P2.0
ADC0–ADC8 IA/D converter input E-1
EP0.0–P0.7 P2.6

S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW
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PIN CIRCUITS
VDD
IN
N-channel
P-channel
Figure 1-5. Pin Circuit Type A
IN
Figure 1-6. Pin Circuit Type B
VDD
Out
Output
DIsable
Data
Figure 1-7. Pin Circuit Type C
I/O
Output
Disable
Data Circuit
Type C
Pull-up
Enable
VDD
Digital
Input
Figure 1-8. Pin Circuit Type D

PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454
1-8
VDD
I/O
Digital
Input
P-CH
VDD
Open-drain
Enable Pull-up
enable
Analog Input
Enable
ADC
Output Disable
(Input Mode)
Data
M
U
X
Alternative
Output
P2.x
P2CONH
P2CONL
N-CH
Figure 1-9. Pin Circuit Type E
VDD
I/O
Digital Input
P-CH
VDD Pull-up
enable
Output Disable
(Input Mode)
Data
M
U
X
Alternative
Output
P0.x
P0CONH
N-CH
Analog Input
Enable
ADC
Interrupt Input
Figure 1-10. Pin Circuit Type E-1

S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW
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VDD
I/O
XIN
XOUT
VDD
Open-drain
Enable
Output Disable
(Input Mode)
P1.x
Digital
Input
Pull-up
enable
Pull-down
enable
Figure 1-11. Pin Circuit Type E-2

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES
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2ADDRESS SPACES
OVERVIEW
The S3C9442/C9444/C9452/C9454 microcontroller has two kinds of address space:
—Internal program memory (ROM)
—Internal register file
A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the internal register file.
The S3C9442/C9444/C9452/C9454 have 2-Kbytes or 4-Kbytes of mask-programmable on-chip program
memory: which is configured as the Internal ROM mode, all of the 4-Kbyte internal program memory is used.
The S3C9442/C9444/C9452/C9454 microcontroller has 208 general-purpose registers in its internal register file.
Twenty-six bytes in the register file are mapped for system and peripheral control functions.

ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454
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PROGRAM MEMORY (ROM)
Normal Operating Mode
The S3C9442/C9444/C9452/C9454 have 2-Kbytes (locations 0H–07FFH) or 4-Kbytes (locations 0H–0FFFH) of
internal mask-programmable program memory.
The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address.
Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory.
3CH, 3DH, 3EH, 3FH is used smart option ROM cell.
The program reset address in the ROM is 0100H.
4.095
2,047
1000H
0100H
60
4-Kbyte
Program
Memory
Area
Interrupt
Vector
64
256
0040H
003CH
0000H
(Decimal) (HEX)
07FFH
2-Kbyte
Program
Memory
Area
Program Start
0002H
0001H
2
1
0
Smart option ROM cell
Figure 2-1. Program Memory Address Space

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES
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Smart Option
Smart option is the ROM option for starting condition of the chip.
The ROM addresses used by smart option are from 003CH to 003FH. The S3C9442/C9444/C9452/9454 only use
003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default
value of ROM is FFH (LVR enable, internal RC oscillator).
ROM Address: 003DH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Must be initialized to 00H.
ROM Address: 003CH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Must be initialized to 00H.
ROM Address: 003EH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
LVR enable/disable bit:
0 = Disable
1 = Enable LVR level selection bits:
11001 = 2.3 V
10010 = 3.0 V
01100 = 3.9 V
Not used
ROM Address: 003FH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Oscillator selection bits:
00 = External crystal/
ceramic oscillator
01 = External RC
10 = Internal RC (0.5 MHz in V DD = 5 V)
11 = Internal RC (3.2 MHz in V DD = 5 V)
Not used.
NOTES:
1. When you use external oscillator, P1.0, P1.1 must be set to output
port to prevent current consumption.
2. The value of unused bits of 3EH, 3FH is don't care.
3. When LVR is enabled, LVR level must be set to appropriate value,
not default value.
Figure 2-2. Smart Option

ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454
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++PROGRAMMING TIP — Smart Option Setting
;<< Interrupt Vector Address >>
ORG 0000H
Vector 00H, INT_9454 ; S3C9454 has only one interrupt vector
;<< Smart Option Setting >>
ORG 003CH
DB 00H ;003CH, must be initialized to 0.
DB 00H ;003DH, must be initialized to 0.
DB 0E7H ;003EH, enable LVR (2.3 V)
DB 03H ;003FH, Internal RC (3.2 MHz in VDD = 5 V)
;<< Reset >>
ORG 0100H
RESET; DI
•
•
•

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES
2-5
REGISTER ARCHITECTURE
The upper 64-bytes of the S3C9442/C9444/C9452/C9454's internal register file are addressed as working
registers, system control registers and peripheral control registers. The lower 192-bytes of internal register
file(00H–BFH) is called the general purpose register space. 234 registers in this space can be accessed; 208 are
available for general-purpose use.
For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by
additional register pages at the general purpose register space (00H–BFH: page0). This register file expansion is
not implemented in the S3C9442/C9444/C9452/C9454, however.
The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in
Table 2-1.
Table 2-1. Register Type Summary
Register Type Number of Bytes
CPU and system control registers 11
Peripheral, I/O, and clock control and data registers 15
General-purpose registers (including the 16-bit
common working register area) 208
Total Addressable Bytes 234

ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454
2-6
FFH
C0H
~
BFH
00H
192 Bytes
64 Bytes of
Common Area
D0H
CFH
E0H
DFH
Working Registers
System Control
Registers
Peripheral Control
Registers
General Purpose
Register File
and Stack Area
Figure 2-3. Internal Register File Organization

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES
2-7
COMMON WORKING REGISTER AREA (C0H–CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
This16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages. However, because the
S3C9442/C9444/C9452/C9454 uses only page 0, you can use the common area for any internal data operation.
The Register (R) addressing mode can be used to access this area
Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the
address of the first 8-bit register is always an even number and the address of the next register is an odd
number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least
significant byte is always stored in the next (+ 1) odd-numbered register.
MSB
Rn
LSB
Rn+1
n = Even address
Figure 2-4. 16-Bit Register Pairs
++ PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples:1. LD 0C2H,40H ;Invalid addressing mode!
Use working register addressing instead:
LD R2,40H ;R2 (C2H) ←the value in location 40H
2. ADD 0C3H,#45H ;Invalid addressing mode!
Use working register addressing instead:
ADD R3,#45H ;R3 (C3H) ←R3 + 45H

ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454
2-8
SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The S3C9442/C9444/C9452/C9454
architecture supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address is always decremented before a push operation and incremented after
a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown
in Figure 2-4.
Stack contents
after a call
instruction
Stack contents
after an
interrupt
Top of
stack Flags
PCH
PCL
PCL
PCH
Top of
stack
Low Address
High Address
Figure 2-5. Stack Operations
Stack Pointer (SP)
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,
the SP value is undetermined.
Because only internal memory space is implemented in the S3C9442/C9444/C9452/C9454, the SP must be
initialized to an 8-bit value in the range 00H–0C0H.
NOTE
In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This
means that a Stack Pointer access invalid stack area. We recommend that a stack pointer is initialized to
C0H to set upper address of stack to BFH.

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES
2-9
++ PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD SP,#0C0H ;SP ← C0H (Normally, the SP is set to C0H by the
; initialization routine)
•
•
•
PUSH SYM ;Stack address 0BFH ← SYM
PUSH R15 ;Stack address 0BEH ← R15
PUSH 20H ;Stack address 0BDH ← 20H
PUSH R3 ;Stack address 0BCH ← R3
•
•
•
POP R3 ;R3 ← Stack address 0BCH
POP 20H ;20H ← Stack address 0BDH
POP R15 ;R15 ← Stack address 0BEH
POP SYM ;SYM ← Stack address 0BFH

S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES
3-1
3ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:
—Register (R)
—Indirect Register (IR)
—Indexed (X)
—Direct Address (DA)
—Relative Address (RA)
—Immediate (IM)

ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454
3-2
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register
addressing differs from Register addressing because it uses an 16-byte working register space in the register file
and an 4-bit register within that space (see Figure 3-2).
dst
Value used in
Instruction Execution
OPCODE OPERAND
8-Bit Register
File Address Point to one
register in register
file
One-Operand
Instruction
(Example)
Sample Instruction:
DEC CNTR ; Where CNTR is the label of an 8-bit register address
Program Memory Register File
Figure 3-1. Register Addressing
dst
OPCODE
4-Bit
Working Register Point to the
working register
(1 of 8)
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2 ; Where R1 and R2 are registers in the currently selected
working register area.
Program Memory
Register File
src 3 LSBs
OPERAND
RP0 or RP1
Selected
RP points to
start of
working
register block
MSB point to
RP0 to RP1
Figure 3-2. Working Register Addressing