Samsung S3F84B8 User manual

S3F84B8
8-bit CMOS Microcontrollers
Revision 1.00
June 2010
U
Us se er r' 's s M Ma an nu ua al l
2010 Samsung Electronics Co., Ltd. All rights reserved.

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Revision History
Revision No. Date Description Author(s)
0.00 Sep. 9, 2009 Initial draft Wei Ningning
1.00 April. 30, 2010 Released version Wei Ningning

Table of Contents
1 OVERVIEW OF S3F84B8 MICROCONTROLLER......................................1-1
1.1 S3C8-Series Microcontrollers .................................................................................................................. 1-1
1.1.1 S3F84B8 Microcontroller .................................................................................................................. 1-1
1.1.2 Key Features of S3F84B8 ................................................................................................................ 1-2
1.1.3 Block Diagram of S3F84B8 .............................................................................................................. 1-5
1.1.4 Pin Assignments............................................................................................................................... 1-6
1.1.5 Pin Descriptions................................................................................................................................ 1-7
1.1.6 Pin Circuits........................................................................................................................................ 1-9
2 ADDRESS SPACES....................................................................................2-1
2.1 Overview of Address Spaces................................................................................................................... 2-1
2.2 Internal Program Memory (ROM) ............................................................................................................ 2-2
2.2.1 Smart Option..................................................................................................................................... 2-3
2.3 Register Architecture ............................................................................................................................... 2-4
2.3.1 Register Page Pointer (PP) .............................................................................................................. 2-6
2.3.1.1 Register Set 1 ......................................................................................................................... 2-7
2.3.1.2 Register Set 2 ......................................................................................................................... 2-7
2.3.1.3 Prime Register Space ............................................................................................................. 2-8
2.3.1.4 Working Registers................................................................................................................... 2-9
2.3.2 Using The Register Points (RP) ..................................................................................................... 2-10
2.4 Register Addressing............................................................................................................................... 2-12
2.4.1 Common Working Register Area (C0H–CFH)................................................................................ 2-14
2.4.2 4-Bit Working Register Addressing................................................................................................. 2-15
2.4.3 8-Bit Working Register Addressing................................................................................................. 2-17
2.4.4 System and User Stack .................................................................................................................. 2-19
2.4.4.1 Stack Operations................................................................................................................... 2-19
2.4.4.2 User-defined Stacks.............................................................................................................. 2-19
2.4.4.3 Stack Pointers (SPL, SPH) ................................................................................................... 2-19
3 ADDRESSING MODES...............................................................................3-1
3.1 Overview of Addressing Modes ............................................................................................................... 3-1
3.2 Register (R) Addressing Mode................................................................................................................. 3-2
3.3 Indirect Register (IR) Addressing Mode................................................................................................... 3-3
3.4 Indirect Register (IR) Addressing Mode (Continued)............................................................................... 3-4
3.5 Indirect Register (IR) Addressing Mode (Continued)............................................................................... 3-5
3.6 Indirect Register (IR) Addressing Mode (Concluded) .............................................................................. 3-6
3.7 Indexed (X) Addressing Mode ................................................................................................................. 3-7
3.8 Indexed (X) Addressing Mode (Continued) ............................................................................................. 3-8
3.9 Indexed (X) Addressing Mode (Concluded)............................................................................................. 3-9
3.10 Direct Address (DA) Mode ................................................................................................................... 3-10
3.11 Direct Address (DA) Mode (Continued) ............................................................................................... 3-11
3.12 Indirect Address (IA) Mode .................................................................................................................. 3-12
3.13 Relative Address (RA) Mode ............................................................................................................... 3-13
3.14 Immediate Mode (IM)........................................................................................................................... 3-14
4 CONTROL REGISTERS..............................................................................4-1

4.1 Overview of Control Registers ................................................................................................................. 4-1
4.1.1 ADCON — A/D Converter Control Register: FAH, BANK0.............................................................. 4-5
4.1.2 AMTDATA — Anti-mis-trigger Data Register: F6H, BANK0............................................................. 4-6
4.1.3 BTCON — Basic Timer Control Register: D3H, BANK0 .................................................................. 4-6
4.1.4 BUZCON — BUZ Control Register: F7H, BANK0............................................................................ 4-7
4.1.5 CLKCON — Clock Control Register: D4H, BANK0.......................................................................... 4-8
4.1.6 CMP0CON — Comparator0 Control Register: EAH, BANK0 .......................................................... 4-9
4.1.7 CMP1CON — Comparator1 Control Register: EBH, BANK0 ........................................................ 4-10
4.1.8 CMP2CON — Comparator1 Control Register: ECH, BANK0 ........................................................ 4-11
4.1.9 CMP3CON — Comparator1 Control Register: EDH, BANK0 ........................................................ 4-12
4.1.10 CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0 .................................... 4-13
4.1.11 FLAGS — System Flags Register: D5H, BANK0......................................................................... 4-14
4.1.12 FMCON — Flash Memory Control Register: F5H, BANK1 .......................................................... 4-15
4.1.13 FMSECH — Flash Memory Sector Address Register (High Byte): F7H, BANK1........................ 4-15
4.1.14 FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1 ......................... 4-16
4.1.15 FMUSR — Flash Memory User Programming Enable Register: F6H, BANK1............................ 4-16
4.1.16 IMR — Interrupt Mask Register: DDH, BANK0 ............................................................................ 4-17
4.1.17 IPH — Instruction Pointer (High Byte): DAH, BANK0 .................................................................. 4-18
4.1.18 IPL — Instruction Pointer (Low Byte): DBH, BANK0.................................................................... 4-18
4.1.19 IPR — Interrupt Priority Register: FFH, BANK0 ........................................................................... 4-19
4.1.20 IRQ — Interrupt Request Register: DCH, BANK0........................................................................ 4-20
4.1.21 OPACON — OP AMP Control Register: E0H, BANK1 ................................................................ 4-21
4.1.22 P0CONH — Port 0 Control Register (High Byte): E4H, Bank0.................................................... 4-22
4.1.23 P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0.................................................... 4-23
4.1.24 P0INT — Port 0 Interrupt Control Register: E3H, BANK0............................................................ 4-24
4.1.25 P0PND — Port 0 Interrupt Pending Register: E6H, BANK0 ........................................................ 4-25
4.1.26 P1CON — Port 1 Control Register: E7H, BANK0 ........................................................................ 4-26
4.1.27 P2CONH — Port 2 Control Register (High Byte): E8H, BANK0 .................................................. 4-27
4.1.28 P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0.................................................... 4-28
4.1.29 PWMCON — PWM Control Register: EFH, BANK0 .................................................................... 4-29
4.1.30 PWMCCON — PWM CMP Control Register: F0H, BANK0......................................................... 4-30
4.1.31 PWMDL — Comparator0 Output Delay Register: F5H, Bank0.................................................... 4-31
4.1.32 PP — Register Page Pointer: DFH, BANK0................................................................................. 4-31
4.1.33 RESETID — Reset Source Indicating Register: F2H, BANK1..................................................... 4-32
4.1.34 RP0 — Register Pointer 0: D6H, BANK0 .................................................................................. 4-33
4.1.35 RP1 — Register Pointer 1: D7H, BANK0 .....................................................................................4-33
4.1.36 SPL — Stack Pointer: D9H, BANK0............................................................................................. 4-34
4.1.37 STOPCON — STOP Mode Control Register: F4H, BANK1 ........................................................ 4-34
4.1.38 SYM — System Mode Register: DEH, BANK0 ............................................................................ 4-35
4.1.39 TACON — Timer A Control Register: E1H, BANK1..................................................................... 4-36
4.1.40 TAPS — TA Pre-scalar Register: E2H, BANK1 ........................................................................... 4-37
4.1.41 TCCON — Timer C Control Register: E5H, BANK1 .................................................................... 4-38
4.1.42 TCPS — TC Pre-scalar Register: E6H, BANK1........................................................................... 4-39
4.1.43 TDCON — Timer D Control Register: E9H, BANK1 .................................................................... 4-40
4.1.44 TDPS — TD Pre-scalar Register: EAH, BANK1 .......................................................................... 4-41
5 INTERRUPT STRUCTURE..........................................................................5-1
5.1 Overview of Interrupt Structure................................................................................................................ 5-1
5.1.1 Levels ............................................................................................................................................... 5-1
5.1.2 Vectors.............................................................................................................................................. 5-1
5.1.3 Sources............................................................................................................................................. 5-1
5.1.4 Interrupt Types.................................................................................................................................. 5-2

5.1.5 S3F84B8 Interrupt Structure............................................................................................................. 5-3
5.1.5.1 Interrupt Vector Addresses ..................................................................................................... 5-4
5.1.5.2 Enable/Disable Interrupt Instructions (EI, DI)..........................................................................5-4
5.1.6 System-Level Interrupt Control Registers ........................................................................................ 5-5
5.1.7 Interrupt Processing Control Points.................................................................................................. 5-6
5.1.8 Peripheral Interrupt Control Registers.............................................................................................. 5-7
5.1.9 System Mode Register (SYM) .......................................................................................................... 5-8
5.1.10 Interrupt Mask Register (IMR) ........................................................................................................ 5-9
5.1.11 Interrupt Priority Register (IPR) .................................................................................................... 5-10
5.1.12 Interrupt Request Register (IRQ).................................................................................................. 5-12
5.1.13 Interrupt Pending Function Types ................................................................................................ 5-13
5.1.13.1 Overview of Interrupt Pending Function Types................................................................... 5-13
5.1.13.2 Pending Bits Cleared Automatically by the Hardware ........................................................ 5-13
5.1.13.3 Pending Bits Cleared by the Service Routine..................................................................... 5-13
5.1.14 Interrupt Source Polling Sequence............................................................................................... 5-14
5.1.15 Interrupt Service Routines ............................................................................................................ 5-14
5.1.16 Generating Interrupt Vector Addresses........................................................................................ 5-15
5.1.17 Nesting of Vectored Interrupts...................................................................................................... 5-15
5.1.18 Instruction Pointer (IP).................................................................................................................. 5-16
5.1.19 Fast Interrupt Processing ............................................................................................................. 5-16
5.1.20 Procedure for Initiating Fast Interrupts ......................................................................................... 5-17
5.1.21 Fast Interrupt Service Routine...................................................................................................... 5-17
5.1.22 Relationship to Interrupt Pending Bit Types ................................................................................. 5-17
5.1.23 Programming Guidelines .............................................................................................................. 5-17
6 INSTRUCTION SET.....................................................................................6-1
6.1 Overview of Instruction Set ...................................................................................................................... 6-1
6.1.1 Key Features of Instruction Set ........................................................................................................ 6-1
6.1.1.1 Data Types.............................................................................................................................. 6-1
6.1.1.2 Register Addressing................................................................................................................ 6-1
6.1.1.3 Addressing Modes .................................................................................................................. 6-1
6.2 Flags Register (FLAGS)........................................................................................................................... 6-5
6.2.1 Flag Descriptions.............................................................................................................................. 6-6
6.2.2 Instruction Set Notation .................................................................................................................... 6-7
6.2.3 Condition Codes ............................................................................................................................. 6-11
6.3 Instruction Descriptions.......................................................................................................................... 6-12
6.3.1 ADC — Add with Carry................................................................................................................... 6-13
6.3.2 ADD — Add .................................................................................................................................... 6-14
6.3.3 AND — Logical AND ...................................................................................................................... 6-15
6.3.4 BAND — Bit AND ........................................................................................................................... 6-16
6.3.5 BCP — Bit Compare....................................................................................................................... 6-17
6.3.6 BITC — Bit Complement ................................................................................................................ 6-18
6.3.7 BITR — Bit Reset ........................................................................................................................... 6-19
6.3.8 BITS — Bit Set................................................................................................................................ 6-20
6.3.9 BOR — Bit OR................................................................................................................................ 6-21
6.3.10 BTJRF — Bit Test, Jump Relativeon False.................................................................................6-22
6.3.11 BTJRT — Bit Test, Jump Relative on True ..................................................................................6-23
6.3.12 BXOR — Bit XOR......................................................................................................................... 6-24
6.3.13 CALL — Call Procedure ............................................................................................................... 6-25
6.3.14 CCF — Complement Carry Flag .................................................................................................. 6-26
6.3.15 CLR — Clear ................................................................................................................................ 6-27
6.3.16 COM — Complement ................................................................................................................... 6-28

6.3.17 CP — Compare ............................................................................................................................ 6-29
6.3.18 CPIJE — Compare, Increment, and Jump on Equal.................................................................... 6-30
6.3.19 CPIJNE — Compare, Increment, and Jump on Non-Equal ......................................................... 6-31
6.3.20 DA — Decimal Adjust ................................................................................................................... 6-32
6.3.21 DA — Decimal Adjust (Continued) ............................................................................................... 6-33
6.3.22 DEC — Decrement ....................................................................................................................... 6-34
6.3.23 DECW — Decrement Word.......................................................................................................... 6-35
6.3.24 DI — Disable Interrupts ................................................................................................................ 6-36
6.3.25 DIV — Divide (Unsigned) ............................................................................................................. 6-37
6.3.26 DJNZ — Decrement and Jump if Non-Zero ................................................................................. 6-38
6.3.27 EI — Enable Interrupts ................................................................................................................. 6-39
6.3.28 ENTER — Enter ........................................................................................................................... 6-40
6.3.29 IDLE — Idle Operation ................................................................................................................. 6-42
6.3.30 INC — Increment.......................................................................................................................... 6-43
6.3.31 INCW — Increment Word............................................................................................................. 6-44
6.3.32 IRET — Interrupt Return............................................................................................................... 6-45
6.3.33 JP — Jump ................................................................................................................................... 6-46
6.3.34 JR — Jump Relative..................................................................................................................... 6-47
6.3.35 LD — Load.................................................................................................................................... 6-48
6.3.36 LD — Load (Continued)................................................................................................................ 6-49
6.3.37 LDB — Load Bit............................................................................................................................ 6-50
6.3.38 LDC/LDE — Load Memory........................................................................................................... 6-51
6.3.39 LDC/LDE — Load Memory (Continued)....................................................................................... 6-52
6.3.40 LDCD/LDED — Load Memory and Decrement............................................................................ 6-53
6.3.41 LDCI/LDEI — Load Memory and Increment................................................................................. 6-54
6.3.42 LDCPD/LDEPD — Load Memory with Pre-Decrement................................................................ 6-55
6.3.43 LDCPI/LDEPI — Load Memory with Pre-Increment..................................................................... 6-56
6.3.44 LDW — Load Word ...................................................................................................................... 6-57
6.3.45 MULT — Multiply (Unsigned) ....................................................................................................... 6-58
6.3.46 NEXT — Next ............................................................................................................................... 6-59
6.3.47 NOP — No Operation................................................................................................................... 6-60
6.3.48 OR — Logical OR......................................................................................................................... 6-61
6.3.49 POP — Pop From Stack............................................................................................................... 6-62
6.3.50 POPUD — Pop User Stack (Decrementing) ................................................................................ 6-63
6.3.51 POPUI — Pop User Stack (Incrementing) ................................................................................... 6-64
6.3.52 PUSH — Push To Stack............................................................................................................... 6-65
6.3.53 PUSHUD — Push User Stack (Decrementing) ............................................................................ 6-66
6.3.54 PUSHUI — Push User Stack (Incrementing) ............................................................................... 6-67
6.3.55 RCF — Reset Carry Flag ............................................................................................................. 6-68
6.3.56 RET — Return .............................................................................................................................. 6-69
6.3.57 RL — Rotate Left.......................................................................................................................... 6-70
6.3.58 RLC — Rotate Left Through Carry............................................................................................... 6-71
6.3.59 RR — Rotate Right....................................................................................................................... 6-72
6.3.60 RRC — Rotate Right Through Carry............................................................................................ 6-73
6.3.61 SB0 — Select Bank 0 ................................................................................................................... 6-74
6.3.62 SB1 — Select Bank 1 ................................................................................................................... 6-74
6.3.63 SBC — Subtract with Carry .......................................................................................................... 6-75
6.3.64 SCF — Set Carry Flag.................................................................................................................. 6-76
6.3.65 SRA — Shift Right Arithmetic ....................................................................................................... 6-77
6.3.66 RP/SRP0/SRP1 — Set Register Pointer......................................................................................6-78
6.3.67 STOP — Stop Operation .............................................................................................................. 6-79
6.3.68 SUB — Subtract ........................................................................................................................... 6-80
6.3.69 SWAP — Swap Nibbles ............................................................................................................... 6-81

6.3.70 TCM — Test Complement Under Mask ....................................................................................... 6-82
6.3.71 TM — Test Under Mask ............................................................................................................... 6-83
6.3.72 WFI — Wait for Interrupt............................................................................................................... 6-84
6.3.73 XOR — Logical Exclusive OR ...................................................................................................... 6-85
7 CLOCK CIRCUIT.........................................................................................7-1
7.1 Overview of Clock Circuit......................................................................................................................... 7-1
7.1.1 Clock Status During Power-Down Modes ........................................................................................ 7-2
7.1.2 System Clock Control Register (CLKCON) ...................................................................................... 7-2
8 RESET AND POWER-DOWN .....................................................................8-1
8.1 Overview of System Reset....................................................................................................................... 8-1
8.1.1 MCU Initialization Sequence ............................................................................................................ 8-3
8.2 Power-down Modes ................................................................................................................................. 8-4
8.2.1 Stop Mode ........................................................................................................................................ 8-4
8.2.1.1 Using RESET to Release Stop Mode ..................................................................................... 8-4
8.2.1.2 Using an External Interrupt to Release Stop Mode ................................................................ 8-4
8.2.1.3 Idle Mode ................................................................................................................................ 8-5
8.2.2 Hardware Reset Values.................................................................................................................... 8-6
9 I/O PORTS...................................................................................................9-1
9.1 Overview of I/O Ports............................................................................................................................... 9-1
9.1.1 Port Data Registers .......................................................................................................................... 9-1
9.1.1.1 Port 0....................................................................................................................................... 9-2
9.1.1.2 Port 1....................................................................................................................................... 9-7
9.1.1.3 Port 2....................................................................................................................................... 9-9
10 BASIC TIMER............................................................................................10-1
10.1 Overview of Basic Timer ...................................................................................................................... 10-1
10.2 Basic Timer Control Register (BTCON)............................................................................................... 10-2
10.2.1 Basic Timer Function Description................................................................................................. 10-3
10.2.1.1 Watchdog Timer Function................................................................................................... 10-3
10.2.1.2 Oscillation Stabilization Interval Timer Function ................................................................. 10-3
11 8-BIT TIMER A...........................................................................................11-1
11.1 Overview of 8-bit Timer A .................................................................................................................... 11-1
11.1.1 Functional Description .................................................................................................................. 11-2
11.1.1.1 Timer A Interrupts ............................................................................................................... 11-2
11.1.1.2 Interval Timer Function ....................................................................................................... 11-2
11.1.1.3 Pulse Width Modulation Mode ............................................................................................11-2
11.1.1.4 Capture Mode ..................................................................................................................... 11-2
11.1.2 Timer A Control Register (TACON).............................................................................................. 11-3
11.1.3 Block Diagram of Timer A............................................................................................................. 11-6
12 TIMER 0.....................................................................................................12-1
12.1 One 16-bit Timer Mode (Timer 0) ........................................................................................................ 12-1
12.1.1 Overview of One 16-bit Timer Mode (Timer 0)............................................................................. 12-1
12.1.2 Functional Description of One 16-bit Timer Mode (Timer 0) ........................................................ 12-2
12.1.2.1 Interval Timer Function ....................................................................................................... 12-2

12.1.2.2 Timer 0 Control Register (TCCON)..................................................................................... 12-2
12.1.3 Block Diagram of Timer 0 ............................................................................................................. 12-4
12.2 Two 8-bit Timers Mode (Timer C and D) ............................................................................................. 12-5
12.2.1 Overview of Two 8-bit Timers Mode (Timer C and D).................................................................. 12-5
12.2.2 Timer C and D Control Register (TCCON, TDCON) .................................................................... 12-5
12.2.3 Functional Description of Two 8-bit Timers Mode (Timer C and D) ............................................. 12-9
12.2.3.1 Interval Timer Function (Timers C and D)........................................................................... 12-9
12.2.3.2 Pulse Width Modulation Mode (Timer D).......................................................................... 12-11
13 A/D CONVERTER......................................................................................13-1
13.1 Overview of A/D Converter .................................................................................................................. 13-1
13.1.1 Using A/D Pins for Standard Digital Input .................................................................................... 13-2
13.1.1.1 A/D Converter Control Register (ADCON).......................................................................... 13-2
13.1.2 Internal Reference Voltage Levels............................................................................................... 13-3
13.1.3 Conversion Timing........................................................................................................................ 13-5
13.1.4 Internal A/D Conversion Procedure.............................................................................................. 13-5
14 COMPARATOR.........................................................................................14-1
14.1 Overview of Comparator ...................................................................................................................... 14-1
14.1.1 Functional Description of Comparator.......................................................................................... 14-1
14.1.1.1 Comparator 0 ...................................................................................................................... 14-1
14.1.1.2 Comparator 1/2/3 ................................................................................................................ 14-4
15 OPERATIONAL AMPLIFIER.....................................................................15-1
15.1 Overview of Operational Amplifier ....................................................................................................... 15-1
15.1.1 Functional Description of Operational Amplifier ........................................................................... 15-1
15.1.2 OPAMP Control Register.............................................................................................................. 15-2
15.1.3 Block Diagram of OPAMP ............................................................................................................ 15-2
15.1.4 Reference Circuit.......................................................................................................................... 15-3
16 10-BIT IH-PWM..........................................................................................16-1
16.1 Overview of 10-bit IH-PWM ................................................................................................................. 16-1
16.2 Functional Description of 10-bit IH-PWM............................................................................................. 16-2
16.2.1 PWM ............................................................................................................................................. 16-2
16.2.2 PWM Clock Rate .......................................................................................................................... 16-2
16.2.3 PWM Functional Description ........................................................................................................ 16-3
16.2.4 PWM Control Register (PWMCON).............................................................................................. 16-4
16.2.5 PWM CMP linkage Control Register (PWMCCON) ..................................................................... 16-5
16.2.6 Block Diagram of PWM Module.................................................................................................... 16-6
17 PROGRAMMABLE BUZZER ....................................................................17-1
17.1 Overview of Programmable Buzzer ..................................................................................................... 17-1
17.2 Functional Description of Programmable Buzzer ................................................................................ 17-1
17.2.1 BUZ Control Registers (BUZCON)............................................................................................... 17-1
17.2.2 BUZ Frequency Table (@4MHz).................................................................................................. 17-2
18 FLASH MCU ROM.....................................................................................18-1
18.1 Overview of Flash MCU ROM.............................................................................................................. 18-1

19 EMBEDDED FLASH MEMORY INTERFACE...........................................19-1
19.1 Overview of Embedded Flash Memory Interface................................................................................. 19-1
19.1.1 Flash ROM Configuration ............................................................................................................. 19-1
19.1.2 Key Features of Embedded Flash Memory Interface................................................................... 19-1
19.1.3 User Program Mode ..................................................................................................................... 19-2
19.1.4 Smart Option................................................................................................................................. 19-2
19.1.5 Flash Memory Control Registers (User Program Mode).............................................................. 19-3
19.1.5.1 Flash Memory Control Register (FMCOn) .......................................................................... 19-3
19.1.5.2 Flash Memory User Programming Enable Register (FMUSR)........................................... 19-3
19.1.5.3 Flash Memory Sector Address Registers ........................................................................... 19-4
19.1.6 Sector Erase ................................................................................................................................. 19-5
19.1.7 Programming ................................................................................................................................ 19-8
19.1.8 Reading ...................................................................................................................................... 19-14
19.1.9 Hard Lock Protection .................................................................................................................. 19-15
20 LOW VOLTAGE RESET............................................................................20-1
20.1 Overview of Low Voltage Reset........................................................................................................... 20-1
21 ELECTRICAL DATA..................................................................................21-1
21.1 Overview of Electrical Data.................................................................................................................. 21-1
22 DEVELOPMENT TOOLS...........................................................................22-1
22.1 Overview of Development Tools.......................................................................................................... 22-1
22.1.1 Target Boards ............................................................................................................................... 22-1
22.1.2 Programming Socket Adapter ...................................................................................................... 22-1
22.2 Development System Configuration .................................................................................................... 22-2
22.3 TB84B8 Target Board .......................................................................................................................... 22-3
22.4 Third Parties for Development Tools ................................................................................................... 22-8
22.4.1 OTP/MTP Programmer (Writer).................................................................................................... 22-9
23 MECHANICAL DATA................................................................................23-1
23.1 Overview of Mechanical Data .............................................................................................................. 23-1

List of Figures
Figure Title Page
Number Number
Figure 1-1 S3F84B8 Block Diagram .................................................................................................................. 1-5
Figure 1-2 S3F84B8 Pin Assignment (20-DIP, 20-SOP) ................................................................................... 1-6
Figure 1-3 Pin Circuit Type 1 ............................................................................................................................. 1-9
Figure 1-4 Pin Circuit Type 2 ............................................................................................................................. 1-9
Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)........................................................................ 1-10
Figure 1-6 Pin Circuit Type 1-2 (P2.3) ............................................................................................................. 1-11
Figure 1-7 Pin Circuit Type 1-3 (P0.3, P0.4, P0.6) .......................................................................................... 1-12
Figure 1-8 Pin Circuit Type 2-1 (P0.5) ............................................................................................................. 1-12
Figure 1-9 Pin Circuit Type 3 (P0.2)................................................................................................................. 1-13
Figure 1-10 Pin Circuit Type 2-2 (P0.0, P0.1).................................................................................................. 1-13
Figure 2-1 Program Memory Address Space..................................................................................................... 2-2
Figure 2-2 Smart Option..................................................................................................................................... 2-3
Figure 2-3 Internal Register File Organization in S3F84B8 ............................................................................... 2-5
Figure 2-4 Register Page Pointer (PP) .............................................................................................................. 2-6
Figure 2-5 Set 1, Set 2, Prime Area Register Map ............................................................................................ 2-8
Figure 2-6 8 Byte Working Register Areas (Slices) ........................................................................................... 2-9
Figure 2-7 Contiguous 16 Byte Working Register Block.................................................................................. 2-10
Figure 2-8 Non-Contiguous 16 Byte Working Register Block .......................................................................... 2-11
Figure 2-9 16-Bit Register Pair......................................................................................................................... 2-12
Figure 2-10 Register File Addressing............................................................................................................... 2-13
Figure 2-11 Common Working Register Area.................................................................................................. 2-14
Figure 2-12 4-Bit Working Register Addressing............................................................................................... 2-15
Figure 2-13 4-Bit Working Register Addressing Example................................................................................ 2-16
Figure 2-14 8-Bit Working Register Addressing............................................................................................... 2-17
Figure 2-15 8-Bit Working Register Addressing Example................................................................................ 2-18
Figure 2-16 Stack Operations .......................................................................................................................... 2-19
Figure 3-1 Register Addressing ......................................................................................................................... 3-2
Figure 3-2 Working Register Addressing ........................................................................................................... 3-2
Figure 3-3 Indirect Register Addressing to Register File ................................................................................... 3-3
Figure 3-4 Indirect Register Addressing to Program Memory............................................................................ 3-4
Figure 3-5 Indirect Working Register Addressing to Register File..................................................................... 3-5
Figure 3-6 Indirect Working Register Addressing to Program or Data Memory ................................................ 3-6
Figure 3-7 Indexed Addressing to Register File................................................................................................. 3-7
Figure 3-8 Indexed Addressing to Program or Data Memory with Short Offset ................................................ 3-8
Figure 3-9 Indexed Addressing to Program or Data Memory ............................................................................ 3-9
Figure 3-10 Direct Addressing for Load Instructions........................................................................................ 3-10
Figure 3-11 Direct Addressing for Call and Jump Instructions......................................................................... 3-11
Figure 3-12 Indirect Addressing ....................................................................................................................... 3-12
Figure 3-13 Relative Addressing...................................................................................................................... 3-13
Figure 3-14 Immediate Addressing .................................................................................................................. 3-14
Figure 4-1 Register Description Format ............................................................................................................. 4-4

Figure 5-1 S3C8/S3F8 Series Interrupt Types................................................................................................... 5-2
Figure 5-2 S3F84B8 Interrupt Structure............................................................................................................. 5-3
Figure 5-3 ROM Vector Address Area ............................................................................................................... 5-4
Figure 5-4 Interrupt Function Diagram ............................................................................................................... 5-6
Figure 5-5 System Mode Register (SYM) .......................................................................................................... 5-8
Figure 5-6 Interrupt Mask Register (IMR) .......................................................................................................... 5-9
Figure 5-7 Interrupt Request Priority Groups................................................................................................... 5-10
Figure 5-8 Interrupt Priority Register (IPR) ...................................................................................................... 5-11
Figure 5-9 Interrupt Request Register (IRQ).................................................................................................... 5-12
Figure 6-1 System Flags Register (FLAGS) ...................................................................................................... 6-5
Figure 6-2 Example of the Usage of ENTER Statement.................................................................................. 6-40
Figure 6-3 Example of the usage of EXIT statement ....................................................................................... 6-41
Figure 6-4 Fast interrupt Service Routine ........................................................................................................ 6-45
Figure 6-5 Example of the Usage of the NEXT Instruction.............................................................................. 6-59
Figure 7-1 Main Oscillator Circuit (RC Oscillator with Internal Capacitor) ......................................................... 7-1
Figure 7-2 Main Oscillator Circuit (Crystal/CeramicOscillator).......................................................................... 7-1
Figure 7-3 System Clock Control Register (CLKCON) ...................................................................................... 7-2
Figure 7-4 System Clock Circuit Diagram .......................................................................................................... 7-3
Figure 8-1 Low Voltage Reset Circuit ................................................................................................................ 8-2
Figure 8-2 Reset Block Diagram ........................................................................................................................ 8-3
Figure 8-3 Timing for S3F84B8 after RESET..................................................................................................... 8-3
Figure 9-1 Port 0 Control Register High Byte (P0CONH) .................................................................................. 9-3
Figure 9-2 Port 0 Control Register Low Byte (P0CONL) ................................................................................... 9-4
Figure 9-3 Port 0 Interrupt Control Register (P0INT) ......................................................................................... 9-5
Figure 9-4 Port 0 Interrupt Pending Register (P0PND)...................................................................................... 9-6
Figure 9-5 Port 1 Control Register (P1CON) ..................................................................................................... 9-8
Figure 9-6 Port 2 High-Byte Control Register (P2CONH)................................................................................ 9-10
Figure 9-7 Port 2 Low-Byte Control Register (P2CONL) ................................................................................. 9-11
Figure 10-1 Basic Timer Control Register (BTCON)........................................................................................ 10-2
Figure 10-2 Oscillation Stabilization Time on RESET...................................................................................... 10-4
Figure 10-3 Oscillation Stabilization Time on STOP Mode Release ...............................................................10-5
Figure 11-1 Timer A Control Register (TACON) .............................................................................................. 11-4
Figure 11-2 Timer A Prescaler Register (TAPS).............................................................................................. 11-5
Figure 11-3 Timer A DATA Register (TADATA)............................................................................................... 11-5
Figure 11-4 Simplified Timer A Functional Block Diagram .............................................................................. 11-6
Figure 12-1 Timer 0 Control Register (TCCON) .............................................................................................. 12-3
Figure 12-2 Timer 0 Prescaler Register (TCPS).............................................................................................. 12-3
Figure 12-3 Timer 0 Functional Block Diagram ............................................................................................... 12-4
Figure 12-4 Timer C Control Register (TCCON).............................................................................................. 12-6
Figure 12-5 Timer C Prescaler Register (TCPS) ............................................................................................. 12-7
Figure 12-6 Timer D Prescaler Register (TDPS) ............................................................................................. 12-7
Figure 12-7 Timer D Control Register (TDCON).............................................................................................. 12-8
Figure 12-8 Timers C and D Function Block Diagram ................................................................................... 12-10
Figure 12-9 Timer D PWM Function Block Diagram...................................................................................... 12-11

Figure 13-1 A/D Converter Control Register (ADCON) ................................................................................... 13-2
Figure 13-2 A/D Converter Circuit Diagram ..................................................................................................... 13-3
Figure 13-3 A/D Converter Data Register (ADDATAH/L) ................................................................................ 13-3
Figure 13-4 A/D Converter Timing Diagram..................................................................................................... 13-4
Figure 13-5 Recommended A/D Converter Circuit for Highest Absolute Accuracy......................................... 13-5
Figure 14-1 CMP0 Control Register (CMP0CON) ........................................................................................... 14-2
Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)......................................................................... 14-2
Figure 14-3 Block Diagram of Comparator 0 ................................................................................................... 14-3
Figure 14-4 CMP1 Control Register (CMP1CON) ........................................................................................... 14-5
Figure 14-5 CMP2 Control Register (CMP2CON) ........................................................................................... 14-5
Figure 14-6 CMP3 Control Register (CMP3CON) ........................................................................................... 14-6
Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)......................................................................... 14-6
Figure 14-8 Block Diagram of Comparator 1/2/3 ............................................................................................. 14-7
Figure 15-1 OPAMP Control Register (OPACON)........................................................................................... 15-2
Figure 15-2 Block Diagram of OPAMP ............................................................................................................ 15-2
Figure 15-3 OPAMP Application Reference Circuit @ Gain=10...................................................................... 15-3
Figure 16-1 PWM Module Control Register (PWMCON)................................................................................. 16-4
Figure 16-2 PWM CMP Linkage Control Register (PWMCCON) .................................................................... 16-5
Figure 16-3 Anti-mis-trigger Data Register (AMTDATA).................................................................................. 16-5
Figure 16-4 Delay trigger Data Register (PWMDL) ......................................................................................... 16-5
Figure 16-5 Functional Block Diagram of PWM Module .................................................................................. 16-6
Figure 16-6 Example of the cooperation of PWM and Comparator 0_Delay Trigger ...................................... 16-7
Figure 16-7 Example of the cooperation of PWM and Comparator 0_Anti-mis-Trigger .................................. 16-7
Figure 16-8 Example of the Cooperation of PWM and Comparator 1/2/3_ Hard Lock ................................... 16-8
Figure 16-9 Example of the Cooperation of PWM and Comparator 1/2/3_Soft Lock...................................... 16-8
Figure 17-1 Buzzer Control Register (BUZCON)............................................................................................. 17-1
Figure 17-2 BUZ Functional Block Diagram..................................................................................................... 17-3
Figure 18-1 Pin Assignment Diagram (20-Pin SOP/DIP Package) ................................................................. 18-1
Figure 19-1 Smart Option................................................................................................................................. 19-2
Figure 19-2 Flash Memory Control Register (FMCON) ................................................................................... 19-3
Figure 19-3 Flash Memory User Programming Enable Register (FMUSR)..................................................... 19-3
Figure 19-4 Flash Memory Sector Address Register (FMSECH) .................................................................... 19-4
Figure 19-5 Flash Memory Sector Address Register (FMSECL).....................................................................19-4
Figure 19-6 Sector configurations in User Program Mode............................................................................... 19-5
Figure 19-7 Sector Erase Flowchart in User Program Mode........................................................................... 19-6
Figure 19-8 Byte Program Flowchart in a User Program Mode....................................................................... 19-9
Figure 19-9 Program Flowchart in a User Program Mode ............................................................................. 19-10
Figure 20-1 Low Voltage Reset Circuit ............................................................................................................ 20-2
Figure 21-1 Input Timing Measurement Points................................................................................................ 21-4
Figure 21-2 Operating Voltage Range @ External clock................................................................................. 21-7
Figure 21-3 Schmitt Trigger Input Characteristics Diagram............................................................................. 21-7
Figure 21-4 Stop Mode Release Timing When Initiated by a RESET ............................................................. 21-8
Figure 21-5 LVR Reset Timing....................................................................................................................... 21-11
Figure 21-6 Circuit Diagram to Improve the EFT Characteristics .................................................................. 21-12

Figure 22-1 Development System Configuration ............................................................................................. 22-2
Figure 22-2 TB84B8 Target Board Configuration ............................................................................................ 22-3
Figure 22-3 DIP Switch for Smart Option......................................................................................................... 22-6
Figure 22-4 40-Pin Connector for TB84B8....................................................................................................... 22-7
Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package.............................................................................. 22-7
Figure 23-1 20-DIP-300A Package Dimensions .............................................................................................. 23-1
Figure 23-2 20-SOP-375 Package Dimensions............................................................................................... 23-2

List of Tables
Table Title Page
Number Number
Table 1-1 Pin Descriptions (20-DIP/20-SOP) in S3F84B8................................................................................. 1-7
Table 1-2 Pin Descriptions used to Read/Write the Flash ROM........................................................................ 1-8
Table 2-1 S3F84B8 Register Type Summary .................................................................................................... 2-4
Table 4-1 System and Peripheral Control Registers Set1 Bank0...................................................................... 4-1
Table 4-2 System and Peripheral Control Registers Set1 Bank1...................................................................... 4-3
Table 5-1 Interrupt Control Register Overview................................................................................................... 5-5
Table 5-2 Interrupt Source Control and Data Registers..................................................................................... 5-7
Table 6-1 Instruction Group Summary ............................................................................................................... 6-2
Table 6-2 Flag Notation Conventions................................................................................................................. 6-7
Table 6-3 Instruction Set Symbols ..................................................................................................................... 6-7
Table 6-4 Instruction Notation Conventions....................................................................................................... 6-8
Table 6-5 Opcode Quick Reference................................................................................................................... 6-9
Table 6-6 Condition Codes .............................................................................................................................. 6-11
Table 8-1 S3F84B8 Set1 Registers Values after RESET .................................................................................. 8-6
Table 8-2 System and Peripheral Control Registers Set1 Bank1...................................................................... 8-8
Table 9-1 S3F84B8 Port Configuration Overview.............................................................................................. 9-1
Table 9-2 Port Data Register Summary ............................................................................................................. 9-1
Table 16-1 PWM Control and Data Registers.................................................................................................. 16-2
Table 17-1 Buzzer Frequency Table (@4MHz) ............................................................................................... 17-2
Table 18-1 Descriptions of Pins Used to Read/Write the Flash ROM ............................................................. 18-2
Table 21-1 Absolute Maximum Ratings ........................................................................................................... 21-2
Table 21-2 DC Electrical Characteristics ......................................................................................................... 21-3
Table 21-3 AC Electrical Characteristics.......................................................................................................... 21-4
Table 21-4 Oscillator Characteristics ............................................................................................................... 21-5
Table 21-5 Oscillation Stabilization Time......................................................................................................... 21-6
Table 21-6 Data Retention Supply Voltage in Stop Mode ............................................................................... 21-8
Table 21-7 A/D Converter Electrical Characteristics........................................................................................ 21-9
Table 21-8 OP AMP Electrical Characteristics............................................................................................... 21-10
Table 21-9 Comparator Electrical Characteristics ......................................................................................... 21-10
Table 21-10 LVR Circuit Characteristics ........................................................................................................ 21-11
Table 21-11 Flash Memory AC Electrical Characteristics.............................................................................. 21-11
Table 21-12 ESD Characteristics................................................................................................................... 21-12

Table 22-1 TB84B8 Components..................................................................................................................... 22-4
Table 22-2 Power Selection Settings for TB84B8............................................................................................ 22-4
Table 22-3 Using Single Header Pins to Select Clock Source and Enable/Disable PWM .............................. 22-5

List of Examples
Example Title Page
Number Number
Example 2-1 Setting the Register Pointers ...................................................................................................... 2-10
Example 2-2 Using the RPs to Calculate the Sum of a Series of Registers.................................................... 2-11
Example 2-3 Addressing the Common Working Register Area .......................................................................2-14
Example 2-4 Standard Stack Operations Using PUSH and POP.................................................................... 2-20
Example 10-1 Configuring the Basic Timer...................................................................................................... 10-6
Example 13-1 Configuring A/D Converter........................................................................................................ 13-6
Example 14-1 Comparator Configuration......................................................................................................... 14-7
Example 19-1 Sector Erase ............................................................................................................................. 19-7
Example 19-2 Programming .......................................................................................................................... 19-11
Example 19-3 Reading................................................................................................................................... 19-14
Example 19-4 Hard Lock Protection .............................................................................................................. 19-15

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER
1-1
1 OVERVIEW OF S3F84B8 MICROCONTROLLER
1.1 S3C8-SERIES MICROCONTROLLERS
Samsung’s SAM8RC family of 8-bit single-chip CMOS microcontrollers offer a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Owing to its address/data bus
architecture and a large number of bit-configurable I/O ports, these microcontrollers provide a flexible
programming environment for applications with varied memory and I/O requirements. To support real-time
operations, timer/counters with selectable operating modes are included.
1.1.1 S3F84B8 MICROCONTROLLER
The S3F84B8 single-chip CMOS microcontrollers are designed using a highly advanced CMOS process
technology based on Samsung’s latest CPU architecture.
S3F84B8 specifies a microcontroller with built-in 8K-byte full-flash ROM.
Using a proven modular design approach, Samsung S3F84B8 integrates the following peripheral modules with a
powerful SAM8 RC core:
3 configurable I/O ports (18 pins)
17 interrupt sources with 17 vectors and 6 interrupt levels
1 watchdog timer function (Basic Timer)
1 basic timer (8-bit) for oscillation stabilization
3 timer/counters (8-bit) with Time Interval, PWM, and Capture modes (Timer C and Timer D can be used for
16-bit Timer 0)
1 timer/counter (16-bit) with 2 operating modes: Interval timer mode and PWM mode (If Timer C and Timer D
are used for Timer 0, S3F84B8 has 1 Timer0 (16-bit))
Analog to digital converter with 8 input channels and 10-bit resolution
1 BUZ for programmable frequency output
High current LED drive I/O ports (High current output: Typical 12 mA)
The S3F84B8 microcontroller is ideal for use in a wide range of home applications requiring simple timer/counter,
ADC, and so on. They are currently available in 20-pin SOP/DIP package.

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER
1-2
1.1.2 KEY FEATURES OF S3F84B8
The key features of S3F84B8 include:
CPU
SAM8RC CPU core
Memory
8K-byte internal multi-time program memory Full-Flash
Sector size: 128 Bytes
10 Years data retention
Fast programming time:
oChip erase: 32ms
oSector erase: 12ms
oByte program: 20us
User programmable by ‘LDC’ instruction
Endurance: 10,000 erase/program cycles
Sector (128-bytes) erase available
Byte programmable
272-byte general-purpose register area
Instruction Set
78 instructions
Idle and Stop instructions added for power-down modes
Instruction Execution Time
400ns at 10MHz fOSC (minimum)
Interrupts
17 Interrupt sources with 17 vectors
Fast interrupt processing feature
General I/O
3 I/O ports
Bit programmable ports

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER
1-3
10-bit IH PWM
10-bit IH specific PWM 1-channel
Cooperate with CMPs
Anti-mis-trigger function
Delay trigger function
Comparators
4 integrated comparators
A/D Converter
8 analog input pins (MAX)
10-bit conversion resolution
OP Amplifier
1 integrated OP Amplifier
Timer/Counters
1 basic timer (8-bit) for watchdog function
1 timer (8-bit) TimerA
Interval mode
Capture mode
8-bit PWM mode
1 timer/counter (16-bit) Timer0
Configurable to 2 timer/counters (8-bit)
Interval mode
CMP0 event counter mode
6-/7-/8-bit PWM mode
BUZ
1 programmable Buzzer
Oscillation Frequency
1MHz to 10MHz external crystal oscillator
Typical 8MHz external RC oscillator
Internal RC: 8MHz (Typical), 0.5MHz (Typical)
Maximum 10MHz CPU clock