Samsung KS57C0302 User manual

USER'S MANUAL ERRATA
This document contains the corrections of errors,
typos and omissions in the following document.
Samsung 4-bit CMOS KS57C0302 Microcontroller User's Manual
Document Number: 20-57-0302
Publication: May 1995

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
ERRATA
Samsung 4-bit CMOS KS57C0302 Microcontroller User's Manual
Document Number: 20-57-0302, Revision 2
Publication: May 1995
1. MEMORY MAP (Page 4-7)
BMOD- BASIC TIMER MODE REGISTER F85H
.2 - .0 Input Clock Frequency and Signal Stabilization Interval Control Bits
000Input clock frequency:
Interrupt interval time: fx / 212 (1.02 kHz)
220 / fx (250 ms)
011Input clock frequency:
Interrupt interval time: fx / 29(8.18 kHz)
217 / fx (31.3 ms)
101Input clock frequency:
Interrupt interval time: fx / 27(32.7 kHz)
215 / fx (7.82 ms)
111Input clock frequency:
Interrupt interval time: fx / 25(131 kHz)
213 / fx (1.95 ms)
2. MEMORY MAP (Page 4-9)
CMOD-Comparator Mode Register FD7H, FD6H
.6 Conversion Time Control Bit
08×2 /fx, 244.4 us at 4.19 MHz
18×2 /fx, 30.5 us at 4.19 MHz
4
7

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
3. MEMORY MAP (Page 4-28)
TMOD0- Timer/Counter 0 Mode Register F91H, F90H
.6 - .4 Timer/Counter 0 Input Clock Selection Bits
000External clock input at TCL0 pin on rising edges
001External clock input at TCL0 pin on falling edges
100fx/210 = 4.09 KHz
101fx/26= 65.5 KHz
110fx/24 = 262 KHz
111fx = 4.19 KHz
NOTE:When fx is system clock of 4.19 MHz.
4. POWER-DOWN (Page 8-2)
Table 8-1. Hardware Operation During Power-Down Modes
Operation Stop Mode (STOP) (note) Idle Mode (IDLE)
Clock oscillator Main system clock oscillation stops CPU clock oscillation stops (main and
subsystem clock oscillation continues)
Basic timer Basic timer stops Basic timer operates (with IRQB set at
each reference interval)
Serial I/O interface Operates only if external SCK input is
selected as the serial I/O clock Operates if a clock other than the CPU clock is selected as the serial I/O clock
Timer/counter 0 Operates only if TCL0 is selected as the
counter clock Timer/counter 0 operates
Comparator Comparator operation is stopped Comparator operates
Watch timer Watch timer operation is stopped Watch timer operates
External interrupts INT1, INTK are acknowledged INT1, INTK are acknowledged
CPU All CPU operations are disabled All CPU operations are disabled
Power-down mode
release signal Interrupt request signals are enabled by
an interrupt enable flag or by RESET
input
Interrupt request signals are enabled by
an interrupt enable flag or by RESET
input
NOTE: STOP mode: when the main clock is selected as the system clock (CPU clock).

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
5. TIMERS AND TIMER/COUNTERS (Page 11-4)
Table 11-2. Basic Timer Mode Register (BMOD) Organization
BMOD.3 Basic Timer Restart Bit
1Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2 BMOD.1 BMOD.0 Basic Timer Input Clock Interrupt Interval Time (5)
000 fx/212 (1.02 kHz) 220/fx (250 ms)
011 fx/29 (8.18 kHz) 217/fx (31.3 ms)
101 fx/27 (32.7 kHz) 215/fx (7.82 ms)
111 fx/25 (131 kHz) 213/fx (1.95 ms)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.
2. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released.
3. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
4. Interrupt interval time is the wait time when STOP mode is released.

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
6. COMPARATOR (Page 12-2)
P1.0/CIN0/KS0
P1.1/CIN1/KS1
INTERNAL BUS
VREF
(EXTERNAL)
M
U
X
M
U
X
COMPARISON
RESULT
REGISTER
(CMPREG)
M
U
X
CMOD.7
CMOD.6
CMOD.5
0
CMOD.3
CMOD.2
CMOD.1
CMOD.0
4
8
REF
(INTERNAL)
+
-
VDD
1/2R
R
R
1/2R
NOTES:
1. INT occures only for digital input selecting: for analog input, any INT doesn’t.
2. The comparison results of CIN0, CIN1, CIN2, and CIN3 are respectively stored in
CMPREG.0, CMPREG.1, CMPREG.2, and CMPREG.3.
P1.2/CIN2/KS2
P1.3/CIN3/KS3
Figure 12-1. Comparator Circuit Diagram

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
7. COMPARATOR (Page 12-3)
1: CIN2; external reference, CIN0 and CIN1; analog input
0: Internal reference, CIN0-2; analog input
Reference voltage selection:
VDD x (n + 0.5)/16, n = 0 to 15
1: Conversion time (8 x 2 /fx, 30.5 us @4.19MHz)
0: Conversion time (8 x 2 /fx, 244.4 us @4.19MHz)
1: Comparator operation enable
0: Comparator operation disable
FD6H-FD7H
CMOD.7 CMOD.6 CMOD.5 "0" CMOD.3 CMOD.2 CMOD.1 CMOD.0
4
7
(VREF)
Figure 12-2. Comparator Mode Register (CMOD) Organization
8. COMPARATOR (Page 12-4)
ANALOG INPUT
VOLTAGE (CIN0−3)
COMPARISON
RESULT (CMPREG)
REFERENCE
VOLTAGE (VREF)
COMPARATOR CLOCK
(CMPCLK, fx/16, fx/128)
COMPARISON
START
0UNKNOWN
COMPARISON
END
COMPARISON TIME
(CMPCLK x 8)
1 1 UNKNOWN
Figure 12-3. Conversion Characteristics

KS57C0302 USER'S MANUAL ERRATA
JUNE 1998
9. COMPARATOR (Page 12-5)
The PROGRAMMING TIP - Programming the Comparator must be changed as follows:
+ PROGRAMMING TIP - Programming the Comparator
The following code converts the analog voltage input at the CIN0-CIN3 pins into 4-bit digital code.
BITR EMB
LD A,#0FH
LD P1MOD,A ;Analog input selection (CIN0-CIN3)
LD EA,#0CXH ;x = 0-F, comparator enable
;Internal reference, conversion time
;(30.5 us at 4.19 MHz)
LD CMOD,EA
WAIT0 LD L,#1H
WAIT1 LD W,A
LD A,#0H
WAIT2 INCS A
JR WAIT2
LD A,CMPREG ;Read the result
DECS L
JR WAIT1
CPSE A,W
JR WAIT0
LD P2,A ;Output the result from port 2