IC BLOCK DIAGRAM &DESCRIPTION
. .
U0301 LC78622E (Diaital Sianal Processor)
No. Name llo Function
1DEFI IInputof defect detection signal. (Connect to OV)
2TAU IFor PLL, Inputfor test, (Surely connect to OV)
3Pm oFor PLL. Output of phase comparator
3for external VCO.
4Vvss -For PLL. Ground for internal VCO.
5ISET Al For PLL. Connection of resistorfor current
adjustment of PDO output.
6VVDD -For PLL. Power supply for internal VCO.
7FR Al For PLL. For adjustment of VCO frequency range.
8Vss -Ground for digital root. (Surely connect to OV)
9EFMO oOutput of EFM signal for slice level control,
10 EFMIN IInput of EFM signal for slice level control,
11 TEST2 IInput for test. (Surely connect to OV)
12 CLV+ oOutput for disc motor control.
13 CLV- 0Output for disc motor control.
14 vIF oMonitor output for automatic selection of rough servo
/phase control.H:roughservo, “~: phase control
15 HFL IInputof track detectionsignal.
16 TES IInput of tracking error signal.
17 TOFF oOutput of tracking OFF signal.
18 TGL oOutput ofselecfion fortrackinggain. wb :gainup
19 .1P+ r--l C)Ih)tof track inImn control
a) JP- 0Output of track jump control.
21 PCK oOutput of clock monitor for playback EFM data,
When rocked tie phase: 4.321 8MHz
Z? FSEQ oOutput of detection for synchronizing signal.
When accordant to detected synchronizing signal
from EFM signal and synchronizing signal in internal
~
24 CONT1 l/O input/Outputforgenerel.
%CONT2 1/0 Control by serial date command from
I28 ICONT5 II/ol I
I29 IEMPH IO10utput of monitor for de-emphasis. I
Playback during diemphasis disc :“H” level
3) C2F oOutput of C2 flag.
31 DOUT oOutput of Digital OUT, (EIAJ foamed)
3? TEST3 IInput for test. (Surely conned to OV)
33 TEST4 IInput for test. (Surely connect to OV)
34 NC -Not connection. (Open)
U0401 LC6543F (Micro-Processor)
INo. IName IVQI Deacriotion I
1IDRF Il/O IRF signal detect
2VDD !-IGNDface for LC7822
I3ISQOUTI 1/0IInter
I4ICOIN 11/0 Ilnterface for LC7822
or LC78225CQCK 1/0 Interface fc
6WRQ 1/0 Interface for LC7822
7RWC 1/0 Interface for LC7822 I
8A-MUTE 1/0 Audio mute control
9FEED+ 1/0 Sled motor control
10 FEED- 1/0 Sled motor control
11 PIJIN 1/0 P~J-lN switch
H===l
35 MUTEL OL-channel 1-bit DAC. Out ut of mutin for L-channel.
L-channel 1-bit DAC. Power su Ifor L-channel.
37 LCHO OL-channel 1-bit DAC. Ou ut si nal for L-channel.
-L-channel 1-bit DAC. Ground terminal for L-channel.
(Surely connect to OV)
33 RVSS -R-channel 1-bit DAC. Ground terminal for R-channel.
(Surely connect to OV)
40 RCHO oR-channel 1-bit DAC. Outaut sianal for R-channel.
41 RVDD -R-channel 1-bit DAC. Power supply for R-channel.
42 MUTER oR-channel 1-bit DAC. Output of muting for R-channel.
43 XVDD -Power supply terminal for crystal oscillation.
44 XOUT oConnection terminal for crystal oscillation.
45 XIN I(16.9345MHz)
46 Xvss oGround terminal for crystal oscillation.
(Surely connect to OV)
47 SBSY oOutput of Synchronizing signal for sub-cede block.
48 EFLG oTerminal of correction monitor for Cl, C2, single
49] Pw ]O[Outputfor P, Q, R, S, T, Uand Wof sub-code.
50 ISFSY IO10utpuf of Synchronizingsignal for sub-code flame.
I I lwhen the stand-by the sub-code, leading edge.
51 ISBCK ] I IInput terminal of reading clock for sub-cde. I
I52 IFSX IO10utput terminal of synchronizing signal divided from I
crystal oscillation (7.35 kHz).
53 WRQ oOutput of stand-by signal for output the sub-code Q.
54 RWC IInputterminal of controlsignal for readkite.
5s SQOUT oOutput terminal for sub-code Q.
56 COIN IInput terminal for command from micro-processor.
57 mIInputof loading clock for command, or fetching clock
for sub-code from SQOUT.
% m IInput terminal of system reset. When ON the power
supply, ones the “L”.
wTST11 oOutput terminal for test.
Use the Open status(Normal the output is “L”).
III(When the un-control, connect to OV)
64 ITEST1 I I IInput for test. (Surely connect to OV)
No. Name Vo Description
16 Oscl IClock input
17 TEST IVss
18 Vss -GND
19 RESET IReset
mSEG-A 1/0 Lightup Signal for LED (Segment a)
21 SEG-B I/o Light up Signal for LED (Segment b)
22 SEG-C 1/0 Light up Signal for LED (Segment c)
23 SEG-D 1/0 Light up Signal for LED (Segment d)
24 SEG-E 1/0 Lightup Signal for LED (Segment e)
25 SEG-F 1/0 Lightup Signal for LED (Segment f)
-.
mswitch
Mute control
I3) IPROG Il/O lProgram LED I
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