Sega Genesis ii User manual

llfliij\"

SERVICE

MANUAL

GENESIS

II

/MEGA

DRIVE

II

(PAL-8/1/G, RGB)

NO.

001

ISSUED JUNE, 1993

CONTENTS

1. SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 3

2.

IDENTIFYING PARTS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 4

3.

DISASSEMBLY · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 6

4.

BLOCK DIAGRAM · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 7

5. SCHEMATIC

DIAGRAMS···································

8

6.

CIRCUIT BOARD

DIAGRAMS···

· · · · · · · · · · · · · · · · · · · · · · · · · · · 12

7.

PARTS

SPECIFICATIONS··································

16

8.

EXPLODED VIEW & PARTS LIST · · · · · · · · · · · · · · · · · · · · · · · · · · 28

8-1. EXPLODED

VIEW···································

28

8-2. MECHANICAL PARTS LIST · · · · · · · · · · · · · · · · · · · · · · · · · · 28

8-3. ELECTRICAL PARTS LIST · · · · · · · · · · · · · · · · · · · · · · · · · · ·

29

8-4. ACCESSORIES/PACKAGE

LIST·······················

37

Sega Enterprises, Ltd.

Before Using This SeNice Manual

This service manual includes data for the GENESIS

II

and MEGA DRIVE

II

.

• Pans of

the

circuits are different

in

the

GENESIS

II

depending

on

the model of

IC

II

(RGI3

encoder used).

Check

the

model of ICII

on

the

main

circuit

board

and

identify the type,

F,

S or

SM.

Type

Model

of

IC11

Part

No.

F

IC

MB3514PF-G-BND-EF 313-5232-A

s

IC

CXAI

145M-T6 SOP 313-5213-A

SM

IC

KA2195D 313-5236-A

IC1

D

CN3

D

IC6

MAIN C.B (Top View)

• Differences

in

the circuits are shown

in

the difference tables

in

the schematic

and

circuit board diagrams.

•

In

the parts

list,

differences are shown

in

the REMARKS columns.

2

1. SPECIFICATIONS

RATINGS

MEGA

DRIVE

II

Model

GENESIS

II

I

PAL-l

PAL-8

PAL-G.

RGB

Power input AC 120V, 60Hz AC220V, 50Hz, AC 240V, 50Hz i AC 220V, 50Hz

I

Power consumption

18

w

18W

18

w I

ISW

I

Usable temperature Humidity 5-35

oC

, 20-80%RH (non-condensing)

Dimensions

220

(W)

X 212 (D) X

59

(H) mm

SPECIFICATIONS

CPU

68000 (8M) & Z80A (4M)

RAM

72k

bytes

Memories

I

VRAM

64k bytes

Audio FM,

PSG,

PCM

VDP

SEGA custom LSI

Display Regular color

TV

Display capability Colors 512

Video

outputs

VIDEO

RGB

Control terminals

2,

control

pad,

etc.

can

be

attached

Reset

button

Game

restart function

Slots For cartridge

and

extension

* Design

and

specifications

are

subject

to

change

without notice.

3

2.

IDENTIFYING PARTS

4

2-1. FRONT & TOP VIEW OF CONSOLE

CONSOLE

Power

Button

Directional

Button

(D-Button)

CONTROL

PAD

2-2. BACK VIEW OF CONSOLE

Reverse

Side

A/V

OUT)ack

Extension

Compartment

Cartridge

Slot

Reset

Button

Power-On Indicator

Control

Port

2

Control

Port

1

Start

Button

C

Button

B

Button

A

AC Adaptor

Jack

AN

OUT ADAPTOR

2-3. ACCESSORIES

GENESIS

IT

RFUnit

SEGA AFUNIT

J.«X>B.

NO M<>1632

NT

.SC-M

f'IA)

CH3-CH4

~VN

Cii~Elec;T

'I

MEGA DRIVE

IT

RF

Unit

SEGA

RF

UNIT

(Except French model)

AC

Adaptor

Except

U.K.

)

Austraria

and

New Zealand

AC

Adaptor

Peritel Cable Sega 16-bit

Game

Canridge

(French

model

only) (Provided or

Sold

separately)

(U.K.) (Australia

and

New

Zealand)

5

3.

DISASSEMBLY

6

3-1. Dismantling procedure

Removal of bottom screws and top case

I) Turn

the

power button off.

2)

Turn the unit over. (See

Fig.

I)

3) Remove four screws (202).

4) Remove top case

(I

).

Main board removal (See Fig. 2)

I) Remove nine screws (20I).

2)

Remove the shield plate.

3)

Remove two screws (203).

4)

Remove the

main

board from the bottom case

(2).

3-2. Reinstalling procedure

Main board reinstallation

I) Attach the 64-pin cover (8).

2)

Attach the main board

to

the bottom case.

3) Tighten

two

screws (203).

4) Attach the shield plate.

.5)

Tighten nine screws (201).

Top case reinstallation

1)

Turn off the tactile power switch (TACT SW)

on

the main board.

2)

Attach the top case.

3)

Engage the top case with the bottom case.

Tightening the screws on the bottom

case.

I) Turn the unit over. (See Fig. I)

2)

Tighten four screws (202).

201

1\

J

?-202

Fig. 1

f-"201

Fig.

2

4.

BLOCK DIAGRAM

PERIPHERAL

DEVICE

(~g~=~~~:

~)

ANTENNA

GAME

CARTRIDGE

"'17'

r--

1

I

------------------------- --------------------

------------------------------------------------------------------~

I

L-

IC7.

ICB

~P041264

V-RAM

64KB

OSCl

n

53.

203424M

!MEGA

DRIVEn>

IC6

ICll

53.

o93!75

(GENESIS

II>

ZCLK:

3.

5MHz

-

VCLK:

7.

oMHZ

FC!004

M83514

VIDEO/

E[lCK

MCLK

AUDIO

CN3

C64P>

VCLK

CN2

C60P>

osc

EDCK

RGB/

SYNC

"

r--

-

ZCLK

42

~

IT

< r

;1;1

1

VCLK

~

ICl

<

~

~r

I

e:i~

131

68000CC

II I

II~

RGB

ENCODER

VDP

-"

I

ADDRESS/CONTROL

BUS

llo

bit>

-v

or---

-,/

CNl

I

~;,

·~

II

~;,

<

~

c;

~

" ::>

1--

<

r--

'

rv-

DATA

BUS

(!b bit> 1

PSG

RGB/SYNC

v

CPU

68000

<(;:,.

II

,(;..

! v JI

1--

......

~

""

.!..---

"'

~

~~

~

t--

<

:>

r&

IC6

' 7

~

7

~

MIX

ao

FC!004

0

IC6

~

7

:>

FC!004

"

MCLK

L

~

EDCK

ZCLK

7 v R

~

BUS

VCLK

I

RAM

l

ARBITER

V1:

A

I/0

EDCK:

MIX

64KB

~1/0.

ZTOV.

VTOZ

13.

3MHZ

~

IC2.

IC3

.),.

"'

0

•

PD42832-15

N

IC4

ZBOQFP

"'

I

;z

,("-

,;

ZCLK

d

,..,.1

....

~

IC6

<

N

b~b

IC12

,~~

<

FCI004

'7

N

FM

SOUND

SOURCE

TA7805HF

/I. "

.

ADDRESS/CONTROL

BUS

CB

bi

tl

+

DC

SV

2

REGULATOR

'

N

),

cPu

zao

l'r

~;,

v

/1

A.

0/A

CONVERTER

IC

DATA

BUS

C8

bit>

~

n -v

ICS

~>

~

./

~

•PD4304CX-15

~7

I

RAM

l

8KB

ONS

I

CN6

-------------------------------------------

----------------------------~------------------------------------------

!CONTROL

PADI

CONTROL

PAD

1

PLAYER

2

PLAYER

OPTION

1 2 3 4 5 6

~

RF

UNIT

i

VIDEO/AUDIO

AUDIO

I

;

RGB

DC

9V

OR

IOV

850mA

I

AC

ADAPTOR

-

7

E

~

TV

~

......

""

-

~

0

' c

AC~

8

A

8

7

8

5.

SCHEMATIC DIAGRAMS

5-1. SCHEMATIC DIAGRAM-1

E

0

c

8

A

IC7

AO

I/01

11

lDO

At

I/02

A2

I/03

A3

I/04

A4

8

SDO

AS

SI/01

AS

SI/02

A7

SI/03

SI/04

sc_

BAa.

~iiE

tiL.

SOE

ZJ:P

ICB

AO

I/0~

AD4

At

I/02

A2

I/03

A3

I/04

A4

~

AS

SI/01

AS

SI/02

A7

SI/03

sc

SI/04

sc_

BAa.

!all

QLIOE

RiB:

NOT

USED

sc

R.O.fH

CAS1

o..:1

vc~;a

F87

_T

tiL.

SOE

ZLP

lp;;p

NOT

USEI

1\

1t"

1

.~o

..

1\

1f;~P

I\

1t"'!~o"

1\

d7

HS601

VCLI<

'"

IC~

rvii:A

IPLO

27.

IPLO

IPL1

IPL2

BGAK

12

R74F~~O

30

_.G..

BG

..

~

BGACK

BR

OTACK

SERA

FCO

FC1

FC2

SG

VMA

E

HALT

RESET

AS

UDS

LD:t

R/W

seooocc

::f:::

C1

220P

NOT

USED

1

'H

!i

....-·A3

~~

-

A6

·;A7

H~

:,:~~

..~

..

12

VA13

-u

..

-1'15

II'

us

./.6.17

-'At8

~i~

-'A21

;A22

.6.23

•.

00

01

02

03

04

OS

06

07

08

09

L

oto

011

t.

012

013

014

.::_ot5

li

2

cs2

~pooP~

/1

~

IRtS

2.2K

.,.

'Lr!~;-~

I I

I

:.

I

_·..:::r

RAB

2.2KO'!~

c~~,~01

~

/I

l

I CAP

ARAV

33Ptt16

IC2

AO

At

A2

A3

A4

AS

A6

A7

AS

A10

AU

A12

A13

A14

,,..,n

:>o

~

liE.

WE

I

NOT

USED

rh

3

I

CAi

DO

D1

02

03

D4

DS

D6

D7

:::j'

C2

33P

rh

r--1-

ce

I

;.;..;

NOT

U!SEO

Jis

n~t~!

YNNL

SCCK

FS13

~

IC"'

1

AO

DO

At

01

A2

02

A3

03

A4

04

AS

05

AS

06

A7

07

AS

A10

AU

A12

A13

At4

RASO

20

~

liE.

WE

4

ovr•

•

a.

rn

,.,

.,,.

rn

"'

~

WAIT

21

HALT

WAIT

l.::::eEINi:T=1ttl2

INT

NMI

ZRES

23

RESET

ZBR

22

SUSRQ

8USAK

ZCLK

1

N.C.

!

I~

ti7

.L,z..,..eo;;;"""""P----1

5

FC1004

(SGE]

R12

2.2K

6

R10

2.2K

R11

v~ftft+ftnl

vn

rn

·~•

v•

r·

....,

~

""'

.----

.;~~

::

F=:

VC!;:1

r.7

::

*

F=:

~~

..

rh

;;

f;:

C6

33P

r.7

::f::

~~OF

r,l-]

4.7K

vc;~t

r:

I

'"

~

....

,.

......

'"

,,

..

7

l£6JJi.

CASO

voo

V01

V02

V03

V04

vos

VO&

V07

voe

VOS

V010

V011

VD12

V013

VDt4

laWS

BQtl_

dEL.

a.s2

FDC

FRES

.UL

SR3

6211

SR2

DisK

VAl

VA2

VA3

VA4

VAS

VA7

VAS

VA8

VA10

VA11

VA12

VA13

VA14

VA15

VA18

l£A.l7

WIS.

WIS-

C6D.

FDWR

VA!.S

627

SL3

S2S

SL2

~

VAS

VAU

VA7

VA12

VA&

VA13

VAS

VA14

VA4

VAtS

VA3 ·

VA16

VA2

VAt7

VAt

V07

VDO

VDB

VD6

VDt

VOS

VDS

VD2

VDtO

VD4

VD3

VD1t

SL.J._

MRES

SRt

VAS

VA

tO

VA18

VA19

VA20

VA21

VA22

~3

:a__

~

HSVNC

~

CAaP

~

AS

~

DIAlS.

CAS2

V015

VDt4

VOt3

:ilU.2.

~

WIS.

W!FI

tQ_

I.ll£.

CART

S

..

P

t;;ON

8

*DIFFERENCE TABLE FOR DIAGRAM-1

CIRCUIT GRID GENESIS

TI

MEGA DRIVE

TI

No.

OSCI C-5 53.693175MHz 53.203424MHz

C9 E-7 NOT USED 47P

CIO C-5 NOT USED lOP

Cll

B-4 NOT USED 33P E

5-2. SCHEMATIC DIAGRAM-2

I-

- - -

:[£.i_

-l

IC2 IC3

1--

~I'J_;3_-

-1

I - - -

_C~2-

- - - l

:~;

:~:

I ·lvccs vccs I +SlY vccs

ikk

I

TP

I

VCC1 VCC1

I I I I I

:~~

'pi

I C311 I I

I

o.oaau

1

'F'

TP

lo

I I I I :f

""

I

!F

o.o~

1..:..

__

__1

l

___

__l

Cl!:27 •

1%28

c

••

47u

0.0112U

IC5

OSC1

TP

:~:

----I

:~1

I

TP

I I I I I

'p''p'

I I

~---

----

~

I

o.oaau

1

o.ou..1

L

______

_j

I

I I I I L

_________

_!

l

___

__l

I I

I_---

c

- - - - -

..1

~6-

- - - - l

:•t-=

~I

r

46

C47

0

.022u

A73

SK

IC4

r - -vc-;s - - 1

I I

I

sou

0

.ORI!u

I

J I

,I I

l

_____

_j

IC7

I-

-v~s--

I

I I

,

_____

_j

r -

l.C_l3_-,

:

vr

I

~pel

I

Rllu

I

I I

l

_____

_j

I

'--------

------------,

B

I~

~

I I-""

f

411

~

F2

T10u

•••

-

;:

,_,_

J

A

---------------------------------

1 2 3 4 9

5-3. SCHEMATIC DIAGRAM-3

E

I

l_C_11_

I

vvcc

I

~L:

b::

100u

I

CN1

:

-;~cc:-

- - - ;

I

EH3

I

I I

I

r·;;u2e

I

,..

J

I I

L

_____

l

CN5

~-------------------,

:

vr

f

vcf

-

--

- - -

-:

:

~

I

~

I

I I

II

I * I

e~ll

:J 0 I

rh

GENESIS D : :

L - - - - - - - - -

_I:-

~-

.=

=

=.

---.:

=

~-

_::

,

CN6

..

I

I I

l

___

_j

~---------,

I VCC1

:~:

*

D

*DIFFERENCE TABLE FOR DIAGRAM-4

CIRCUIT GENESIS

ll

No. GRID MEGA DRIVE

ll

TYPE-F TYPE-S TYPE-SM

IC11

E-6

MB3514PF-G-BND-EF CXA1145-T6 SOP

KA2195D

MB3514PF-G-BND-EF

c

L2

E-7

100

.u

100

.u

NOT

USED

IOO.u

L3

D-7

12

.u

12

.u

NOT

USED

12

.u

L6

D-7

NOT

USED

NOT

USED

NOT

USED

100

.u

CE14

D-6

220

.u

IO.u IO.u

220

.u

C28

E-7

l8P (CH)

18P

(CH)

NOT

USED

l8P

(CH)

C29

D-7

0.01

.u

0.01

.u

NOT

USED

0.01

.u

C30

D-7

I80P (CH) I80P

(CH)

NOT

USED

I80P

(CH)

C32

E-6

ISP (CH)

180P

(CH)

NOT

USED

15P

(CH)

C57

D-5

-

lOOP

(CH)

NOT

USED

NOT

USED

lOOP

(CH)

B

C61

D-6

NOT

USED

NOT

USED

NOT

USED

0.1

.u

C62

D-7

NOT

USED

NOT

USED

NOT

USED

12P

(CH)

R47

E-6

12K

1.2K

NOT

USED

12K

R54

D-6

,_.

NOT

USED

24K 24K

NOT

USED

R55

D-6

!OK

lK

NOT

USED

!OK

R56

D-7

1.2K

NOT

USED

l.2K

R57

D-7

330 330

NOT

USED

IK

R61

E-5

4.7K

!OK

IOK

4.7K

A

2 3

10

5-4. SCHEMATIC DIAGRAM-4

CN7

DC

IN

l

TP

VCC1

All

11!0

r-----------------------------------------------------~~+9V

C33

NOT

USI!O

L!l

..---1

-=iJ

~~.

~

rh

2 3

A21

2.1!K

4

A:!IS

47K

5

L1

A711

7.!!K

6

A<Ill

2.2k

A!l7

330

*

GENESIS ll

.._.

__

_

ti.SK

A711

10K

A77

10K

R79

330

RIIO

330

------

I

I R!l7

I

330

-'--

*

I

MEGA

~=~I

DRIVE

ll

~~~I--

I

~=gPI

(etill

7

* I

I

-'

1

I

i::P

I

(CHI

I

* I

I

___

...1

CN1

E

0

c

8

A

8

11

6. CIRCUIT BOARD DIAGRAMS

6-1. MAIN CIRCUIT BOARD (Top View)

E

D

c

B

•A

2

12

-For

GENESIS

II

-

.

~'

. { j

,,.

· . r

·-

..

__

,

r·

.:~

-~h~:.lL

~·

..

~.~=,

-~~.

;

'.~···;··"··r

,.~:._;j

3 4 5

*DIFFERENCE TABLE

CIRCUIT GENESIS

II

No. TYPE-F TYPE-S TYPE-SM

6

L2 0

L3 0

L6 X

C9 X

CIO X

Cll

X

C28 0

C29 0

C30 0

C32 0

C57 0

C6l

X

C62 X

R47 0

R54 X

RSS

0

R56 0

R57 0

x :

N01

MOUNTED

0:

MOUNTED

0 X

X X

0 X

X X

0 X

0 0

0 X

7 8

6-2. MAIN CIRCUIT BOARD (Bottom View)

2

.,._,'),

('ft!-'".,.,'

R;t<

.,.

••

•

("./"

•

~·;,

~·

'··:·

.'J·-,.::r

(r-

..

'1

Fl-~v~

·-~-'/0#1·

·~.

""';

',".>•

~·

..

-

1'-,

.........

":!"'';,.~:

.....

:..

..

:-~_

,~-··

~"'

..

-~-~:.,.

_::-:__

-~·

~1~-?~J;"T?."...,.

~~-

~

'

p;:

.....

7..""'•1"•

'""·(1

....

r •

~

"''~""'"'l~~~rt~~

,-("

~·;ff'~~-!rr

0...-

.

""'"~.....-[).''

~"'"":"-"~-tf:lJ'•

0: •

.K~

ll"¥11?1!'-~.~.~'::-~:~

~

(-~~~Cit..

~t.

t-'~!-~~-:'7~j'.(

~--~)../

.•

-

_,.,.

/ ..·

"~''"""'

•

.n

ll[i

,.

.,~,_,,,..,.

.•

~I

a--

...

~~·:··~¥-1'!

.

-For

GENESIS

II

E

0

Ill

"'

c

8

A

3 4 5 6 7

6-3. MAIN CIRCUIT BOARD {Top VIew)

-For

MEGA DRIVE

II

-

E

0

c

B

A

2 3 4 5 6 7 8

14

6-4. MAIN CIRCUIT BOARD (Bottom View)

-For

MEGA DRIVE

II

2 3 4 5 6 7

··:.

;-~.~

-·

E

0

'C

B

~!PARTS

SPECIFICATION

~.L_IC~.

'~.•.·.r

IC

~.

C>6aHCOOOCP8

IC

MC68HCOOOFN8

: .

'·

&

Pa~

No.: 315-0685-A Parts No.: 315-0686-A

1

·c·

; • Outside View

Name

1/0

Function

No.

41

RES

1/0 Reset

42

VPA

I Valid Peripheral Address.

43

IPL2

I Interrupt Priority

Level

2.

9

168

61

44

IPI...o

I Interrupt Priority

Level

0.

60

45

FC,

0 Function

Code

Output

l.

46

N!C

-

N/C

47

A2

0 Address

Bus

2.

48

As

0 Address

Bus

5.

~

49

Aa

0 Address

Bus

8.

I

so

AIU

0 Address

Bus

10.

f 0 Address

Bus

II.

51

Au

44

.

52

A12

0 Address

Bus

12.

27

43 .

53

A,s

0 Address

Bus

15.

54

A,ti

0 Address

Bus

18.

~nnnnnnn~AAnnn~

.

..

...

..

.

....

55

Vee

I Power

Input.

56

Vss

I

GND.

:x.. • Description

57

An

0 Address

Bus

23.

Name

1/0

Function

No.

58

D,~

1/0 Data

bus

14.

59

Du

l/0

Data

bus

II.

Pir:

Name

1/0

Function

No.

I

N/C

-

N/C

21

A.. 0 Address

Bus

16.

60

D~

1/0 Data

bus

9.

2

DTACK

I

Data

Transfer Acknowledge. 22

A,1

0 Address

Bus

17.

61

D6

1/0 Data

bus

6.

-·

.

3

.BGACK

I

Bus

Grant Acknowledge.

23

'A,9 0 Address

Bus

19.

62

DJ

I/0

Data

bus

3.

-··

4

BR

I

Bus

Request.

24

Azo

0 Address

Bus

20.

63

Do

1/0 Data

bus

0.

5

CLK

I

Clock.

25

A21

0 Address

Bus

21.

64

UDS

0 Upper

Data

Strobe.

6

HALT

1/0

Halt.

26

An

0 Address

Bus

22.

65

R/W

0 Read/Write.

7

VMA

0

Valid

Memory Address.

27

D,s

'I/O

Data

bus

15.

66

IPL, I Interrupt Priority Level

1.

8 E 0 Enable.

28

D,z

1/0

Data

bus

12.

67

A,J

0 Address

Bus

13.

9

BERR

I

Bus

Error.

29

DIO

1/0

Data

bus

10.

68

DIJ

I/0

Data

Bus

13.

f--

10

N/C

-

N/C

30

Da

1/0

Data

bus

8.

f-

II

FC2

0 Function Code Output

2.

31

D, 1/0

Data

bus

7.

f-·

12

FC,

0 Function Code Output

0.

32

Ds

1/0 Data

bus

5.

13

A,

0 Address

Bus

I.

33

D~

1/0

Data

bus

4.

14

AJ

0 Address

Bus

3.

34

Dz

1/0 Data

bus

2.

15

A,

0 Address

Bus

4.

35

D,

1/0

Data

bus

l.

16

A6

0 Address

Bus

6.

36

AS

0 Address Strobe.

f-·

17

A,

0 Address

Bus

7.

37

LDS

0 Lower

Data

Strobe.

18

A.

0 Address

Bus

9.

38

BG

0

Bus

Grant.

19

N/C

-

N/C

39

Vee

I Power Input.

20

A,,

0 Address

Bus

14.

40

Vss

I

GND.

6

IC2/3 IC

HM65256BLFP-10

Pans

No.

: 315-0547-lOA

IC TC81832AFL-10

Pans

No.

: 315-0759-lOA

• Outside View

28

15

14

6ruwnnni!IIIIIIIIIIIIJ

• Operation Mode

CE

I

OE

I

WE

1/0

L I L H I LowZ

L X L HighZ

L H H HighZ

H L X HighZ

H H X HighZ

• Block Diagram

~

o---_._--t--1

RUD

IlliTE

lllNTRa.

({

o----_._-1

~~----~====r---~

IC

TC51832FL-10

Pans No. : 315-0677-A

IC LH5P832N-12

Pans

No.:

315-0760-12A

IC

TC51832AFL-85

Pans No. : 315-0759-85A

• Pin Layout

MODE

Read

Write

-

Refresh

Standby

A.,

A,

A

..

O"E

17

IC4 IC Z84C0006

Pans No. : 315-0738-R IC UPD9033GB-4-384

Pans No. : 315-5676-R IC TMPZ84COOAU-6

Pans

No.

: 315-0782-R

• Outside View

• Description

Pin I Name

No.

1 CLK

2-S

7-IO

DO-D7

6 Vee

II/17

NC

(PLCC Only)

I2

INT

I3

NMI

14 HALT

IS MREQ

18

1/0

I

I/0

-

I

eLK

04

03

05

06

vee

02

07

DO

01

Ne

;~~;~~:g::;~~~

33

32

31

30

29

28

27

26

25

24

23

NC

AS

A4

A3

A2

AI

AO

vss

~

'fli

RESET

Function

Single-phase clock input.When the clock input is set to DC ("1"

or

"0" level continued),

the MPU stops and holds that state.

8-bit bidirectional data bus.

+SV powersupply.

Not connected internally.

Set to open.

Maskable interrup request signal.

Interrupts are given by a peripheral LSI. When the interrupt enable flipflop (IFF)

is

set

to

"I"

by

software,·the interrupt is accepted.

INTis

usually used as the wired OR and a pull-up resistor is added externally.

Non-maskable interrupt request signal.

This interrupt request has priority overthe maskable interrupt and does not depend on the

state

of

the interrupt enable flipflop (IFF).

Halt signal.

"0" is output when the MPU executes a HALT command and is set to the HALT state.

Memory request signal.

"0" is output when there is an effective address for memory access on the address bus.

MRFQ also goes "0" together with the RFSH signal during memory refresh.

Pin I Name 1

110

1 Function

No. I

Input/output request

signal.

"0"

is

output

when

the

address for input/output

is

on

the

low-order 8

bits

(AO-A

7) of

the

16

IORQ

0 address

bus

when

an

input or output

is

given. The

IORQ

signal

is

also

output

together

with

I the

Ml

signal

when

an

interrupt

is

acknowledged

to

infonn

the

peripheral

LSI

that

the

I interrupt response vector

can

be

superimposed

on

the

data

bus.

i

READ

signal.

18

RD

0 "0"

is

output while

the

MPU

can

accept the

data

from

a peripheral

LSI.

The

data

in

the

designated

LSI

or

memory

is

gated

by

this signal

and

can

be

superimposed

on

the

MPU

data

bus.

I

WRITE

signal.

19

WR

0 This

is

output

when

the

data

to

be

stored

in

the

memory

or peripheral

LSI

is

superimposed

on

the

MPU

data

bus.

Bus acknowledge

signal.

When

the

BUSREQ

signal

is

input,

the

BUSACK

signal

infonns

the

peripheral LSis

that

20

BUSACK

0 the address

bus

and

data

bus

of

the

MPU

and

the

MREQ,

IORQ,

RD

and

WR

signals

have

been

set to

high

impedance.

WAIT signal.

21

WAIT

I The

WAIT

signal infonns

the

MPU

that

the designated

memory

or

peripheral

LSI

is

not

ready for

data

transfer. The

MPU

continues

in

the

wait

state

as

long

as

the

WAIT

signal

is

''0".

Bus request signal.

22

BUSREQ

The

BUSREQ

signal requests

to

set

the

address

bus

and

data

bus

of

the

MPU

and

the

I

MREQ,

IORQ,

RD

and

WR

signals

to

high

impedance.

BUSREQ

is

usually

used

as

the

wired

OR

and

a pull-up resistor

is

connected externally.

Reset signal.

23

RESET

I The

RESET

signal initializes

the

MPU

and

should

be

active ("0") for

at

least

3

clock-signal periods.

Signal that indicates machine cycle

I.

-"0"

is

output together

with

the

MREQ

in

the

command

operation code

fetch

cycle.

When

24

Ml

0 2-byte operation codes

are

executed, MI

is

output

each

time

the

operation code

is

fetched.

MI

is

output

with

the

IORQ

signal

in

the

maskable interrupt acknowledge

cycle.

Refresh signal.

25

RFSH

0 "0"

is

output

when

the

address

that

refreshes

the

dynamic

memory

is

on

the

low-order 7

bits of

the

address

bus.

The

MREQ

signal also goes active ("0")

in

this

state.

26

Vss

-

OV

power supply

27-32 16-bit address

bus.

34-38 AO-AIS 0 Address the

memory

and

input/output

ports.

40-44 The address for refreshing

is

output

during

refreshing.

19

ICS

IC

UPD4364G-15L

PartS

No.

: 315-0546-A IC MB8464A-80

PartS

No.: 315-0651-A

20

IC LC3564PM-10L

PartS

No.: 315-0753-IOA

IC

KM6264BLG-1

OL

PartS

No.

: 315-0755-A

IC

CXK5864CM-70LL-T6

PartS

No.

: 315-0773-A

• Outside View

28

15

~RRRRRRRBRRRRBBI

I o I

QQQQQQQQQQQQQQ

'"'

• Operation Mode

CE,

CE2

OE

H X X

WE

X

IC LC3564PM-12L

Parts

No.

: 315-0753-12A

IC LC3664BML-85H

Parts

No.

: 315-0766-85

• Pin Layout

v,.

WE

CE,

A.

A,

A.,

oe

CE.

MODE

OUTPUT

STATE

Non-Select

X L X X (Power

Down)

High

Impedance

L H H

L H L

L H X

• Block Diagram

1(0,

1/0,

-

-ADDRESS

-BUFFER

-

:JO-

~

1-

ROW

DECODER

1-

INPUT

DATA

CONTROL

1-

r-

1--

I

H Output Disable

H

Read

Dour

L Write

DIN

115.5311

err

(2511

X

2511)

MEMORY CELL

ARRAY

I I

SENSE SWITCH

r-

-

1--

OUTPUT

COLUMN CONTROL

DECODER

I I

ADDRESS

BUFFER

~l.l.l.l

IC MB8464A-10LL

PartS

No.

: 315-0635-A

IC KM6264BLG-10

Parts

No.

: 315-0754-A

IC LC3664BML-10H

PartS

No.

: 315-0766-10

A,-A.,

:ADDRESS

INPUT

oe

: OUTPUT ENABLE INPUT

1(0,-1/0,

:DATA

INIOUTPUT

Vee

: +5V POWER SUPPLY

CE., CE, : CHIP ENABLE 1, 2 INPUT

GND

:GROUND

\\iE

:WRITE ENABLE INPUT

NC : NO CONNECTION

POWER

SUPPLY

CURRENT

lse

leo.

Sega GENESIS II User manual

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