Sega Cd ii User manual

111ma·

SERVICE

MANUAL

SEGA CD

II

/MEGA CD

II

NO.

002

ISSUED AUGUST, 1993

CONTENTS

1.

SPECIFICATIONS·········································

2

2.

IDENTIFYING PARTS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 3

3.

DISASSEMBLY···········································

4

4.

CD

DRIVE ADJUSTMENT · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 6

5.

CD

INTERFACE···········································

8

6.

CD

DRIVE UNIT REPLACEMENT PROCEDURE· · · · · · · · · · · · · · 9

7.

TOC READ-IN FLOWCHART· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 10

8.

GUIDES FOR SERVICING· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·

11

9.

BLOCK DIAGRAM · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·

~

·

· · · · · · ·

15

10.

SCHEMATIC

DIAGRAMS·································

16

11.

CIRCUIT BOARD

DIAGRAMS·····························

18

12. PARTS SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 18

13.

EXPLODED VIEW & PARTS

LIST·························

38

13-1. Exploded

View······································

38

13-2. Mechanical Parts List · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 39

13-3. Electrical Parts List · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·

39

13-4. Accessories/Package List · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 42

Sega Enterprises, Ltd.

1. SPECIFICATIONS

Ratings

Model SEGA CD

II

Power

input

AC

120V,

60Hz

Power consumption

18W

I

Temperature : 0

to

40

°C

MEGA

CD

II

AC230

or

240V

,

SOHz

18W

Operating environment

Humidity

:

10%

to

80%RH

(no

condensation)

Dimensions

396

(W)

x

220

(D)

x

84

(H)

mm

Specifications

CPU 68000 (

12.SMHz)

6M

bit

(Program, Picture

data,

Sound

data

memory)

RAM 512k

bit

(PCM

waveform memory)

128k

bit

(CD-ROM

data

cache memory)

Memory

64k

bit

(Back-up memory)

1M

bit

CD

game

BIOS

Boot ROM

CD

player software

CD+G

compatible

PCM sound source Stereo 8channels.

Sampling

frequency 32kHz

max.

Sound circuitry

16

bit

DIA converter.

DIA

converter

8x

internal over-sampling digital filter.

PCM

and

CD

sound

mixing

.

Mixing

with

mixing

terminal possible.

Frequency characteristics

20Hz

to

20kHz

Audio characteristics Signal v. noise ratio (S/N) Over

80dB

(1kHz) (Line

out)

Dynamic range Over90dB

Battery back-up secondary duration

Approx.

1

month

CD diameter

12cm

and

Bern

CD

drive unit Rotational direction Counter-clockwise

(relative

to

the

side opposite

from

the

label)

Access time Average l.Ss

Audio output Line out

RCA

jack x 2 (L/R)

Audio input Mixing Stereo jack

mixing.

* Design

and

specifications are subject to change without

notice.

2

••

\

2. IDENTIFYING PARTS

2-1. Front & Top View of Console 2-2. Back View of Console

=0 c=:::i

D 0

r====>

Indicator LE

2-3. Accessories

SEGA-CD D

AC Adaptor

Stereo Mixing Cable

(Except Canada)

Steel Joining Plate

(Retainer Bracket)

D Door

Door Knob

MEGA-CD D

AC Adaptor

AC AdaptorJack

---Audio

Line Out Jacks tor

Stereo Sound Connection

to Other Components

=

Mixing Jack for Stereo Sound Connection

to the Original Mega Drive & Genesis

( ExceptU.K. , Kuwait ) (U.K. and Kuwait) (Australia and New Zealand)

Australia and New Zealand

Audio RCA Cable

(Except USA& Canada)

Screwfor Steel

Joining Plate

Extension Panel

(Assy Spacer)

(Conn Plate

B)

Extension Plate

(Hold Plate Spacer)

(Conn Plate A)

Note: Names

of

pans in brackets ( ) arc

used

inthe pans list.

3

3.

DISASSEMBLY

4

3-1.Chuck Disk Assembly Removal

(I ) Press the door knob to open the door.

(2) Release three (3) stoppers holding the chuck disk

assembly.

(3) When reinstalling, align the recesses

in

the chuck

holder with the stoppers.

3-2. Top Case Assembly Removal

(I)

Turn over the unit and remove six (6) screws from

the bottom.

(2) Do not remove the bottom case

in

this state.

Be sure

to

turn over the unit again and then

remove the top case

in

the original state.

/Bo:om

Case

B

~i

3-3. Door Removal

(I)

Remove the top case assembly. (See item 3-2)

(2) Press the door knob to open the door.

(3) Remove the blind sheet on the right.

(4) Remove the door spring.

(5) Tum over the top case and remove two (2) screws.

then remove the oil damper.

(6) Push the door installation section

in

the directions

of

the arrows to release the bosses.

Blind Sheet

Door Knob

Door

Spring

j .

. '

3-4. Dismantling the Chuck Disk

Assembly

(

l)

Remove

the

chuck

disk

as

_

sembly

.

(See

item

3-1)

(2) Remove

the

screw

and

release

two

(2) stoppers.

The connector·

plate,

magnet,

chuck holder

and

chuck

disk

come

apan

on

their

own.

~Screw

t:f

~Connector

Plate

@-Magnet

Ring

~/---1

r----

Chuck Holder

Chuck Disk

3-5. CD Drive Unit Removal

(

l)

Remove

the

top case assembly. (See

item

3-2)

(2) Disconnect three (3) connectors

and

lift the

CD

drive

unit.

CD Drive Unit

Connectors

3-6. Circuit Board Assembly

Removal

(l)

Remove

the

top

case assembly.

(See

item

3-2)

(2)

Remove

five

(5) screws

holding

the

shield

plate

.

(3) Disconnect three (3) connectors

from

the

CD

drive

unit.

(4)

Remove

two

(2) screws

holding

the

circuit

board

assembly.

3-7. Door Lever and Door Knob

Removal

(1)

Remove

the

top

case assembly.

(See

item

3-2)

(2)

Turn

over

the

top

case

assembly

and

release

two

(2) stoppers,

then

remove

the

door lever

in

the

direction of

the

arrow.

(3) Release

two

(2) stoppers

and

remove

the

door

knob

.

Door

Knob

5

4.

CD DRIVE ADJUSTMENT

6

4-1. Test Equipment and Test Disc

J) Frequency counter

2) Oscilloscope (20MHz

or

more)

3) Adjustment jig (MEGA-CD II (F) CD ADJ. JIG)

4) Audio generator

5) Voltmeter (two units with one needle

or

one unit with two needles)

6) Test CD (SONY TYPE-4)

4-2. Set-up for Adjustment

J) Connect both terminals

of

J40I.

2) Tum SW401 on and fix

it

using plastic tape, etc.

3) Connect the jig to CN403.

('4)

Supply power to the unit and jig. (Use AC adaptor

of

MEGA

CD

II /SEGA CD II forjig)

\

~)

Press the [RESET] switch

of

the jig so the counter reads

"O"

. .

6) Connect the Q301

's

emitter and CNIOl pin 28 B

or

connect Mega Drive II /Genesis II .

(

Sn,

.

,,vfJ

IJ

f

f51:_lw.;~

rv

) 1..r/

f'

'-t-

Test mode Adjustment item

0 vco

2

EF

balance

3 Tracking gain

Note 1: The test mode

is

incremented each time the [TEST] switch

of

the jig is pressed.

Note 2: Test mode I

is

for checking the laser power and keeps the pickup laser illuminated.

4-3. Adjustment Parts Location

TP·PLCK 0

ED

TP-80

0

TP·A

0 B SW401

0301

0 0

~

1

;2

C410 0

TP-D

TP-VR 0

VR401

[!]

(EF balance)

0

TP-X

r;i

IC404 0 VR402

~mD

J401 0

GND

CN403

BTP-Y~

(Tracking gain)

VR403

[!]

(VCO)

TP°.vR

Adjustment

jig

TEST

MODE

0

TEST

RESET

ICI

ICJI

C .

4-4 Adjustment

. '2'S'v/·.:i111 I •

..,.i

\.:!.

\

Adjustment

I

Adjust-

I Test Test Adjustment procedure Purpose IFaults due

to

incom-

name

Jment

point

· equipment plete adjustment

VR403 TP-PLCK Frequency Shon both terminals of

C410

To

reproduce •

It

takes

more

time

to

(Connect counter

or

connectTP-D

and

GND.

a reference search for

the Adjust variable resistor clock signal Small each track.

1. vco probe's VR403 so the frequency of during

CD

the signal attest

PLCK is I

adjustment ground

to

play.

•No

play

pos-

GND)

4.320 ±

O.OSMHz.

Large sible.

VR401

TP-X Oscilloscope, Press(TEST) switch twice

to

To adjust the • Playability

of

(CQllnect

Adjustment jig. set

to

"Test Mode 2". center of

the

diny discs

the Probe:

10

:1 tracking error

and

scratched

probe's 50mv/div v

..

.O

(\

rcy)

signal discs

be-

Small

ground to Ims/div

vv=i

_(B)

comes

poor.

TP-VR) Test

CD

2.EF

Adjust VR40I so that peaks

balance (A) and (B)

of

the

output

adjustment waveform shown above are

•It

becomes

equal. impossible

to

search for

each

track.

Large

VR402 TP-X 2 voltmeters,

VTVMI

VTVM2

To adjust the •Becomes

TP-Y Generator,

EZI

ai

tracking susceptible to

Adjustment jig servo gain. shocks.

-

Test

CD

'O

•It

becomes

)

VTP-VR

Small impossible to

lo3

I search for

vTP-X

each track

on

-diny

and

SG

TP-Y scratched

3.

Tracking

discs.

gain Connect as shown above.

adjustment Press (TEST) switch three • Playability

of

times to setto "Test Mode 3" diny discs

and supply a l

.OkHz,

and

scratched

O.lSVnns signal from the discs be-

generator. Large comes

poor.

Adjust VR402 so the 2

voltmeters

read

the same

value.

7

5.

CD INTERFACE

8

5-1. CD Drive Block Diagram

500mv/div

5µs/div

(6)

500mv/div 50ms/div

11

~

.....

~),.

.,,,

p

"'

:

~

• <

,...

500mv/div 500ms/div

2 4

~N~~

'

1111111

200mv/div 50ms/div 50mv/div 50ms/div

2µs/div

2v/d1v. 1µ

s/d1v

(8) 9

i:=t.

~

i

.f

.

%1r---

..........

',,,.,

50mv/div 2s/div

ioomv/div

1

OOms/div

1

OOmv/div

50ms/div 200mv/div 500mv/div

i3)

200mv/div 2s/div 500mv/div 50ms/div

,---

----------------------,

I

''

,'

'

c,

"

J~Q2

IV

o'\

I'

CXAIOBI

"" IC403 IC40!

CXAI

082

CXOl

167

I

L'.==

_________________________

_J

I .

'

5-2. Description of CD Interface

Signals

Name 1/0 : Function !

1c

No_

/Pin

. I

No.

0 IError flag. Outputs

"H"

when I

C2PO !data correction is disabled. IC40l @

BCLK 0 IBit clock. IIC40l @

SDATA 0 ISerial data output. IIC401 @

LRCK 0 UR-channel identification clock. IC401 @

16MHz 0 i!6.9344MHz output. IC401 @

WFCK 0 IFrame clock. IC401

@)

EXCK I Sub-code read clock. IC401 @

SBSO 0 ISub-code data. IC401 @

SCOR 0 ISub-code sync. IC401 @

L-

MUTE

0 IOutputs

"L"

when playing back IC404 @

(DM) music and

"H"

in other modes.

!RO

0 Interrupt request. IC404 @

COCK 0

CD

mechanism control commu- IC404 @

nications clock.

HOCK I Host communications clock. IC404 @

DBO

1/0 Data bus 0. IC404 @

DB l 1/0 Data bus I. IC404 @

DB2

1/0 Data bus 2. IC404 @

DB3

1/0 Data bus

3.

IC404 @

RESET I Resets the

CD

hardware. IC404 @

5-3. CD Interface Connection

Reference Diagram

C2PO

LRCK

DATA 6CLK Serial data

PROCESS communications

DATA

IC401 16MHz

CXD1167 WFCK

EXCK Sub-code

S6SO

communications

SCOR

~1r

L-MUTE

(OM)

Audio control signal

MECHANISM IRQ

CONTROL UP

06US

(4bit)

063

IC404

062

UPD75006

061

Hostcommunications

060

CDKC

HOCK

RESET

6.

CD

DRIVE

UNIT

REPLACEMENT

PROCEDURE

Remove the GENESIS II/MEGA DRIVE

II

from

the SEGA CD II/MEGA CD

II

and unpl

ug

t

he

power cord

of

the SEGA CD II/MEGA

CD

II

from

the AC outlet.

Replace the CD drive

un

i

t.

Connect the power adapter and

GE

NESIS

II/MEGA DRIVE II.

Tum

on the door close detection switch (SW401)

forcibly to turn the power switch on. Check that

the laser emits a beam for about 2 seconds and the

pickup's object lens moves up and down.

Caution: Be careful; it is dangerous to look

straight at a laser beam.

Do not bring your eyes too close

to

it.

Adjust the

EF

balance. (VR40I)

Adjust the tracking gain. (VR402)

Check that an

RF

wavefonn

of

approx. l.5Vp-p

can be observed

at

IC402-2 (TP-RF).

Replacement complete.

9

f

f:..f)L-1:

7.

TOC

(Total of Contents) READ-IN FLOWCHART

Focus operation timing

Focus drive signal at JC403

pin@

v~r

~i~,//

[5]

'

F~~iz~~~rI_Pc.:X~l

:

Vref

IC401

pin @ , ·'

[5]

Sense~~

=i_

[G]

Focused point

IC404 pin

@or

IC403 pin @

10

Focus~~

--------

-1

L______

_

______

[6]

Broken lines show that focus

is

not obtained.

[1] Power

ON

[2] Pickup moves

to

inner edge.

NO

[4]

LaserON

[5] Focus search

[6] Focus servo

ON

-

[7]

Make a disc rotate.

[8] Tracking servo ON

[9] Disc servo

ON

[1

OJ

Reads

in

the TDC (disc data).

END

IC403pin@

Vrcf

SWS~I

ON [3]

~

IC403

pin@

sv-1v

--SW501

ON

~~

-

___

-

__

-_

-L

[3]

IC402pin@

sv-1v

~~

________

___!

Laser ON [4]

IC403 pin

Cl)

/\

/1

[5]

Vrcf--/

V

'---

--~~':~~P_!:~~-~~~~~-~P-~-~-~~~~2-

IC403

pin@

Vrcf

--uf~.,//L_

__

[6]

IC403

pin@

vrcr

Ji~8vl

__________

__

[7]

IC403

pin@

S..VoO'\.~

[BJ

IC403pin@

~50ms/~~!

.

500ms/div.

IC401

pin@

[10)

SV

..-Starts reading data.

ovER~-'---

8.

GUIDES FOR SERVICING

Is

the

EF

balance adjustment OK?

YES

Proceed to the tracking circuit

flowchart.

'--~~~~--.~~~~~-'NO

Proceed to the feed circuit

flowchart.

Proceed to the disc circuit flowchart.

Check the pickup.

(Din

on lens,

laser powermeasurement: 90 -

120

/.1

W)

Check the audio circuit.

Proceed to the control circuit flow-

chart.

PowerON

YES

Does the LED flash normally?

YES

Is the SEGA CD Il/MEGA CD Il NO

introduction picture normal?

YES

Does the control picture appear

when the start button is pressed?

YES

Does the cursormove?

YES

Does

the counterread "00:00"

when the CD dooris closed?

YES

Is the

TOC

read? (Sec the flowchart NO

on page

IO

until the TOC is read)

YES

Can

the first track

of

test CD be

played?

YES

ls

the TP-RF at IC402-

®normal?

-

NO

YES

Can each track

be

searched cor-

rectly?

YES

ls

the sound output?

YES

Check general operation.

YES

Is each operation in the control

picture nonnal?

YES

OK

YES

Check the control circuits.

NO

.-----@

NO Refer to pagel2.

Does

the disc rotate?

YES

ls

the tracking loop engaged?

IC403-@

1..--

Servo ON

vm

-1liill\lllllo

(ls the wavcfonn

of

IV

/div.,

05s/div. observed?)

NO

Proceed to the tracking circuit

flowchart.

Is an RF wavcfonn

of

approx.

l .SVp-p observed at IC402- ®

TP

RF.

-NO

Check RF circuit IC402 and pickup

(din on lens, etc.).

Proceed to the disc circuit

flowchart.

YES

11

@ Proceed to the feed circuit flowchart.

i •

I

NO

Does the pickup lens move

up

and down NO Is IC404-@

QY'.'

after SW401 is set to ON from OFF?

YES

lYES

Proceed to the focus circuit flowchart.

ls the laser lit for about 2 seconds after NO

SW401

is

set to ON from OFF? (Check the

laser power meter becomes

90-120

J1

W)

n_

Does

IC404-®

become

OY

from

SY

for N

0

about 2 seconds after SW401

is

set to ON

,__

YES

from OFF?

' !YES

Is

focus engaged for about 2 seconds after

NO

SW40!

is

set to

ON

from OFF? (Check the -Check Q401

's

peripheral circuits, the 8-pin I

lens movement visually.) cable and pickup.

YES

'

Proceed to the disc circuit flowchart. Does IC404-@ become

OY

from

SY

for N

0

about 2 seconds after SW401

is

set to

ON

r-

from OFF?

Proceed to the focus circuit flowchart.

f-

l

YES

Check the connections

of

IC402-®

. IC404 faulty

8-1. Focus Circuit Flowchart

Are

IC409-Q)/@/@9Y'.'

YES

Remove the top cover.

Set SW401 to ON to tum the power

on and check that the pickup lens

moves

up

and down.

YES

Does the waveform shown below

appear at

TP-Xl

when SW401

is

set to ON from OFF?

Yref

.............

Approx.

4Yp-p

· '

Approx.

O.Sms

Solid line: When focus is engaged.

Dotted line: When focus

is

not

engaged

YES

Check focus circuit IC403.

12

NO

1---~

Check the power circuit.

NO Docs the waveform shown below

appear berween IC409-(J)

and@

i---~

(FD).

Approx. 7V

-

/\-71·1·

OY

1L----~----~--

-

FD : Focus Drive

YES

Check the connection with the

pickup.

NO Check the pickup (dirt on lens, laser

is

output) and tracking circuit IC402.

t

NO Does the waveform shown below

appear berween IC403-(J) and ®

.------.

(FEO).

Pin@

Yref

Approx. 3Y

-

A·.7l1-·

-V

....

~--

·

=-

..

FEO

:Focus Error Out

YES

Check the path berween IC403-@

and IC409- ®.

IC403 faulty.

NO

8-2. Tracking Circuit Flowchart

Are

IC409-CDl@/@9V?

1---~

Check the power circuit.

YES

....------.1..-------. YES

....-------------..

YES

Is the TOC read? (Page

IO)

1---~

Can all tracks be searched precisely?

1..-------....-------' NO

NO

Docs the waveform shown below NO Check the pickup

(din

on lens. laser

appear at TP-X?

1---M

power 90-120

µ.

W)

and tracking

: Servo

OFF

Servo ON

.__ci_rc_u_it_

.

-----------'

Vrcf

Approx. 2V

YES

Does the waveform shown below

NO

....---------------.

appear at IC403-

@?

1---~

Check tracking circuit (IC403).

Servo

OFF

IServo ON

......

v~r

---i""' YES Tracking is OK. Proceed to the feed

circuit flowchan.

8-3. Disc Circuit Flowchart

NO

Are IC409-CD/

@/@9V?

1---M

Check the power circuit.

YES NO

Is

the disc stopped in the stop mode?

1---M

Is [email protected] ?

YES

Does the disc tum 1-2 seconds after

SW401

is

set to ON from OFF?

YES

Check IC409.

NO

OK

Proceed to the feed circuit flowchan.

YES

NO

Is it +3V between IC409-@ and

@?

1---~

Docs the following waveform

appearat

IC403-®?

(Page

IO

[9])

Docs the disc stop immediately

when the stop button

is

pressed?

YES

OK

YES

Check the disc motor (MSOI) and its

connections.

Check the disc motor(M501) and its Is it -3V between

IC409-@

and@

connections.

---1

when the stop button is pressed?

Check the path between

IC403-®

and

IC409-@,

and also check

IC409.

NO

.._Y_ES~

ls

IC403-®

+IV

when the stop

button

is

pressed?

NO

YES

Check the connection between

IC403-®and JC409-@ , and also

check IC409.

Check IC401 and disc circuit 1C403.

13

8-4. Feed Circuit Flowchart

Are IC403-®>!© 5V

and

IC409-<1)/@/@9V?

YES

Can

the TOC be read?

YES

Can each track

be

searched?

NO

Does the following waveform

appear at

IC403-®

during search?

Searcb

outer

edge

Search

inner

edge

Vref

_I''lnJ-

--

~JUI-

YES

Does the following waveform

appear berween IC409- ® and @

during search? NO

Searcb

outer

edge

Searcb

inner

edge

ovI'lfUt---

~~

YES

Check the feed motor and its

connections.

-----

-

----

JI~\~

'c

'-i.

0 \

{~

·

14

-t

'

I ..

Check the feed circuit (IC403).

Check the path berween IC403- @

and IC409-@.

' .

o··

:~-:

· .

'

*,

:·" !

Does

IC403-®

(SSTOP) change YES

from 5V to

OV

when SW501

(P.U SW)

is

set to ON from OFF?

NO

Check the coMection bcrwccn

SW501 and

IC404-@

.

YES

Check that the following pins

are~

.

IC403 IC404

@ @

~

®

@ ®

®

~

IC403-@1. i:.-

lf

IC404-@J

J .

/l

'-r-C

3 -

l.

'-

''

'+cc.,.

-l.O

·.

..

IC101 CUSTOM CHIP

IC

MCE3

Pans

No

. : 315-5632

•TopView

157

208

156

.o

/NDEX

•

• Description

No

. 1/0 Pin Name

1 0

OCK25

2 0

OB

RAM

3 -

Vss

4 I

OXBROM

5 I

!ROM

6 I

ICASO

7 I

ILWR

8 I

IUWR

9 I !ASEL

JO

-

Vnn

11

I

IRAS2

12

I

ICAS2

13

I

IFDC

14

I

IFRES

15

-

Vs..,,

16

0

OERES

17

l!O

BEA

DO

18

l!O

BEAD!

19

1/0

BEAD2

20

l!O

BEAD3

21

l!O

BEAD4

22

1/0

BEADS

23

l!O

BEAD6

24 1

/0

BEAD7

25

1/0

BEDS

26 -

Vs..,,

27 -

Vnn

28 1/0

BED9

29 1/0

BEDlO

30 1/0 BEDll

31

1/0

BED12

32 1/0

BED13

33 1/0

BED14

34 1/0

BED15

3S

0

OERAS

36 0

OECAS

37 0 OEOE

3S

-

Vss

39 0 OEWE

40 0

OORAS

41

0

OOCAS

42

0

OOOE

105

0

104

0

53

52

No. 1/0 Pin

Name

43

-

Vnn

44 0

OOWE

45

1/0

BO

ADO

46

1/0 BOADl

47

l!O

BOAD2

4S

1/0

BOAD3

49

l!O

BOAD4

50 -

Vss

51

l!O

BOAD5

52

l!O

BOAD6

53

1/0

BOAD7

54

1/0

BODS

55

1/0

BOD9

56 1/0

BODIO

57

1/0

BODI

I

5S

1/0

BOD12

59

1/0

BOD13

60

-

Vs..,,

61

-

Vnn

62

1/0

BOD14

63

1/0

BOD15

64

0

OLEDR

65

0

OLEDG

66

0

OLATCH

67

0 OSHFf

6S

0

OATT

69

0

ODTM

70

I

IWFCK

71

I I

SCOR

72 -

Vs.<:.

73

I I

SBSO

74

0

OEXCK

75

I I

LR

CK

76

I

!DATA

77

I

IC2PO

7S

1/0

BDB3

79

-

Ynn

80 1/0

BDB2

SI

1/0 BDBl

82

1/0

BOBO

83

0

OHOCK

84

I

ICKSO

No. 1/0 Pin Name

No

. 1/0 Pin Name

S5

v

14

7 -

Vnn

S6

IIRQ

148

1/0 8D9

87

IDXM

149

1/0

8Dl0

SB

I

!COCK

lSO

1/0

8Dll

89

0

OX

PCM

lSl 1/0

8012

90 I

ID

TEN

1S2

1/0

8Dl3

91

1

!WAIT

1S3

1/0

8Dl4

92

0

OHRD

1S4

-

Vss

93

I

IINT

15S

1/0

8DlS

94 0

OCDC

1S6

1/0

BPRAO

95

0 OPROE

1S7

1/0 8PRA1

96

v

1S8

1/0 8PRA2

97

v

1S9

1/0 8PRA3

98

0

OC2LR

160

l!O

BPRA4

99

I

IA19

161

1/0 8PRA5

100

1

IA18

162

1/0

BPRA6

101

I

1A17

163

l!O

BPRA

7

102

I

IA16

164

-

Vs.<:.

103

I IAIS

16S

-

Vnn

104

I

IA14

166

1/0 8PRA8

lOS

1/0

BA13

167

0

OPRRAS

106

1/0

BA12

168

0

OPRCAS

107

v

169

0

OPRUWE

108

1/0 BAH

170

0

OPRLWE

109

1/0

BAIO

171

l!O

IVA!

llO 1/0

BA9

172

1/0

IVA2

111

1/0

BAB

173

1/0

IVA3

112

1/0

BA7

174

110

IVA4

113

1/0

BA6

175

1/0

!VAS

114

v

176

-

Vss

115

1/0

BAS

177

1/0

IVA6

116

1/0

BA4

178

1/0

IVA7

117

l!O

BA3

179

1/0

!VAS

118

1/0

BA2

180

1/0

IVA9

119

v

181

1/0

IVAIO

120

1/0 BAI

182

l!O !VAii

12

1 I

IFCO

183

-

Von

122

I IFCl 184 1/0

IVA12

123

0

OIPLD

185

1/0

IVA13

124

0 OIPLl

1S6

1/0

IVA14

12S

0 OIPL2

1S7

1/0 IVAlS

126

0

OVPA

lSS

1/0

IVA16

127

0

ORES

ET

1S9

-

Vs..,,

128

0

OHALT

190

1

IVA17

129

0

OCLK

191

1/0

BVDO

130 v

192

1/0

BVDI

131

v

193

1/0

BVD2

132

0

ODTACK

194

1/0

BVD3

133

I

IRXW

195

1/0

BVD4

134

1

IXLDS

196

1/0

BVD5

13S

I

IXUDS

197

1/0

BVD6

136

I

IXAS

198

1/0

BVD7

137

1/0

BOO

199

1/0

BVD8

138

1/0 BDI

200

-

Vss

139

1/0

BD2

201

-

Vnn

140

1/0

BD3

202

1/0

BVD9

141

1/0

804

203

1/0

BVDlO

142

v 204 1/0 BVDll

143

1/0

BD5

20S

1/0

BVD12

144

1/0

806

206

1/0

BVD13

145

1/0

BD7

207

1/0

BVD14

146

1/0

BDS

208

1/0 BVDIS

19

IC102/103

1Mblt

Dynamic

RAM IC104/105

8blt

CMOS

Static

RAM

IC TC511664BJ-80

IC UPD421664-80 IC TC421664LE-70

IC UPD421664-80L

•Top

View & Pin Layout

GND

11015

11014

11013

11012

AO-A7 : Address inputs

11011

11010

1/01-1/016 : Data inputs/outputs

1109

RAS : Row address strobe

IC CKX5864BM-70

IC MB8464-90 IC M88464-80

•Top

View & Pin Layout

1 A

10

CE1

AO-A

12 : Address inputs

1/01-1/08 : Data inputs

CE1.CE2 : Chip enable 1/2 inputs

WE : Write enable input

1

NC

CAS : Column address strobe 1

llOa

OE : Output enable input

GND

CAs

OE

NC

A1

As

A5

1 GND

IC106 CD-ROM LSI

IC LC89515

•TopView

80

• Description

No

.

1/0

Pin Name

I -

V~c:.

2 0

RA6

3 0

RA7

4 0

RAB

5 0

RA9

6 0

RAIO

7 0 RAll

8 0

RA12

9 0

RAI3

10 0

RA14

II 0

RAIS

I2

0

RWE

I3

-Vss

I4

0

ROE

IS

110

ERA

I6

110

108

I7

1/0

I07

18

110

106

I9

1/0

105

20

110

I04

20

uw

LW

OE

vcc

GND

NC

64

: High-order byte write

enable

: Low-order byte write

enable

: Output enable

: Supply voltage

: Ground

: Not connected.

41

24

No.

1/0

Pin Name

21

1/0

103

22

1/0

I02

23

110

IOI

24

-

V~c:.

25 I

EXT

AL

26

0

XTAL

27

I

TESTA

28

I TESTS

29

I

CSEL

30 I

LMSEL

31

-Vnn

32

I

LRCK

33

I

SDATA

34

I

BCK

35

I

C4LR

36

I

C2PO

37

0

MCK

38

1/0

DO

39

110

DI

40

110

02

Vee

: +SV supply

GND : Ground

NC : Not connected.

No.

1/0

Pin Name No.

1/0

Pin Name

41

-Vss

61

0

EOP

42

1/0

D3

62

0

RCS

43

1/0

04

63

0

HDE

44

1/0

DS

64

-

V~c:.

45

1/0

06

65

I/O

HD7

46

1/0

07

66

l/O

HD6

47

I

RS

67

1/0

HD5

48

I

RD

68

I/O

HD4

49

I

WR

69

1/0

HD3

50

I cs

70

1/0

HD2

51

0

INT

71

1/0

HDl

52

-

Vs..,,

72

I/O

HOO

53

I

RESET

73

-Ynn

54 I

ENABLE

74

I

SELDRO

55 I

HRW

75

0

RAO

56

I

HRD

76

0

RAl

57

I

CMD

77

0

RA2

58

0

WAIT

78

0

RA3

59

0

DTEN

79

0

RA4

60 0

STEN

80

0

RAS

IC107 CMOS

Dynamic

RAM

IC

UPD424270LE-80

IC

HM514270AJ-8

IC

M5M44270AJ-8

IC

MN414270SJ-08

•Top

View & Pin Layout

Vss

11015

11014

11013

11012

Vss

11011

Input

State

Output

Operation

Mode

RAS

CAS

I UWE I LWE

State

I

H H D D I Ooen Standby

11010

H L H H Valid Standby

1109

L L H H Valid Read cycle

L L L 2)

L2)

Open Early write cycle

NC

L L

L2)

I

L2)

Underlined Delayed write cycle

NC

L L

H-+L H-+L

Valid Read modified write cycle

'CAS

L H D D Open RAS onlv refresh cvcle

i5E

H-+L

L D D Open CAS before /RAS refresh cvcle

As

L

H-+L

H H Valid High-speed page mode read cycle

A1

L

H-+L

L2) L2)

Open High-speed page mode early write cycle

L

H-+L

L2)

Underlined High-speed page mode delayed write cycle

A5

L

H-+L

H-+L H-+L

Valid High-speed page mode read modified write cvcle

A4

Note: H=High(inactive), L=Low(active), D=Don't care.

1 Vss

IC108/109 Sblt CMOS

Pseudo

Static

RAM

IC

LH5P832N-10

IC

TC51832AFL-10

IC

TC51832FL-10

•Top

View & Pin Layout

Vee

RfW

A13

As

Ag

Au

OE/RFSH

1 A

10

CE

• Pin Configuration and Pin Description

Symbol Pin

Name

A,-A,. Address Input

R/W Read I Write Input

OE/

RFSH Output Enable I Refresh

CE

Chip Enable

1/0,-1/0, Data Input I Output

IC11O PCM

Sound

Source

IC

RF5C164A

Parts

No. : 315-5476A

•Top

View & Pin Layout

21

• Description (IC110)

Pin I

Name

,,0

I Function

No. 1

Name

1/0 Function

No.

78

Al2

79

All

75 RAMAi 0 Low address signals

of

the SRAM &

76

RA

MAO

MROM.

80 AlO 42

RA

MAX 0 LSB address signal

of

the MROM.

1 A9

2 A8

(i

I RAMC2B 0 High order 32k byte SRAM & MROM

select signal.

3 A7

4 A6 I Address signals from µ.P. 6060 Note: 0 Low order 32k byte SRAM & MROM

The inter- select signal.

5 i

AS

6 I A4 63 RAMWEB 0 Signal to write data to the pseudo

SRAM

or

SRAM.

7 I A3

8 A2 62 RAMOEB 0 Signal to read data from the pseudo

SRAM, SRAM

or

MROM.

9

Al

31

DAC7

10

AO

21

D7

22

D6

32 DAC6 Multiplex signals

of

"R" and "L" data

33 DAC5 0

34 DAC4 output to the parallel DAC.

23

DS

37 DAC3

24 D4

l!O

Data bus signals with µ.P.

25

D3 29 SHL 0 DAC7-3 "L" data sample/hold signal.

30 SHR 0 DAC7-3 "R" data sample/hold signal.

26

D2

27 DI 39 DAC7R 0 Signal obtained

by

sampling and

holding the DAC7 output at SHR.

28

DO

77 CSB I Chip select signal from

µ.

P. 38 DAC7L 0 Signal obtained

by

sampling and

holding the DAC7 output at SHL.

13

RDB I Read signal from

µ.P.

14

WRB I Write signal from µ.P.

41

WCLKl 0 Word clock signal output to the serial

DAC.

44

RAMAD7 When connected to a pseudo SRAM,

45

RAMAD6 these pins provide multiplex signals

of

40 LRCLK 0 LR clock signal output to the serial

DAC.

46

RA

MADS the low order address/data to the

47 RAMAD4 SRAM, and when connected to an

48

RAMAD3

110

MROM, these pins provide data input

signal from the MROM.

49 RAMAD2 When connected to an SRAM, these

36 DATA 0 Digital audio data signal output

to

the

serial DAC.

35 BCLK 0 Bit clock signal output to the serial

DAC.

50

RAMADI pins also provide data bus signals to the 64 RESETB I Reset signal.

51

RAMA

DO

SRAM. 70

XJN

I An external crystal oscillator IS

53 RAMAl4 connected.

54

RAMAl3

71

XOUT 0 A clock signal is input to XIN directly.

55 RAMA12 High order address signals

of

the SRAM

56

RAMAi!

0

57 RAMAIO

&MROM

.

16 TEST! Test signal inputs. Normally, fixed at

17 TEST2 I "L".

However, TEST2

is

fixed at "H" when

58 RAMA9

18

TEST3

an

MROM

or

SRAM

is

used.

59 RAMA8

65 RAMA7

66 RAMA6

67 RAMA5 0 Low address signals

of

the SRAM &

68 RAMA4 MROM.

73 RAMA3

74 RAMA2

12

-19 vcc Power supply pins.

--

43

-69

15

-GND Ground pins.

52 -

>-----

72

Note: The interface with the serial DAC

is

formed in the MSB initial mode.

22

• Block Diagram (IC110)

CPU

l/Fl==========================~A~DORE;:::~ss:;:==========================~

DATA

BUS

RAMA°'

RAMA/3

RAMAl2

RAMA11

RAMAIO

RAMA9

RAMA8

R&MA7

RAMA6

RA~

RAMA4

RAMA3

RAMA2

RAMAi

AAMAO

RAMAX

1----....i

INTERNAL

MEMORY

ADDRESS

POINTER

OCA

WAVE

DATA

RAMCIB

RAMC28

RAMA

..

.,,,.0

RAMA07

RAMAD6

RAMAO~

RAMA04

RAMAD3

RAMA02

llAMAOI

llAMAOO

RAMWEB

RAM

OE

RAMCIB

RAMC21!

1-----.....ir-~T~IM:l:N:G~CON:::::TROL=:-~-------l..J-----..J---~:..._--~---~OAU

---~

SERIAL

DAC

1/F

HCUU

TESTI~

TEST2~

TEST3o--+

XIN

XOUT

RE

ETR

IC111 1

Mblt

CMOS

Masked

Programable

ROM

IC

SEGA-C02 BOOT ROM

EP

IC

SEGA-C02 USA BOOT

ROM

IC

MEGA-C02 (PAL) BOOT ROM

•Top

View & Pin Layout

01

1

Oo

1

Vee

CEz!CE1

/D.C

OE2

/0E

1

/D.C

A15

A14

A13

A12

Au

A10

1

Ag

GNO

As

A1

As

A5

A4

A3

Az

OE1

/0E

1

-,,

___

_r-

• Block Diagram

A.

A,

A.

A,

A.

A,

~

A~

A

..

A.

A.,

Au

A.,

A.

• Operation Mode

·

et.

CE,

OE,

I x x

x I x

A A I

A A x

A A A

1-----oOllCLJ(

L--------t"-----t.OLRCLK

-----tlODA'7R

i.....----t.,

_______

_r-----.ODA7L.

LATCH

IC MEGA-C02 BOOT

EP

MULTI

OE

1

OE2

MEMORY CELL MATRIX

a:

85538 x 18 w

CE

1

""

BIT

""

:::>

ID

I-

~

CE

2

3:

OE, Mode Output

x

Non-

x selective

x High Impedance

I Selective

A

Data

23

"'

IC112

64k(8k

x S)blt

Static

RAM

IC MB8464A-10LL

•Top

View & Pin Layout

Vee

A12

WE

CS

2

As

A5

Ag

Ao-A12

:Address

inputs

A4

A11

1/01-1/08 :

Data

inputs/outputs

As

~

CS

1 :

Chip

select

1

A2

1

A10

CS

2 :

Chip

select

2

CS

1

OE

:

Output

enable

WE

:Write

enable

Vee

:Power

supply

(+SV)

GND

:

Ground

NC

:Not

connected

IC113

16/32-Blt

Microprocessor

24

IC MC68HCOOOFN12 IC

HDSBHCOOOCP-12

•Top

View & Pin Layout

V, -

CLK

GND

013

014

015

GNO

GND

A23

A22

A21

A19

All

A17

A16

A15

A1'

A13

• Block Diagram

A12

>

) 0

::D

0 0

::D

)

~

m

(/)

0

(/)

m

= 0

c:

0

,,

0

,,

m

::D

A5

::D

cs

A•

~

DDRES

BUFFER

Ao cs

OE

INPUT

BUFFER

WE

cs

CS

1

~

CSz

CS

IC

TMPSBHCOOOT-12

• Signal Description

PROCESSOR

STATUS

M8800

PERIPHERAL

CONTROL

SYSTEM

CONTROL

VCC{2)

GND{2)

CLK

{~

FCO

FC1

FC2

E

{

iiMA

VPA

{='

-HALT

MC88HCOOO

--OVc

c

--0

GND

( MEMORY CELL ARRAY

)

2sex32xe

---

1/0 GATE. COLUMN

DECODER

-

INPUT/OUTPUT

CS

BUFFER

ADDRESS B

us

23-A1

}A

DATA BUS

}DI

,,

AS

RN/

-.

UDS

)

~

OT

ACK

--

BR

-

liG -

BGACK

-

nsro

}

iPi:1"

iPil

5-00

ASYNCHRONOUS

BUS CONTROL

BUS

ARBITRATION

CONTROL

INTERRUPT

CONTROL

·

'!'"

·

Sega CD II User manual

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