Sharp Blue Treak LH75400 User manual

LH75400/01/10/11
System-on-Chip
Preliminary User’s Guide
7/15/03

Specifications are subject to change without notice.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on spe-
cial applications. See Limited Warranty for Sharp’s product warranty. The Limited Warranty is in lieu,
and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRAN-
TIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FIT-
NESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will Sharp
be liable, or inany way responsible, for any incidental or consequential economic or property damage.
BlueStreak is a trademark (pending) of SHARP Microelectronics of the Americas
ARM7TDMI-S is a trademark of Advanced RISC Machines, United Kingdom.
Motorola SPI is a trademark of Motorola, Inc.
National Semiconductor Microwire is a trademark of National Semiconductor Corporation
LH75400/01/10/11 System-on-Chip Preliminary User’s Guide
Produced by the SHARP Microelectronics of the Americas Technical Publication Group.
© 2003 Copyright SHARP Microelectronics of the Americas. Printed and Bound in USA.
Reference No. SMA02058

6/17/03 i
Table of Contents
Preface
Supplemental Documentation...............................................................................xxxi
Terms and Conventions........................................................................................xxxi
Multiplexed Pins ................................................................................................xxxi
Pin Names........................................................................................................xxxii
Peripheral Devices ........................................................................................... xxxii
Register Names................................................................................................xxxii
Register Addresses..........................................................................................xxxii
Register Tables ............................................................................................... xxxiii
Chapter 1 – Introduction
1.1 Product Overview.............................................................................................1-1
1.2 ARM and Thumb State.....................................................................................1-2
1.3 Bus Architecture...............................................................................................1-2
1.4 Operating Modes..............................................................................................1-3
1.4.1 Normal Mode.............................................................................................1-4
1.4.2 PLL Bypass Mode .....................................................................................1-4
1.4.3 Embedded ICE Mode................................................................................1-4
1.5 Power Supplies ................................................................................................1-4
1.5.1 Linear Regulator Power.........................................................................1-5
1.5.1.1 PLL Power..........................................................................................1-5
1.5.1.2 PCB Mounted Analog Power Supply Filter for PLL Usage.................1-5
1.5.2 Real-World Component Selection.........................................................1-6
1.6 Crystal Oscillator Usage...................................................................................1-7
1.7 Clocking Strategy.............................................................................................1-7
1.8 Reset Strategy..................................................................................................1-8
Chapter 2 – LH75401 SoC
2.1 LH75401 Features............................................................................................2-1
2.2 LH75401 Block Diagram ..................................................................................2-2
2.3 LH75401 Applications ......................................................................................2-3
2.4 LH75401 Pin Diagram......................................................................................2-4
2.5 LH75401 Numerical Pin Listing........................................................................2-5
2.6 LH75401 Signal Descriptions...........................................................................2-9
Chapter 3 – LH75411 SoC
3.1 LH75411 Features............................................................................................3-1
3.2 LH75411 Block Diagram ..................................................................................3-2
3.3 LH75411 Applications ......................................................................................3-3
3.4 LH75411 Pin Diagram......................................................................................3-4
3.5 LH75411 Numerical Pin Listing........................................................................3-5
3.6 LH75411 Signal Descriptions...........................................................................3-9

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
ii 6/17/03
Chapter 4 – LH75400 SoC
4.1 LH75400 Features............................................................................................4-1
4.2 LH75400 Block Diagram ..................................................................................4-2
4.3 LH75400 Applications ......................................................................................4-3
4.4 LH75400 Pin Diagram......................................................................................4-4
4.5 LH75400 Numerical Pin Listing........................................................................4-5
4.6 LH75400 Signal Descriptions...........................................................................4-9
Chapter 5 – LH75410 SoC
5.1 LH75410 Features............................................................................................5-1
5.2 LH75410 Block Diagram ..................................................................................5-2
5.3 LH75410 Applications ......................................................................................5-3
5.4 LH75410 Pin Diagram......................................................................................5-4
5.5 LH75410 Numerical Pin Listing........................................................................5-5
5.6 LH75410 Signal Descriptions...........................................................................5-9
Chapter 6 – Memory Interface Architecture
Chapter 7 – Static Memory Controller
7.1 SMC Features..................................................................................................7-1
7.2 SMC Theory of Operation ................................................................................7-2
7.2.1 SMC Write Process...................................................................................7-2
7.2.2 SMC Read Process...................................................................................7-4
7.2.3 SMC Burst Mode Read Process ...............................................................7-4
7.2.4 External Memory Bus Cycle......................................................................7-8
7.2.5 External Bus Read/Write Operations........................................................7-9
7.2.6 SMC Memory Connection Diagram.........................................................7-11
7.3 SMC Programmer’s Model.............................................................................7-12
7.3.1 SMC Register Summary..........................................................................7-12
7.3.2 SMC Register Definitions........................................................................7-13
7.3.2.1 Configuration Register for Memory Bank 0 ......................................7-13
7.3.2.2 Configuration Register for Memory Bank 1 ......................................7-15
7.3.2.3 Configuration Register for Memory Bank 2 ......................................7-17
7.3.2.4 Configuration Register for Memory Bank 3 ......................................7-19
7.3.3 SMC Default Memory Widths..................................................................7-21
Chapter 8 – Static Random Access Memory Controller
Chapter 9 – Reset, Clock, and Power Controller
9.1 RCPC Features................................................................................................9-2
9.2 RCPC Theory of Operation..............................................................................9-2
9.2.1 Reset Generation ......................................................................................9-3
9.2.2 Clock Generation.......................................................................................9-4
9.2.3 RCPC Power Modes .................................................................................9-4
9.2.3.1 Active Mode........................................................................................9-5
9.2.3.2 Standby Mode ....................................................................................9-5
9.2.3.3 Sleep Mode ........................................................................................9-5
9.2.3.4 Stop1 Mode........................................................................................9-5
9.2.3.5 Stop2 Mode........................................................................................9-5
9.3 RCPC Programmer’s Model.............................................................................9-6

LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents
6/17/03 iii
9.3.1 RCPC Register Summary .........................................................................9-6
9.3.2 RCPC Register Definitions........................................................................9-7
9.3.2.1 Control Register..................................................................................9-7
9.3.2.2 Identification Register.........................................................................9-8
9.3.2.3 Remap Control Register.....................................................................9-8
9.3.2.4 Soft Reset Register ............................................................................9-9
9.3.2.5 Reset Status Register.......................................................................9-10
9.3.2.6 Reset Status Clear Register.............................................................9-11
9.3.2.7 HCLK Prescaler Register .................................................................9-12
9.3.2.8 Peripheral Clock Control Register 0.................................................9-13
9.3.2.9 Peripheral Clock Control Register 1.................................................9-14
9.3.2.10 AHB Clock Control Register...........................................................9-15
9.3.2.11 LCD Clock Prescaler Register........................................................9-16
9.3.2.12 SSP Clock Prescaler Register........................................................9-17
9.3.2.13 External Interrupt Configuration Register.......................................9-18
9.3.2.14 External Interrupt Clear Register....................................................9-20
Chapter 10 – Vectored Interrupt Controller
10.1 Theory of Operation .....................................................................................10-1
10.1.1 Interrupts...............................................................................................10-1
10.1.2 VIC Interrupt Listing...............................................................................10-2
10.1.3 Vectored Interrupts................................................................................10-3
10.1.4 External Interrupts.................................................................................10-3
10.1.5 Clearing Interrupts.................................................................................10-4
10.1.6 Priority ...................................................................................................10-4
10.1.7 Sequencing ...........................................................................................10-5
10.1.8 External Level-Sensitive Interrupts........................................................10-7
10.1.9 Software Guidelines ..............................................................................10-7
10.2 VIC Programmer’s Model.............................................................................10-7
10.2.1 VIC Register Summary..........................................................................10-8
10.2.2 VIC Register Definitions ........................................................................10-9
10.2.2.1 IRQ Status Register........................................................................10-9
10.2.2.2 FIQ Status Register......................................................................10-10
10.2.2.3 Raw Interrupt Status Register ......................................................10-11
10.2.2.4 Interrupt Select Register...............................................................10-12
10.2.2.5 Interrupt Enable Register..............................................................10-13
10.2.2.6 Interrupt Enable Clear Register....................................................10-14
10.2.2.7 Software Interrupt Register...........................................................10-15
10.2.2.8 Software Interrupt Clear Register.................................................10-16
10.2.2.9 Vector Address Register...............................................................10-17
10.2.2.10 Default Vector Address Register................................................10-18
10.2.2.11 Vector Address Registers...........................................................10-19
10.2.2.12 Vector Control Registers ............................................................10-20

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
iv 6/17/03
Chapter 11 – I/O Configuration
11.1 IOCON Theory of Operation.........................................................................11-1
11.2 IOCON Programmer’s Model.......................................................................11-2
11.2.1 IOCON Register Summary....................................................................11-2
11.2.2 IOCON Register Definitions ..................................................................11-3
11.2.2.1 EBI Interface Muxing Register........................................................11-3
11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register................................11-5
11.2.2.3 Pins PE7/SSPRM to PD0/INT0 Muxing Register...........................11-6
11.2.2.4 Timer Muxing Register ...................................................................11-8
11.2.2.5 LCD Mode Muxing Register .........................................................11-10
11.2.2.6 Pins PA7/D15 to PA0/D8 Resistor Muxing Register.....................11-11
11.2.2.7 Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register............11-13
11.2.2.8 Pins PC7/A23 to PC0/A16 Resistor Muxing Register...................11-14
11.2.2.9 Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register................11-16
11.2.2.10 Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register 11-18
11.2.2.11 Pins AN7/PJ7 to AN0/PJ0..........................................................11-20
Chapter 12 – Direct Memory Access Controller
12.1 DMA Controller Features..............................................................................12-1
12.2 DMA Theory Of Operation............................................................................12-2
12.2.1 Interrupt, Error, and Status Registers....................................................12-4
12.2.2 DMA Controller Timing Diagrams..........................................................12-4
12.3 DMA Programmer’s Model...........................................................................12-7
12.3.1 DMA Controller Register Summary.......................................................12-7
12.3.2 DMA Controller Register Definitions......................................................12-8
12.3.2.1 Source Base Registers...................................................................12-8
12.3.2.2 Destination Base Register..............................................................12-8
12.3.2.3 Maximum Count Register...............................................................12-8
12.3.2.4 Control Register..............................................................................12-9
12.3.2.5 Current Source Registers.............................................................12-11
12.3.2.6 Current Destination Registers ......................................................12-11
12.3.2.7 Terminal Count Register...............................................................12-11
12.3.2.8 Interrupt Mask Register................................................................12-12
12.3.2.9 Interrupt Clear Register................................................................12-13
12.3.2.10 Status Register...........................................................................12-14
Chapter 13 – Color Liquid Crystal Display Controller
13.1 CLCDC Features..........................................................................................13-3
13.2 CLCDC Theory of Operation........................................................................13-4
13.2.1 LCD DMA FIFOs ...................................................................................13-4
13.2.2 Pixel Serializer.......................................................................................13-4
13.2.3 How Pixels are Stored in Memory.........................................................13-5
13.2.4 Palette RAM ..........................................................................................13-6
13.2.5 Grayscale Algorithm..............................................................................13-7
13.2.6 LCD Panel Resolutions.........................................................................13-7
13.3 CLCDC Programmer’s Model.....................................................................13-10
13.3.1 CLCDC Register Summary .................................................................13-10
13.3.2 CLCDC Register Definitions................................................................13-11

LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents
6/17/03 v
13.3.2.1 Horizontal Timing Panel Control Register ....................................13-11
13.3.2.2 Horizontal Timing Restrictions......................................................13-12
13.3.2.3 Vertical Timing Panel Control Register.........................................13-13
13.3.2.4 Clock and Signal Polarity Control Register...................................13-14
13.3.2.5 Upper Panel Frame Buffer Base Address Register......................13-15
13.3.2.6 Lower Panel Frame Buffer Base Address Register......................13-16
13.3.2.7 Interrupt Enable Register..............................................................13-17
13.3.2.8 LCD Panel Parameters, LCD Panel Power, and
CLCDC Control Register........................................................................13-18
13.3.2.9 Raw Interrupt Status Register ......................................................13-20
13.3.2.10 Final Masked Interrupts Register................................................13-21
13.3.2.11 LCD Upper Panel Frame Buffer Current Address Register........13-22
13.3.2.12 256 × 16-bit Color Palette Register............................................13-23
13.3.3 CLCDC Interrupts................................................................................13-24
13.4 HR-TFT Controller......................................................................................13-24
13.4.1 HRTFTC Operating Modes .................................................................13-24
13.4.1.1 Bypass Mode................................................................................13-24
13.4.1.2 HR-TFT Mode...............................................................................13-24
13.4.2 HRTFTC Theory of Operation.............................................................13-25
13.4.3 HRTFTC Programmer’s Model............................................................13-25
13.4.4 HRTFTC Register Summary ...............................................................13-25
13.4.5 HRTFTC Register Definitions..............................................................13-26
13.4.5.1 Setup Register..............................................................................13-26
13.4.5.2 Control Register............................................................................13-27
13.4.5.3 Timing1 Register ..........................................................................13-28
13.4.5.4 Timing2 Register ..........................................................................13-29
13.5 Timing Waveforms .....................................................................................13-30
13.5.1 STN Horizontal Timing ........................................................................13-30
13.5.2 STN Vertical Timing ............................................................................13-30
13.5.3 TFT Horizontal Timing.........................................................................13-30
13.5.4 TFT Vertical Timing.............................................................................13-30
13.5.5 HR-TFT Horizontal Timing Waveforms ...............................................13-30
13.5.6 HR-TFT Vertical Timing Waveforms....................................................13-30
Chapter 14 – Liquid Crystal Display Controller
14.1 LCDC Features ............................................................................................14-3
14.2 LCDC Theory of Operation...........................................................................14-3
14.2.1 LCD DMA FIFOs ...................................................................................14-4
14.2.2 Pixel Serializer.......................................................................................14-4
14.2.3 How Pixels are Stored in Memory.........................................................14-4
14.2.4 Palette RAM ..........................................................................................14-5
14.2.5 Grayscale Algorithm..............................................................................14-5
14.2.6 Supported Grayscale.............................................................................14-6
14.3 LCDC Programmer’s Model.........................................................................14-7
14.3.1 LCDC Register Summary......................................................................14-7
14.3.2 LCDC Register Definitions ....................................................................14-8
14.3.2.1 Horizontal Timing Panel Control Register ......................................14-8
14.3.2.2 Horizontal Timing Restrictions........................................................14-9

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
vi 6/17/03
14.3.2.3 Vertical Timing Panel Control Register.........................................14-10
14.3.2.4 Clock and Signal Polarity Control Register...................................14-11
14.3.2.5 Upper Panel Frame Buffer Base Address Register......................14-12
14.3.2.6 Lower Panel Frame Buffer Base Address Register......................14-13
14.3.2.7 Interrupt Enable Register..............................................................14-14
14.3.2.8 LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register...........................................................................14-15
14.3.2.9 Raw Interrupt Status Register ......................................................14-17
14.3.2.10 Final Masked Interrupts Register................................................14-18
14.3.2.11 LCD Upper Panel Frame Buffer Current Address Register........14-19
14.3.2.12 LCD Palette Register..................................................................14-20
14.3.3 LCDC Interrupts ..................................................................................14-20
Chapter 15 – Timers
15.1 Timer Theory of Operation...........................................................................15-5
15.1.1 Count Timing.........................................................................................15-5
15.1.2 Counter Clear Upon Compare Match....................................................15-6
15.1.3 Capture Signal Sampling.......................................................................15-7
15.1.4 PWM Mode............................................................................................15-7
15.2 Timer Programmer’s Model..........................................................................15-9
15.2.1 Timer Register Summary ......................................................................15-9
15.2.2 Timer Register Definitions...................................................................15-10
15.2.2.1 Timer 0 Control Register ..............................................................15-10
15.2.2.2 Timer 0 Compare/Capture Control Register................................15-11
15.2.2.3 Timer 0 Interrupt Control Register................................................15-13
15.2.2.4 Timer 0 Status Register................................................................15-14
15.2.2.5 Timer 0 Counter Register.............................................................15-15
15.2.2.6 Timer 0 Compare Registers .........................................................15-16
15.2.2.7 Timer 0 Capture Registers ...........................................................15-17
15.2.2.8 Timer 1 Control Register ..............................................................15-18
15.2.2.9 Timer 1 Interrupt Control Register................................................15-20
15.2.2.10 Timer 1 Status Register..............................................................15-21
15.2.2.11 Timer 1 Counter Register...........................................................15-22
15.2.2.12 Timer 1 Compare Registers .......................................................15-23
15.2.2.13 Timer 1 Capture Registers .........................................................15-24
15.2.2.14 Timer 2 Control Register ............................................................15-25
15.2.2.15 Timer 2 Interrupt Control Register..............................................15-27
15.2.2.16 Timer 2 Status Register..............................................................15-28
15.2.2.17 Timer 2 Counter Register...........................................................15-29
15.2.2.18 Timer 2 Compare Registers .......................................................15-30
15.2.2.19 Timer 2 Capture Registers .........................................................15-31
15.2.2.20 Timer Interrupts..........................................................................15-32

LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents
6/17/03 vii
Chapter 16 – Watchdog Timer
16.1 WDT Features..............................................................................................16-1
16.2 WDT Theory of Operation............................................................................16-2
16.3 WDT Programmer’s Model...........................................................................16-2
16.3.0.1 WDT Register Summary.................................................................16-2
16.3.1 WDT Register Definitions......................................................................16-3
16.3.1.1 Control Register..............................................................................16-3
16.3.1.2 Counter Reset Register..................................................................16-4
16.3.1.3 Status Register...............................................................................16-5
16.3.1.4 Counter Section 0 Register ............................................................16-6
16.3.1.5 Counter Section 1 Register ............................................................16-6
16.3.1.6 Counter Section 2 Register ............................................................16-7
16.3.1.7 Counter Section 3 Register ............................................................16-7
Chapter 17 – Real-Time Clock
17.1 RTC Features...............................................................................................17-1
17.2 RTC Theory of Operation.............................................................................17-2
17.3 RTC Programmer’s Model............................................................................17-3
17.3.1 RTC Register Summary ........................................................................17-3
17.3.2 RTC Register Definitions.......................................................................17-4
17.3.2.1 Data Register 0...............................................................................17-4
17.3.2.2 Data Register 1...............................................................................17-5
17.3.2.3 Match Register 0 ............................................................................17-6
17.3.2.4 Match Register 1 ............................................................................17-6
17.3.2.5 Interrupt Status/Clear .....................................................................17-7
17.3.2.6 Read/Write Load Register 0...........................................................17-8
17.3.2.7 Read/Write Load Register 1...........................................................17-9
17.3.2.8 Control Register............................................................................17-10
17.3.3 RTC Interrupts.....................................................................................17-10
Chapter 18 – Synchronous Serial Port
18.1 SSP Features...............................................................................................18-1
18.2 SSP Theory Of Operation ............................................................................18-3
18.3 SSP Timing Waveforms...............................................................................18-4
18.3.1 Motorola SPI Frame Format..................................................................18-5
18.3.2 Texas Instruments Frame Format.........................................................18-7
18.3.3 National Semiconductor Frame Format ................................................18-8
18.4 Clock Generation..........................................................................................18-8
18.5 SSP Programmer’s Model..........................................................................18-11
18.5.1 SSP Register Summary ......................................................................18-11
18.5.2 SSP Register Definitions.....................................................................18-12
18.5.2.1 Control Register 0.........................................................................18-12
18.5.2.2 Control Register 1.........................................................................18-13
18.5.2.3 Receive / Transmit FIFO Register................................................18-14
18.5.2.4 Status Register.............................................................................18-15
18.5.2.5 Clock Prescale Register...............................................................18-16
18.5.2.6 Interrupt Identification/Clear Register...........................................18-17
18.5.2.7 Receive Timeout Register............................................................18-18

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
viii 6/17/03
18.5.3 SSP Interrupts.....................................................................................18-19
18.5.3.1 Receive Interrupt..........................................................................18-19
18.5.3.2 Transmit Interrupt.........................................................................18-19
18.5.3.3 Receive Overrun Interrupt............................................................18-19
18.5.3.4 Receive Timeout Interrupt............................................................18-20
18.5.3.5 SSPINTR......................................................................................18-20
Chapter 19 – UART0 and UART1
19.1 UART0 and UART1 Features.......................................................................19-2
19.2 UART0 and UART1 Theory of Operation.....................................................19-2
19.2.1 UART0 and UART1 Receiver Data Frame............................................19-2
19.2.2 Status Conditions ..................................................................................19-3
19.2.3 On-Chip DMA Capabilities ....................................................................19-4
19.2.4 Programming Control Registers............................................................19-4
19.3 UART0 and UART1 Programmer’s Model ...................................................19-5
19.3.0.1 UART0 and UART1 Register Summary ........................................19-5
19.3.1 UART0 and UART1 Register Definitions...............................................19-6
19.3.1.1 Data Register..................................................................................19-6
19.3.1.2 Receive Status/Error Clear Register..............................................19-8
19.3.1.3 Flag Register................................................................................19-10
19.3.1.4 UART Line Control Register.........................................................19-11
19.3.1.5 Integer Baud Rate Divisor Register..............................................19-12
19.3.1.6 Fractional Baud Rate Divisor Register .........................................19-13
19.3.1.7 Calculating the Divisor Value........................................................19-14
19.3.1.8 Typical Bit Rates and Their Corresponding Divisor......................19-14
19.3.1.9 Line Control Register....................................................................19-15
19.3.1.10 UART Control Register...............................................................19-17
19.3.1.11 Interrupt FIFO Level Select Register..........................................19-18
19.3.1.12 Interrupt Mask Set/Clear Register..............................................19-19
19.3.1.13 Raw Interrupt Status Register ....................................................19-21
19.3.1.14 Masked Interrupt Status Register...............................................19-22
19.3.1.15 ICR .............................................................................................19-23
19.3.1.16 DMACTRL..................................................................................19-24
19.3.2 UART0 and UART1 Interrupts.............................................................19-25
19.3.2.1 UARTRXINTR ..............................................................................19-25
19.3.2.2 UARTTXINTR...............................................................................19-25
19.3.2.3 UARTINTR ...................................................................................19-25
Chapter 20 – UART2
20.1 UART2 Features ..........................................................................................20-2
20.2 UART2 Theory of Operation.........................................................................20-2
20.2.1 UART Receiver Data Frame .................................................................20-3
20.2.2 Status Conditions ..................................................................................20-5
20.2.3 Disabling the Loading of Incoming Characters......................................20-5
20.2.4 Baud Rate Generators ..........................................................................20-6
20.3 UART2 Programmer’s Model.......................................................................20-7
20.3.1 UART2 Register Summary....................................................................20-7
20.3.1.1 Register Bank 0..............................................................................20-7

LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents
6/17/03 ix
20.3.1.2 Register Bank 1..............................................................................20-8
20.3.1.3 Register Bank 2..............................................................................20-8
20.3.1.4 Register Bank 3..............................................................................20-9
20.3.2 UART2 Register Definitions ................................................................20-10
20.3.2.1 Transmit Buffered Data Register..................................................20-10
20.3.2.2 Receive Buffered Data Register...................................................20-11
20.3.2.3 BRGA Divisor Least Significant Byte Register .............................20-12
20.3.2.4 BRGA Divisor Most Significant Byte Register ..............................20-13
20.3.2.5 General Enable Register..............................................................20-14
20.3.2.6 General Interrupt/Bank Register...................................................20-15
20.3.2.7 Line Control Register....................................................................20-17
20.3.2.8 Loopback Control Register...........................................................20-19
20.3.2.9 Line Status Register.....................................................................20-20
20.3.2.10 Address/Control Character Register0........................................20-21
20.3.2.11 Transmit Character Flag Register ..............................................20-22
20.3.2.12 Received Character Flags Register............................................20-23
20.3.2.13 Timer Control Register ...............................................................20-24
20.3.2.14 Timer Status Register.................................................................20-25
20.3.2.15 FIFO Level Register ...................................................................20-26
20.3.2.16 Receive Command Register.......................................................20-27
20.3.2.17 Receive Machine Status Register ..............................................20-28
20.3.2.18 Transmit Command Register......................................................20-29
20.3.2.19 Internal Command Register........................................................20-30
20.3.2.20 General Status Register.............................................................20-31
20.3.2.21 FIFO Mode Register...................................................................20-32
20.3.2.22 Transmit Machine Mode Register...............................................20-33
20.3.2.23 Internal Mode Register...............................................................20-34
20.3.2.24 Address/Control Character Register 1........................................20-35
20.3.2.25 Receive Interrupt Enable Register..............................................20-36
20.3.2.26 Receive Machine Mode Register................................................20-37
20.3.2.27 Clocks Configure Register..........................................................20-38
20.3.2.28 BRGA Configuration Register.....................................................20-39
20.3.2.29 BRGB Divisor Least Significant Byte Register ...........................20-40
20.3.2.30 BRGB Divisor Most Significant Byte Register ............................20-41
20.3.2.31 BRGB Configuration Register.....................................................20-42
20.3.2.32 Timer Interrupt Enable Register .................................................20-43
20.3.3 UART2 Interrupts ................................................................................20-44
20.3.3.1 Acknowledge Modes ....................................................................20-44
20.3.3.2 Interrupt Service...........................................................................20-45
Chapter 21 – General Purpose Input/Output
21.1 GPIO Features.............................................................................................21-2
21.2 GPIO Theory of Operation ...........................................................................21-2
21.2.1 GPIO Programmer’s Model...................................................................21-3
21.2.2 GPIO Registers Summary.....................................................................21-3
21.2.3 GPIO Register Definitions .....................................................................21-4
21.2.3.1 Port A Data Register.......................................................................21-4
21.2.3.2 Port B Data Register.......................................................................21-5

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
x 6/17/03
21.2.3.3 Port A Data Direction Register .......................................................21-6
21.2.3.4 Port B Data Direction Register .......................................................21-7
21.2.3.5 Port C Data Register ......................................................................21-8
21.2.3.6 Port D Data Register ......................................................................21-9
21.2.3.7 Port C Data Direction Register.....................................................21-10
21.2.3.8 Port D Data Direction Register.....................................................21-11
21.2.3.9 Port E Data Register.....................................................................21-12
21.2.3.10 Port F Data Register...................................................................21-13
21.2.3.11 Port E Data Direction Register ...................................................21-14
21.2.3.12 Port F Data Direction Register....................................................21-15
21.2.3.13 Port G Data Register..................................................................21-16
21.2.3.14 Port H Data Register ..................................................................21-17
21.2.3.15 Port G Data Direction Register...................................................21-18
21.2.3.16 Port H Data Direction Register...................................................21-19
21.2.3.17 Port I Data Register....................................................................21-20
21.2.3.18 Port J Data Register...................................................................21-21
21.2.3.19 Port I Data Direction Register.....................................................21-22
Chapter 22 – Controller Area Network
22.1 CAN 2.0B Features......................................................................................22-2
22.2 CAN Theory of Operation.............................................................................22-2
22.2.1 Protocols ...............................................................................................22-3
22.2.2 Frame Types .........................................................................................22-3
22.2.2.1 Message Frame..............................................................................22-3
22.2.2.2 Remote Frame................................................................................22-4
22.2.2.3 Bit Errors.........................................................................................22-4
22.2.2.4 Message Errors..............................................................................22-4
22.2.2.5 Acknowledgement Errors ...............................................................22-4
22.2.3 Transmitted and Received Data............................................................22-4
22.2.4 Time Delays ..........................................................................................22-5
22.2.5 Bus Timing ............................................................................................22-5
22.2.6 Bus Arbitration.......................................................................................22-5
22.2.7 Error Handling .......................................................................................22-6
22.3 CAN Programmer’s Model ...........................................................................22-6
22.3.1 CAN Register Summary........................................................................22-7
22.3.2 CAN Register Definitions.......................................................................22-8
22.3.2.1 Mode Register................................................................................22-8
22.3.2.2 Command Register.........................................................................22-9
22.3.2.3 Status Register.............................................................................22-10
22.3.2.4 Interrupt Register..........................................................................22-12
22.3.2.5 Interrupt Enable Register..............................................................22-13
22.3.2.6 Bus Timing Register 0..................................................................22-14
22.3.2.7 Bus Timing Register 1..................................................................22-15
22.3.2.8 Arbitration Lost Capture Register.................................................22-16
22.3.2.9 Error Code Capture Register........................................................22-18
22.3.2.10 Error Warning Limit Register......................................................22-20
22.3.2.11 Receive Error Counter Register .................................................22-21
22.3.2.12 Transmit Error Counter Register ................................................22-22

LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents
6/17/03 xi
22.3.2.13 Transmit Buffer...........................................................................22-23
22.3.2.14 Transmit Buffer Descriptor Field.................................................22-24
22.3.2.15 CAN Receive Buffer ...................................................................22-26
22.3.2.16 Receive Buffer Descriptor Field..................................................22-27
22.3.2.17 Acceptance Code Registers.......................................................22-27
22.3.2.18 Acceptance Mask Registers (AMR0 - AMR3) ............................22-27
22.3.2.19 Receive Message Counter Register...........................................22-28
22.3.2.20 Receive Buffer Start Address Register.......................................22-29
22.3.3 CAN Reset Mode ................................................................................22-30
22.3.4 CAN Acceptance Filtering ...................................................................22-32
Chapter 23 – Analog-to-Digital Converter/Brownout Detector
23.1 ADC Features...............................................................................................23-3
23.1.1 Bias-and-Control Network .....................................................................23-3
23.1.2 Clock Generator....................................................................................23-3
23.1.3 Brownout Detector.................................................................................23-4
23.1.4 SAR Architecture...................................................................................23-5
23.2 ADC Theory of Operation.............................................................................23-7
23.3 ADC Programmer’s Model ...........................................................................23-8
23.3.1 ADC Registers Summary ......................................................................23-8
23.3.2 ADC Register Definitions.......................................................................23-9
23.3.2.1 High Word Register........................................................................23-9
23.3.2.2 Control Bank Low Word Register.................................................23-11
23.3.2.3 Results Register...........................................................................23-12
23.3.2.4 Interrupt Masking/Enabling Register ............................................23-13
23.3.2.5 Power Configuration Register.......................................................23-14
23.3.2.6 General Configuration Register....................................................23-16
23.3.2.7 Sequence Start Mode Issues .......................................................23-17
23.3.2.8 General Status Register...............................................................23-18
23.3.2.9 Interrupt Status Register...............................................................23-19
23.3.2.10 FIFO Status Register..................................................................23-20
23.3.2.11 Control Bank Registers...............................................................23-21
23.3.2.12 Idle High Word Register .............................................................23-22
23.3.2.13 Idle Low Word Register..............................................................23-23
23.3.2.14 Masked Interrupt Status Register...............................................23-24
23.3.2.15 Interrupt Clear Register..............................................................23-25
23.3.3 ADC Timing Formulas.........................................................................23-26
23.3.4 ADC Interrupts.....................................................................................23-26
23.3.4.1 Brownout Interrupt........................................................................23-27
23.3.4.2 Pen Interrupt.................................................................................23-27
23.3.4.3 End-of-Sequence Interrupt...........................................................23-27
23.3.4.4 FIFO Watermark Interrupt ............................................................23-27
23.3.4.5 FIFO Overrun Interrupt.................................................................23-28
Chapter 24 – LCD Pin Multiplexing
24.1 LCD Panel Signal Multiplexing Details.........................................................24-1

Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide
xii 7/15/03
Chapter 25 – Recommended Layout Practices
25.1 Protecting Against ElectroStatic Discharge..................................................25-1
25.1.1 Special ESD Considerations .................................................................25-1
25.2 Printed Circuit Board Layout Practices.........................................................25-2
25.2.1 Power Supply Decoupling .....................................................................25-2
25.2.2 Required VDDA_PLL, VSSA_PLL Filter ...............................................25-2
25.2.3 Unused Input Signal Conditioning.........................................................25-3
25.2.4 Other Circuit Board Layout Practices....................................................25-3
Chapter 26 – Register Map
26.1 SMC Registers.............................................................................................26-1
26.2 RCPC Registers...........................................................................................26-2
26.3 VIC Registers...............................................................................................26-3
26.4 IOCON Registers .........................................................................................26-5
26.5 DMA Controller Registers.............................................................................26-5
26.6 DMA Stream Registers.................................................................................26-6
26.7 CLCDC Registers.........................................................................................26-7
26.8 HR-TFTC Registers......................................................................................26-7
26.9 LCDC Registers ...........................................................................................26-8
26.10 Timer Registers..........................................................................................26-9
26.11 WDT Registers.........................................................................................26-10
26.12 RTC Registers..........................................................................................26-10
26.13 SSP Registers..........................................................................................26-11
26.14 UART0 and UART1 Registers..................................................................26-11
26.15 UART2 Registers .....................................................................................26-12
26.16 GPIO Registers........................................................................................26-13
26.17 CANBUS Controller Registers..................................................................26-14
26.18 ADC Registers..........................................................................................26-15
Chapter 27 – Glossary

6/17/03 xiii
List of Figures
Preface
Figure 1. Multiplexer................................................................................................xxxiv
Figure 2. Register with Bit Field Named..................................................................xxxiv
Figure 3. Register with Multiple Bit Fields Named....................................................xxxv
Figure 4. Register with Bit Field Named...................................................................xxxv
Chapter 1 – Introduction
Figure 1-1. Crystal Oscillator......................................................................................1-7
Chapter 2 – LH75401 SoC
Figure 2-1. LH75401 Block Diagram..........................................................................2-2
Figure 2-2. LH75401 System Application Example....................................................2-3
Figure 2-3. LH75401 Pin Diagram..............................................................................2-4
Chapter 3 – LH75411 SoC
Figure 3-1. LH75411 Block Diagram..........................................................................3-2
Figure 3-2. LH75411 System Application Example....................................................3-3
Figure 3-3. LH75411 Pin Diagram..............................................................................3-4
Chapter 4 – LH75400 SoC
Figure 4-1. LH75400 Block Diagram..........................................................................4-2
Figure 4-2. LH75400 System Application Example....................................................4-3
Figure 4-3. LH75400 Pin Diagram..............................................................................4-4
Chapter 5 – LH75410 SoC
Figure 5-1. LH75410 Block Diagram..........................................................................5-2
Figure 5-2. LH75410 System Application Example....................................................5-3
Figure 5-3. LH75410 Pin Diagram..............................................................................5-4
Chapter 7 – Static Memory Controller
Figure 7-1. SMC Write Access...................................................................................7-3
Figure 7-2. SMC Write, nCSx De-asserted Early.......................................................7-5
Figure 7-3. SMC Read Access...................................................................................7-6
Figure 7-4. SMC Burst Read Access .........................................................................7-7
Figure 7-5. Typical Memory Connection Diagram....................................................7-11
Chapter 9 – Reset, Clock, and Power Controller
Figure 9-1. RCPC Block Diagram ..............................................................................9-1
Chapter 12 – Direct Memory Access Controller
Figure 12-1. Peripheral-to-Memory Data-Transfer Timing.......................................12-5
Figure 12-2. Memory-to-Peripheral Data-Transfer Timing.......................................12-6

List of Figures LH75400/01/10/11 (Preliminary) User’s Guide
xiv 6/17/03
Chapter 13 – Color Liquid Crystal Display Controller
Figure 13-1. Color LCD Controller Block Diagram (LH75401 and LH75411 Only)..13-2
Figure 13-2. STN Horizontal Timing Diagram........................................................13-31
Figure 13-3. STN Vertical Timing Diagram ............................................................13-32
Figure 13-4. TFT Horizontal Timing Diagram.........................................................13-33
Figure 13-5. TFT Vertical Timing Diagram.............................................................13-34
Figure 13-6. HR-TFT Horizontal Timing Diagram ..................................................13-35
Figure 13-7. HR-TFT Vertical Timing Diagram.......................................................13-35
Chapter 14 – Liquid Crystal Display Controller
Figure 14-1. LCD Controller Block Diagram (LH75400 and LH75410 Only)............14-2
Chapter 15 – Timers
Figure 15-1. Overall Timer Block Diagram...............................................................15-2
Figure 15-2. Timer 0 Block Diagram ........................................................................15-3
Figure 15-3. Timers 1 and 2 Block Diagram.............................................................15-4
Figure 15-4. Count Clock Timing (System Clock in Phase with CTCLK).................15-5
Figure 15-5. Count Clock Timing (System Clock not in Phase with CTCLK)...........15-5
Figure 15-6. Compare Match and Counter Clear.....................................................15-6
Figure 15-7. Capture Signal Synchronization Timing...............................................15-7
Figure 15-8. PWM Output Signal Timing..................................................................15-8
Chapter 16 – Watchdog Timer
Figure 16-1. Watchdog Timer Block Diagram..........................................................16-1
Chapter 17 – Real-Time Clock
Figure 17-1. RTC Block Diagram.............................................................................17-1
Chapter 18 – Synchronous Serial Port
Figure 18-1. Synchronous Serial Port Block Diagram..............................................18-2
Figure 18-2. SSP Timing Waveform.........................................................................18-4
Figure 18-3. Motorola SPI Frame Format (Single Transfer).....................................18-5
Figure 18-4. Motorola SPI Frame Format (Continuous Transfer) ............................18-5
Figure 18-5. Motorola SPI Frame Format with SPH = 0 ..........................................18-6
Figure 18-6. Motorola SPI Frame Format with SPH = 1 ..........................................18-6
Figure 18-7. Texas Instruments Synchronous Serial Frame Format
(Single Transfer)...................................................................................................18-7
Figure 18-8. Texas Instruments Synchronous Serial Frame Format
(Continuous Transfers).........................................................................................18-7
Figure 18-9. Microwire Frame Format (Single Transfer)..........................................18-9
Figure 18-10. Microwire Frame Format (Continuous Transfers)............................18-10
Chapter 19 – UART0 and UART1
Figure 19-1. UART0 and UART1 Block Diagram.....................................................19-1
Chapter 20 – UART2
Figure 20-1. UART2 Block Diagram.........................................................................20-1
Figure 20-2. Interrupt and Status Reporting Structure...........................................20-46
Chapter 21 – General Purpose Input/Output
Figure 21-1. GPIO Block Diagram............................................................................21-1

LH75400/01/10/11 (Preliminary) User’s Guide List of Figures
6/17/03 xv
Chapter 22 – Controller Area Network
Figure 22-1. CAN Controller Block Diagram ............................................................22-1
Figure 22-2. General Structure of a Bit Period.......................................................22-15
Chapter 23 – Analog-to-Digital Converter/Brownout Detector
Figure 23-1. ADC Block Diagram.............................................................................23-2
Figure 23-2. Bias-and-Control Network Block Diagram ...........................................23-4
Figure 23-3. Simplified N-bit SAR Architecture........................................................23-5
Figure 23-4. Example of a 4-bit SAR ADC Operation..............................................23-6
Figure 23-5. Bias-and-Control Network Block Diagram .........................................23-28
Chapter 25 – Recommended Layout Practices
Figure 25-1. ESD Filter Circuit Example ..................................................................25-1
Figure 25-1. VDD_PLL, VSSA_PLL Filter Circuit.....................................................25-2

6/17/03 xvii
List of Tables
Preface
Table 1. Register Name .......................................................................................... xxxiii
Table 2. Bit Definitions ............................................................................................ xxxiii
Chapter 1 – Introduction
Table 1-1. Feature Summary .....................................................................................1-1
Table 1-2. Bus Master Priority....................................................................................1-2
Table 1-3. Device Operating Modes...........................................................................1-3
Table 1-4. Linear Regulator Ramp-up Time...............................................................1-5
Chapter 2 – LH75401 SoC
Table 2-1. LH75401 Numerical Pin List......................................................................2-5
Table 2-2. LH75401 Signal Descriptions....................................................................2-9
Chapter 3 – LH75411 SoC
Table 3-1. LH75411 Numerical Pin List......................................................................3-5
Table 3-2. LH75411 Signal Descriptions....................................................................3-9
Chapter 4 – LH75400 SoC
Table 4-1. LH75400 Numerical Pin List......................................................................4-5
Table 4-2. LH75400 Signal Descriptions....................................................................4-9
Chapter 5 – LH75410 SoC
Table 5-1. LH75410 Numerical Pin List......................................................................5-5
Table 5-2. LH75410 Signal Descriptions....................................................................5-9
Chapter 6 – Memory Interface Architecture
Table 6-1. Memory Mapping ......................................................................................6-2
Table 6-2. External Memory Section Mapping...........................................................6-3
Table 6-3. Primary AHB Peripheral Register Mapping...............................................6-3
Table 6-4. APB Peripheral Register Mapping ............................................................6-4
Chapter 7 – Static Memory Controller
Table 7-1. Address Bus Organization ........................................................................7-1
Table 7-2. SMC Bus Turnaround Usage....................................................................7-8
Table 7-3. 8-bit External Bus Read............................................................................7-9
Table 7-4. 16-bit External Bus Read..........................................................................7-9
Table 7-5. 8-bit External Bus Write ..........................................................................7-10
Table 7-6. 16-bit External Bus Write ........................................................................7-10
Table 7-7. SMC Memory Bank Address Space........................................................7-12
Table 7-8. SMC Register Summary .........................................................................7-12
Table 7-9. BCR0 Register (16-bit Mode)..................................................................7-13
Table 7-10. BCR0 Register (8-bit Mode)..................................................................7-13
Table 7-11. BCR0 Register Definitions ....................................................................7-14
Table 7-12. BCR1 Register......................................................................................7-15
Table 7-13. BCR1 Register Definitions ....................................................................7-15
Table 7-14. BCR2 Register......................................................................................7-17

List of Tables LH75400/01/10/11 (Preliminary) User’s Guide
xviii 6/17/03
Table 7-15. BCR2 Register Definitions ....................................................................7-17
Table 7-16. BCR3 Register......................................................................................7-19
Table 7-17. BCR3 Register Definitions ....................................................................7-19
Table 7-18. SMC System Reset Default Memory Width..........................................7-21
Chapter 9 – Reset, Clock, and Power Controller
Table 9-1. Clock and Enable States for Different Power Modes................................9-4
Table 9-2. RCPC Register Summary.........................................................................9-6
Table 9-3. Ctrl Register..............................................................................................9-7
Table 9-4. Ctrl Register Definitions ............................................................................9-7
Table 9-5. ID Register................................................................................................9-8
Table 9-6. ID Register Definitions ..............................................................................9-8
Table 9-7. Remap Register........................................................................................9-8
Table 9-8. Remap Register Definitions ......................................................................9-8
Table 9-9. SoftReset Register....................................................................................9-9
Table 9-10. SoftReset Register Definitions................................................................9-9
Table 9-11. ResetStatus Register............................................................................9-10
Table 9-12. ResetStatus Register Definitions ..........................................................9-10
Table 9-13. ResetStatusClr Register........................................................................9-11
Table 9-14. ResetStatusClr Register Definitions......................................................9-11
Table 9-15. SysClk Prescaler Register ....................................................................9-12
Table 9-16. SysClk Prescaler Register Definitions...................................................9-12
Table 9-17. SysClkPrescaler Register Values .........................................................9-12
Table 9-18. APBPeriphClkCtrl0 Register .................................................................9-13
Table 9-19. APBPeriphClkCtrl0 Register Definitions................................................9-13
Table 9-20. APBPeriphClkCtrl1 Register .................................................................9-14
Table 9-21. APBPeriphClkCtrl1 Register Definitions................................................9-14
Table 9-22. AhbClkCtrl Register...............................................................................9-15
Table 9-23. AhbClkCtrl Register Definitions.............................................................9-15
Table 9-24. LCDPrescaler Register .........................................................................9-16
Table 9-25. LCDPrescaler Register Definitions........................................................9-16
Table 9-26. LCDPrescaler Register Values .............................................................9-16
Table 9-27. SSPPrescaler Register .........................................................................9-17
Table 9-28. SSPPrescaler Register Definitions........................................................9-17
Table 9-29. SSPPrescaler Register Values .............................................................9-17
Table 9-30. IntConfig Register .................................................................................9-18
Table 9-31. IntConfig Register Definitions................................................................9-18
Table 9-32. IntClear Register...................................................................................9-20
Table 9-33. IntClear Register Definitions .................................................................9-20
Chapter 10 – Vectored Interrupt Controller
Table 10-1. Interrupt Assignments...........................................................................10-2
Table 10-2. VIC Register Summary .........................................................................10-8
Table 10-3. IRQStatus Register...............................................................................10-9
Table 10-4. IRQStatus Register Definitions .............................................................10-9
Table 10-5. FIQStatus Register..............................................................................10-10
Table 10-6. FIQStatus Register Definitions............................................................10-10
Table 10-7. RawIntr Register .................................................................................10-11
Table 10-8. RawIntr Register Definitions................................................................10-11

LH75400/01/10/11 (Preliminary) User’s Guide List of Tables
6/17/03 xix
Table 10-9. IntSelect Register................................................................................10-12
Table 10-10. IntSelect Register Definitions............................................................10-12
Table 10-11. IntEnable Register.............................................................................10-13
Table 10-12. IntEnable Register Definitions...........................................................10-13
Table 10-13. IntEnClear Register...........................................................................10-14
Table 10-14. IntEnClear Register Definitions.........................................................10-14
Table 10-15. SoftInt Register .................................................................................10-15
Table 10-16. SoftInt Register Definitions................................................................10-15
Table 10-17. SoftIntClear Register.........................................................................10-16
Table 10-18. SoftIntClear.......................................................................................10-16
Table 10-19. VectAddr Register.............................................................................10-17
Table 10-20. VectAddr Register Definitions...........................................................10-17
Table 10-21. DefVectAddr Register .......................................................................10-18
Table 10-22. DefVectAddr Register Definitions......................................................10-18
Table 10-23. VectAddr Registers...........................................................................10-19
Table 10-24. VectAddr Register Definitions...........................................................10-19
Table 10-25. VectCtrl Registers.............................................................................10-20
Table 10-26. VectCtrl Register Definitions.............................................................10-20
Chapter 11 – I/O Configuration
Table 11-1. IOCON Register Summary....................................................................11-2
Table 11-2. EBI_MUX Register (16-bit Mode)..........................................................11-3
Table 11-3. EBI_MUX Register (8-bit Mode)............................................................11-3
Table 11-4. EBI_MUX Register Definitions..............................................................11-4
Table 11-5. PD_MUX Register.................................................................................11-5
Table 11-6. PD_MUX Register Definitions...............................................................11-5
Table 11-7. PE_MUX Register (LH75401 and LH75400) ........................................11-6
Table 11-8. PE_MUX Register (LH75410 and LH75411) ........................................11-6
Table 11-9. PE_MUX Register Definitions...............................................................11-7
Table 11-10. TIMER_MUX Register.........................................................................11-8
Table 11-11. TIMER_MUX Register Definitions.......................................................11-8
Table 11-12. LCD_MUX Register...........................................................................11-10
Table 11-13. LCD_MUX Register Definitions
(LH75401 and LH75411 SoC Devices)..............................................................11-10
Table 11-14. LCD_MUX Register Definitions
(LH75400 and LH75410 SoC Devices)..............................................................11-10
Table 11-15. PA_RES_MUX Register....................................................................11-11
Table 11-16. PA_RES_MUX Register Definitions..................................................11-11
Table 11-17. PB_RES_MUX Register....................................................................11-13
Table 11-18. PB_RES_MUX Register Definitions..................................................11-13
Table 11-19. PC_RES_MUX Register ...................................................................11-14
Table 11-20. PC_RES_MUX Register Definitions..................................................11-14
Table 11-21. PD_RES_MUX Register ...................................................................11-16
Table 11-22. PD_RES_MUX Register Definitions..................................................11-16
Table 11-23. PERES_MUX Register......................................................................11-18
Table 11-24. PE_RES_MUX Register Definitions..................................................11-18
Table 11-25. ADC_MUX Register..........................................................................11-20
Table 11-26. ADC_MUX Register..........................................................................11-20