Sharp Blue Treak LH75400 User manual

LH75400/01/10/11
System-on-Chip
Preliminary User’s Guide
7/15/03

Specifications are subject to change without notice.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on spe-
cial applications. See Limited Warranty for Sharp’s product warranty. The Limited Warranty is in lieu,
and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRAN-
TIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FIT-
NESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will Sharp
be liable, or inany way responsible, for any incidental or consequential economic or property damage.
BlueStreak is a trademark (pending) of SHARP Microelectronics of the Americas
ARM7TDMI-S is a trademark of Advanced RISC Machines, United Kingdom.
Motorola SPI is a trademark of Motorola, Inc.
National Semiconductor Microwire is a trademark of National Semiconductor Corporation
LH75400/01/10/11 System-on-Chip Preliminary User’s Guide
Produced by the SHARP Microelectronics of the Americas Technical Publication Group.
© 2003 Copyright SHARP Microelectronics of the Americas. Printed and Bound in USA.
Reference No. SMA02058

6/17/03 i
Table of Contents
Preface
Supplemental Documentation...............................................................................xxxi
Terms and Conventions........................................................................................xxxi
Multiplexed Pins ................................................................................................xxxi
Pin Names........................................................................................................xxxii
Peripheral Devices ........................................................................................... xxxii
Register Names................................................................................................xxxii
Register Addresses..........................................................................................xxxii
Register Tables ............................................................................................... xxxiii
Chapter 1 – Introduction
1.1 Product Overview.............................................................................................1-1
1.2 ARM and Thumb State.....................................................................................1-2
1.3 Bus Architecture...............................................................................................1-2
1.4 Operating Modes..............................................................................................1-3
1.4.1 Normal Mode.............................................................................................1-4
1.4.2 PLL Bypass Mode .....................................................................................1-4
1.4.3 Embedded ICE Mode................................................................................1-4
1.5 Power Supplies ................................................................................................1-4
1.5.1 Linear Regulator Power.........................................................................1-5
1.5.1.1 PLL Power..........................................................................................1-5
1.5.1.2 PCB Mounted Analog Power Supply Filter for PLL Usage.................1-5
1.5.2 Real-World Component Selection.........................................................1-6
1.6 Crystal Oscillator Usage...................................................................................1-7
1.7 Clocking Strategy.............................................................................................1-7
1.8 Reset Strategy..................................................................................................1-8
Chapter 2 – LH75401 SoC
2.1 LH75401 Features............................................................................................2-1
2.2 LH75401 Block Diagram ..................................................................................2-2
2.3 LH75401 Applications ......................................................................................2-3
2.4 LH75401 Pin Diagram......................................................................................2-4
2.5 LH75401 Numerical Pin Listing........................................................................2-5
2.6 LH75401 Signal Descriptions...........................................................................2-9
Chapter 3 – LH75411 SoC
3.1 LH75411 Features............................................................................................3-1
3.2 LH75411 Block Diagram ..................................................................................3-2
3.3 LH75411 Applications ......................................................................................3-3
3.4 LH75411 Pin Diagram......................................................................................3-4
3.5 LH75411 Numerical Pin Listing........................................................................3-5
3.6 LH75411 Signal Descriptions...........................................................................3-9

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Chapter 4 – LH75400 SoC
4.1 LH75400 Features............................................................................................4-1
4.2 LH75400 Block Diagram ..................................................................................4-2
4.3 LH75400 Applications ......................................................................................4-3
4.4 LH75400 Pin Diagram......................................................................................4-4
4.5 LH75400 Numerical Pin Listing........................................................................4-5
4.6 LH75400 Signal Descriptions...........................................................................4-9
Chapter 5 – LH75410 SoC
5.1 LH75410 Features............................................................................................5-1
5.2 LH75410 Block Diagram ..................................................................................5-2
5.3 LH75410 Applications ......................................................................................5-3
5.4 LH75410 Pin Diagram......................................................................................5-4
5.5 LH75410 Numerical Pin Listing........................................................................5-5
5.6 LH75410 Signal Descriptions...........................................................................5-9
Chapter 6 – Memory Interface Architecture
Chapter 7 – Static Memory Controller
7.1 SMC Features..................................................................................................7-1
7.2 SMC Theory of Operation ................................................................................7-2
7.2.1 SMC Write Process...................................................................................7-2
7.2.2 SMC Read Process...................................................................................7-4
7.2.3 SMC Burst Mode Read Process ...............................................................7-4
7.2.4 External Memory Bus Cycle......................................................................7-8
7.2.5 External Bus Read/Write Operations........................................................7-9
7.2.6 SMC Memory Connection Diagram.........................................................7-11
7.3 SMC Programmer’s Model.............................................................................7-12
7.3.1 SMC Register Summary..........................................................................7-12
7.3.2 SMC Register Definitions........................................................................7-13
7.3.2.1 Configuration Register for Memory Bank 0 ......................................7-13
7.3.2.2 Configuration Register for Memory Bank 1 ......................................7-15
7.3.2.3 Configuration Register for Memory Bank 2 ......................................7-17
7.3.2.4 Configuration Register for Memory Bank 3 ......................................7-19
7.3.3 SMC Default Memory Widths..................................................................7-21
Chapter 8 – Static Random Access Memory Controller
Chapter 9 – Reset, Clock, and Power Controller
9.1 RCPC Features................................................................................................9-2
9.2 RCPC Theory of Operation..............................................................................9-2
9.2.1 Reset Generation ......................................................................................9-3
9.2.2 Clock Generation.......................................................................................9-4
9.2.3 RCPC Power Modes .................................................................................9-4
9.2.3.1 Active Mode........................................................................................9-5
9.2.3.2 Standby Mode ....................................................................................9-5
9.2.3.3 Sleep Mode ........................................................................................9-5
9.2.3.4 Stop1 Mode........................................................................................9-5
9.2.3.5 Stop2 Mode........................................................................................9-5
9.3 RCPC Programmer’s Model.............................................................................9-6

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9.3.1 RCPC Register Summary .........................................................................9-6
9.3.2 RCPC Register Definitions........................................................................9-7
9.3.2.1 Control Register..................................................................................9-7
9.3.2.2 Identification Register.........................................................................9-8
9.3.2.3 Remap Control Register.....................................................................9-8
9.3.2.4 Soft Reset Register ............................................................................9-9
9.3.2.5 Reset Status Register.......................................................................9-10
9.3.2.6 Reset Status Clear Register.............................................................9-11
9.3.2.7 HCLK Prescaler Register .................................................................9-12
9.3.2.8 Peripheral Clock Control Register 0.................................................9-13
9.3.2.9 Peripheral Clock Control Register 1.................................................9-14
9.3.2.10 AHB Clock Control Register...........................................................9-15
9.3.2.11 LCD Clock Prescaler Register........................................................9-16
9.3.2.12 SSP Clock Prescaler Register........................................................9-17
9.3.2.13 External Interrupt Configuration Register.......................................9-18
9.3.2.14 External Interrupt Clear Register....................................................9-20
Chapter 10 – Vectored Interrupt Controller
10.1 Theory of Operation .....................................................................................10-1
10.1.1 Interrupts...............................................................................................10-1
10.1.2 VIC Interrupt Listing...............................................................................10-2
10.1.3 Vectored Interrupts................................................................................10-3
10.1.4 External Interrupts.................................................................................10-3
10.1.5 Clearing Interrupts.................................................................................10-4
10.1.6 Priority ...................................................................................................10-4
10.1.7 Sequencing ...........................................................................................10-5
10.1.8 External Level-Sensitive Interrupts........................................................10-7
10.1.9 Software Guidelines ..............................................................................10-7
10.2 VIC Programmer’s Model.............................................................................10-7
10.2.1 VIC Register Summary..........................................................................10-8
10.2.2 VIC Register Definitions ........................................................................10-9
10.2.2.1 IRQ Status Register........................................................................10-9
10.2.2.2 FIQ Status Register......................................................................10-10
10.2.2.3 Raw Interrupt Status Register ......................................................10-11
10.2.2.4 Interrupt Select Register...............................................................10-12
10.2.2.5 Interrupt Enable Register..............................................................10-13
10.2.2.6 Interrupt Enable Clear Register....................................................10-14
10.2.2.7 Software Interrupt Register...........................................................10-15
10.2.2.8 Software Interrupt Clear Register.................................................10-16
10.2.2.9 Vector Address Register...............................................................10-17
10.2.2.10 Default Vector Address Register................................................10-18
10.2.2.11 Vector Address Registers...........................................................10-19
10.2.2.12 Vector Control Registers ............................................................10-20

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Chapter 11 – I/O Configuration
11.1 IOCON Theory of Operation.........................................................................11-1
11.2 IOCON Programmer’s Model.......................................................................11-2
11.2.1 IOCON Register Summary....................................................................11-2
11.2.2 IOCON Register Definitions ..................................................................11-3
11.2.2.1 EBI Interface Muxing Register........................................................11-3
11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register................................11-5
11.2.2.3 Pins PE7/SSPRM to PD0/INT0 Muxing Register...........................11-6
11.2.2.4 Timer Muxing Register ...................................................................11-8
11.2.2.5 LCD Mode Muxing Register .........................................................11-10
11.2.2.6 Pins PA7/D15 to PA0/D8 Resistor Muxing Register.....................11-11
11.2.2.7 Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register............11-13
11.2.2.8 Pins PC7/A23 to PC0/A16 Resistor Muxing Register...................11-14
11.2.2.9 Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register................11-16
11.2.2.10 Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register 11-18
11.2.2.11 Pins AN7/PJ7 to AN0/PJ0..........................................................11-20
Chapter 12 – Direct Memory Access Controller
12.1 DMA Controller Features..............................................................................12-1
12.2 DMA Theory Of Operation............................................................................12-2
12.2.1 Interrupt, Error, and Status Registers....................................................12-4
12.2.2 DMA Controller Timing Diagrams..........................................................12-4
12.3 DMA Programmer’s Model...........................................................................12-7
12.3.1 DMA Controller Register Summary.......................................................12-7
12.3.2 DMA Controller Register Definitions......................................................12-8
12.3.2.1 Source Base Registers...................................................................12-8
12.3.2.2 Destination Base Register..............................................................12-8
12.3.2.3 Maximum Count Register...............................................................12-8
12.3.2.4 Control Register..............................................................................12-9
12.3.2.5 Current Source Registers.............................................................12-11
12.3.2.6 Current Destination Registers ......................................................12-11
12.3.2.7 Terminal Count Register...............................................................12-11
12.3.2.8 Interrupt Mask Register................................................................12-12
12.3.2.9 Interrupt Clear Register................................................................12-13
12.3.2.10 Status Register...........................................................................12-14
Chapter 13 – Color Liquid Crystal Display Controller
13.1 CLCDC Features..........................................................................................13-3
13.2 CLCDC Theory of Operation........................................................................13-4
13.2.1 LCD DMA FIFOs ...................................................................................13-4
13.2.2 Pixel Serializer.......................................................................................13-4
13.2.3 How Pixels are Stored in Memory.........................................................13-5
13.2.4 Palette RAM ..........................................................................................13-6
13.2.5 Grayscale Algorithm..............................................................................13-7
13.2.6 LCD Panel Resolutions.........................................................................13-7
13.3 CLCDC Programmer’s Model.....................................................................13-10
13.3.1 CLCDC Register Summary .................................................................13-10
13.3.2 CLCDC Register Definitions................................................................13-11

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13.3.2.1 Horizontal Timing Panel Control Register ....................................13-11
13.3.2.2 Horizontal Timing Restrictions......................................................13-12
13.3.2.3 Vertical Timing Panel Control Register.........................................13-13
13.3.2.4 Clock and Signal Polarity Control Register...................................13-14
13.3.2.5 Upper Panel Frame Buffer Base Address Register......................13-15
13.3.2.6 Lower Panel Frame Buffer Base Address Register......................13-16
13.3.2.7 Interrupt Enable Register..............................................................13-17
13.3.2.8 LCD Panel Parameters, LCD Panel Power, and
CLCDC Control Register........................................................................13-18
13.3.2.9 Raw Interrupt Status Register ......................................................13-20
13.3.2.10 Final Masked Interrupts Register................................................13-21
13.3.2.11 LCD Upper Panel Frame Buffer Current Address Register........13-22
13.3.2.12 256 × 16-bit Color Palette Register............................................13-23
13.3.3 CLCDC Interrupts................................................................................13-24
13.4 HR-TFT Controller......................................................................................13-24
13.4.1 HRTFTC Operating Modes .................................................................13-24
13.4.1.1 Bypass Mode................................................................................13-24
13.4.1.2 HR-TFT Mode...............................................................................13-24
13.4.2 HRTFTC Theory of Operation.............................................................13-25
13.4.3 HRTFTC Programmer’s Model............................................................13-25
13.4.4 HRTFTC Register Summary ...............................................................13-25
13.4.5 HRTFTC Register Definitions..............................................................13-26
13.4.5.1 Setup Register..............................................................................13-26
13.4.5.2 Control Register............................................................................13-27
13.4.5.3 Timing1 Register ..........................................................................13-28
13.4.5.4 Timing2 Register ..........................................................................13-29
13.5 Timing Waveforms .....................................................................................13-30
13.5.1 STN Horizontal Timing ........................................................................13-30
13.5.2 STN Vertical Timing ............................................................................13-30
13.5.3 TFT Horizontal Timing.........................................................................13-30
13.5.4 TFT Vertical Timing.............................................................................13-30
13.5.5 HR-TFT Horizontal Timing Waveforms ...............................................13-30
13.5.6 HR-TFT Vertical Timing Waveforms....................................................13-30
Chapter 14 – Liquid Crystal Display Controller
14.1 LCDC Features ............................................................................................14-3
14.2 LCDC Theory of Operation...........................................................................14-3
14.2.1 LCD DMA FIFOs ...................................................................................14-4
14.2.2 Pixel Serializer.......................................................................................14-4
14.2.3 How Pixels are Stored in Memory.........................................................14-4
14.2.4 Palette RAM ..........................................................................................14-5
14.2.5 Grayscale Algorithm..............................................................................14-5
14.2.6 Supported Grayscale.............................................................................14-6
14.3 LCDC Programmer’s Model.........................................................................14-7
14.3.1 LCDC Register Summary......................................................................14-7
14.3.2 LCDC Register Definitions ....................................................................14-8
14.3.2.1 Horizontal Timing Panel Control Register ......................................14-8
14.3.2.2 Horizontal Timing Restrictions........................................................14-9

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14.3.2.3 Vertical Timing Panel Control Register.........................................14-10
14.3.2.4 Clock and Signal Polarity Control Register...................................14-11
14.3.2.5 Upper Panel Frame Buffer Base Address Register......................14-12
14.3.2.6 Lower Panel Frame Buffer Base Address Register......................14-13
14.3.2.7 Interrupt Enable Register..............................................................14-14
14.3.2.8 LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register...........................................................................14-15
14.3.2.9 Raw Interrupt Status Register ......................................................14-17
14.3.2.10 Final Masked Interrupts Register................................................14-18
14.3.2.11 LCD Upper Panel Frame Buffer Current Address Register........14-19
14.3.2.12 LCD Palette Register..................................................................14-20
14.3.3 LCDC Interrupts ..................................................................................14-20
Chapter 15 – Timers
15.1 Timer Theory of Operation...........................................................................15-5
15.1.1 Count Timing.........................................................................................15-5
15.1.2 Counter Clear Upon Compare Match....................................................15-6
15.1.3 Capture Signal Sampling.......................................................................15-7
15.1.4 PWM Mode............................................................................................15-7
15.2 Timer Programmer’s Model..........................................................................15-9
15.2.1 Timer Register Summary ......................................................................15-9
15.2.2 Timer Register Definitions...................................................................15-10
15.2.2.1 Timer 0 Control Register ..............................................................15-10
15.2.2.2 Timer 0 Compare/Capture Control Register................................15-11
15.2.2.3 Timer 0 Interrupt Control Register................................................15-13
15.2.2.4 Timer 0 Status Register................................................................15-14
15.2.2.5 Timer 0 Counter Register.............................................................15-15
15.2.2.6 Timer 0 Compare Registers .........................................................15-16
15.2.2.7 Timer 0 Capture Registers ...........................................................15-17
15.2.2.8 Timer 1 Control Register ..............................................................15-18
15.2.2.9 Timer 1 Interrupt Control Register................................................15-20
15.2.2.10 Timer 1 Status Register..............................................................15-21
15.2.2.11 Timer 1 Counter Register...........................................................15-22
15.2.2.12 Timer 1 Compare Registers .......................................................15-23
15.2.2.13 Timer 1 Capture Registers .........................................................15-24
15.2.2.14 Timer 2 Control Register ............................................................15-25
15.2.2.15 Timer 2 Interrupt Control Register..............................................15-27
15.2.2.16 Timer 2 Status Register..............................................................15-28
15.2.2.17 Timer 2 Counter Register...........................................................15-29
15.2.2.18 Timer 2 Compare Registers .......................................................15-30
15.2.2.19 Timer 2 Capture Registers .........................................................15-31
15.2.2.20 Timer Interrupts..........................................................................15-32

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Chapter 16 – Watchdog Timer
16.1 WDT Features..............................................................................................16-1
16.2 WDT Theory of Operation............................................................................16-2
16.3 WDT Programmer’s Model...........................................................................16-2
16.3.0.1 WDT Register Summary.................................................................16-2
16.3.1 WDT Register Definitions......................................................................16-3
16.3.1.1 Control Register..............................................................................16-3
16.3.1.2 Counter Reset Register..................................................................16-4
16.3.1.3 Status Register...............................................................................16-5
16.3.1.4 Counter Section 0 Register ............................................................16-6
16.3.1.5 Counter Section 1 Register ............................................................16-6
16.3.1.6 Counter Section 2 Register ............................................................16-7
16.3.1.7 Counter Section 3 Register ............................................................16-7
Chapter 17 – Real-Time Clock
17.1 RTC Features...............................................................................................17-1
17.2 RTC Theory of Operation.............................................................................17-2
17.3 RTC Programmer’s Model............................................................................17-3
17.3.1 RTC Register Summary ........................................................................17-3
17.3.2 RTC Register Definitions.......................................................................17-4
17.3.2.1 Data Register 0...............................................................................17-4
17.3.2.2 Data Register 1...............................................................................17-5
17.3.2.3 Match Register 0 ............................................................................17-6
17.3.2.4 Match Register 1 ............................................................................17-6
17.3.2.5 Interrupt Status/Clear .....................................................................17-7
17.3.2.6 Read/Write Load Register 0...........................................................17-8
17.3.2.7 Read/Write Load Register 1...........................................................17-9
17.3.2.8 Control Register............................................................................17-10
17.3.3 RTC Interrupts.....................................................................................17-10
Chapter 18 – Synchronous Serial Port
18.1 SSP Features...............................................................................................18-1
18.2 SSP Theory Of Operation ............................................................................18-3
18.3 SSP Timing Waveforms...............................................................................18-4
18.3.1 Motorola SPI Frame Format..................................................................18-5
18.3.2 Texas Instruments Frame Format.........................................................18-7
18.3.3 National Semiconductor Frame Format ................................................18-8
18.4 Clock Generation..........................................................................................18-8
18.5 SSP Programmer’s Model..........................................................................18-11
18.5.1 SSP Register Summary ......................................................................18-11
18.5.2 SSP Register Definitions.....................................................................18-12
18.5.2.1 Control Register 0.........................................................................18-12
18.5.2.2 Control Register 1.........................................................................18-13
18.5.2.3 Receive / Transmit FIFO Register................................................18-14
18.5.2.4 Status Register.............................................................................18-15
18.5.2.5 Clock Prescale Register...............................................................18-16
18.5.2.6 Interrupt Identification/Clear Register...........................................18-17
18.5.2.7 Receive Timeout Register............................................................18-18

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18.5.3 SSP Interrupts.....................................................................................18-19
18.5.3.1 Receive Interrupt..........................................................................18-19
18.5.3.2 Transmit Interrupt.........................................................................18-19
18.5.3.3 Receive Overrun Interrupt............................................................18-19
18.5.3.4 Receive Timeout Interrupt............................................................18-20
18.5.3.5 SSPINTR......................................................................................18-20
Chapter 19 – UART0 and UART1
19.1 UART0 and UART1 Features.......................................................................19-2
19.2 UART0 and UART1 Theory of Operation.....................................................19-2
19.2.1 UART0 and UART1 Receiver Data Frame............................................19-2
19.2.2 Status Conditions ..................................................................................19-3
19.2.3 On-Chip DMA Capabilities ....................................................................19-4
19.2.4 Programming Control Registers............................................................19-4
19.3 UART0 and UART1 Programmer’s Model ...................................................19-5
19.3.0.1 UART0 and UART1 Register Summary ........................................19-5
19.3.1 UART0 and UART1 Register Definitions...............................................19-6
19.3.1.1 Data Register..................................................................................19-6
19.3.1.2 Receive Status/Error Clear Register..............................................19-8
19.3.1.3 Flag Register................................................................................19-10
19.3.1.4 UART Line Control Register.........................................................19-11
19.3.1.5 Integer Baud Rate Divisor Register..............................................19-12
19.3.1.6 Fractional Baud Rate Divisor Register .........................................19-13
19.3.1.7 Calculating the Divisor Value........................................................19-14
19.3.1.8 Typical Bit Rates and Their Corresponding Divisor......................19-14
19.3.1.9 Line Control Register....................................................................19-15
19.3.1.10 UART Control Register...............................................................19-17
19.3.1.11 Interrupt FIFO Level Select Register..........................................19-18
19.3.1.12 Interrupt Mask Set/Clear Register..............................................19-19
19.3.1.13 Raw Interrupt Status Register ....................................................19-21
19.3.1.14 Masked Interrupt Status Register...............................................19-22
19.3.1.15 ICR .............................................................................................19-23
19.3.1.16 DMACTRL..................................................................................19-24
19.3.2 UART0 and UART1 Interrupts.............................................................19-25
19.3.2.1 UARTRXINTR ..............................................................................19-25
19.3.2.2 UARTTXINTR...............................................................................19-25
19.3.2.3 UARTINTR ...................................................................................19-25
Chapter 20 – UART2
20.1 UART2 Features ..........................................................................................20-2
20.2 UART2 Theory of Operation.........................................................................20-2
20.2.1 UART Receiver Data Frame .................................................................20-3
20.2.2 Status Conditions ..................................................................................20-5
20.2.3 Disabling the Loading of Incoming Characters......................................20-5
20.2.4 Baud Rate Generators ..........................................................................20-6
20.3 UART2 Programmer’s Model.......................................................................20-7
20.3.1 UART2 Register Summary....................................................................20-7
20.3.1.1 Register Bank 0..............................................................................20-7