Sharp LH79524 User manual

LH79524/LH79525
User’s Guide
Version 1.0

Specifications are subject to change without notice.
Suggestedapplications(ifany)areforstandard use;SeeImportantRestrictions for limitationsonspecial
applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and
exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES,
INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR
A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in
any way responsible, for any incidental or consequential economic or property damage.
Purchase of I2C components from SHARP Corporation or one of its sublicensed Associated
Companies conveys a license under the Philips I2C Patent. Rights are granted to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips.
LH79524/LH79525 SoC User’s Guide
Produced by the SHARP Microelectronics of the Americas MarCom Group.
© 2004-2007 Copyright SHARP Microelectronics of the Americas.
Reference No. SMA04007

Version 1.0 i
Table of Contents
Preface
Conventions and Terms......................................................................................xxxv
Unconnected (Floating) Inputs........................................................................xxxv
Multiplexed Pins ..............................................................................................xxxv
Pin Names......................................................................................................xxxvi
Peripheral Devices ......................................................................................... xxxvi
Register Addresses........................................................................................xxxvi
Register Tables ............................................................................................. xxxvii
Numeric Values.............................................................................................xxxviii
Block Diagrams .............................................................................................xxxviii
What’s in This User’s Guide......................................................................................xl
Chapter 1 – Overview............................................................................................xl
Chapter 2 – ADC and Brownout Detector.............................................................xl
Chapter 3 – Boot Controller...................................................................................xl
Chapter 4 – Color LCD Controller .........................................................................xl
Chapter 5 – DMA Controller..................................................................................xl
Chapter 6 – Ethernet MAC....................................................................................xl
Chapter 7 – External Memory Controller..............................................................xli
Chapter 8 – General Purpose Input/Output..........................................................xli
Chapter 9 – I2C Interface.....................................................................................xli
Chapter 10 – I2S Converter .................................................................................xli
Chapter 11 – I/O Configuration ............................................................................xli
Chapter 12 – Real Time Clock .............................................................................xli
Chapter 13 – Reset, Clock Generation and Power Control..................................xli
Chapter 14 – Synchronous Serial Port.................................................................xli
Chapter 15 – Timers............................................................................................xlii
Chapter 16 – UARTs...........................................................................................xlii
Chapter 17 – USB Device ...................................................................................xlii
Chapter 18 – Vectored Interrupt Controller .........................................................xlii
Chapter 19 – Watchdog Timer............................................................................xlii
Appendix – Glossary ...........................................................................................xlii
Chapter 1 – Overview
1.1 Bus Architecture...............................................................................................1-3
1.2 Power Supply...................................................................................................1-3
1.2.1 Linear Regulator........................................................................................1-3
1.2.2 Phase Locked Loop Power .......................................................................1-3
1.3 Clock Strategy..................................................................................................1-4
1.3.1 Bus Clocking Modes..................................................................................1-6
1.3.1.1 Standard Bus Clocking Modes...........................................................1-6
1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes......................1-7
1.3.1.3 Fastbus Extension Bus Clocking Mode..............................................1-7
1.4 Reset Strategy..................................................................................................1-8
1.4.1 Resetting the Test Access Port Controller ................................................1-9

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1.4.2 Hardware Requirements at Reset...........................................................1-10
1.4.2.1 Floating Inputs..................................................................................1-10
1.4.2.2 Test Pins...........................................................................................1-10
1.4.2.3 Active Pull Ups .................................................................................1-11
1.5 AHB Bus Master Priority and Arbitration........................................................1-12
1.6 Memory Interface Architecture.......................................................................1-12
1.7 Instruction and Data Cache............................................................................1-17
1.8 Memory Management Unit (MMU).................................................................1-17
Chapter 2 – Analog-to-Digital Converter/Brownout Detector
2.1 Theory of Operation .........................................................................................2-1
2.1.1 Operational Summary ...............................................................................2-1
2.1.2 Bias-and-Control Network.........................................................................2-3
2.1.3 Clock Generator........................................................................................2-5
2.1.4 Brownout Detector.....................................................................................2-5
2.1.5 SAR Architecture.......................................................................................2-5
2.1.6 Battery Control Feature.............................................................................2-7
2.1.7 Timing Formulas........................................................................................2-8
2.1.8 Interrupts...................................................................................................2-8
2.1.8.1 Brownout Interrupt..............................................................................2-8
2.1.8.2 Pen Interrupt.......................................................................................2-9
2.1.8.3 End-of-Sequence Interrupt.................................................................2-9
2.1.8.4 FIFO Watermark Interrupt ..................................................................2-9
2.1.8.5 FIFO Overrun Interrupt.......................................................................2-9
2.1.9 Application Details.....................................................................................2-9
2.2 Register Reference ........................................................................................2-10
2.2.1 Memory Map ...........................................................................................2-10
2.2.2 Register Descriptions ..............................................................................2-11
2.2.2.1 High Word Register (HW).................................................................2-11
2.2.2.2 Low Word Register (LW)..................................................................2-13
2.2.2.3 Results Register (RR).......................................................................2-14
2.2.2.4 Interrupt Mask Register (IM).............................................................2-15
2.2.2.5 Power Configuration Register (PC)..................................................2-16
2.2.2.6 General Configuration Register (GC)...............................................2-18
2.2.2.7 General Status Register (GS)...........................................................2-19
2.2.2.8 Interrupt Status Register (IS)............................................................2-20
2.2.2.9 FIFO Status Register (FS)................................................................2-21
2.2.2.10 Control Bank Registers...................................................................2-22
2.2.2.11 Idle High Word Register (IHWCTRL)..............................................2-23
2.2.2.12 Idle Low Word Register (ILWCTRL)...............................................2-24
2.2.2.13 Masked Interrupt Status Register (MIS).........................................2-25
2.2.2.14 Interrupt Clear Register (IC)...........................................................2-26

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Version 1.0 iii
Chapter 3 – Boot Controller
3.1 Theory of Operation .........................................................................................3-2
3.1.1 Boot Device Determination........................................................................3-2
3.1.1.1 NAND Flash Operation.......................................................................3-4
3.1.2 Hardware Design Considerations..............................................................3-4
3.1.2.1 Active Pullups To Signal Boot Mode ..................................................3-4
3.1.2.2 NAND Flash Hardware Design...........................................................3-5
3.1.3 Booting Using the I2C Interface ................................................................3-6
3.1.4 Booting from UART ...................................................................................3-7
3.2 Register Reference ..........................................................................................3-7
3.2.1 Memory Map .............................................................................................3-7
3.2.2 Register Definitions ...................................................................................3-8
3.2.2.1 Power-up Boot Configuration Register (PBC)....................................3-8
3.2.3 nCS1 Override Register (CS1OV).............................................................3-9
3.2.4 External Peripheral Mapping Register (EPM) .........................................3-10
Chapter 4 – Color Liquid Crystal Display Controller
4.1 Introduction.......................................................................................................4-1
4.1.1 LCD Panel Architecture.............................................................................4-2
4.2 CLCDC Features..............................................................................................4-3
4.3 Theory of Operation .........................................................................................4-3
4.3.1 Supported Displays and Panels ................................................................4-5
4.3.2 Frame Buffer .............................................................................................4-5
4.3.3 LCD DMA FIFOs .......................................................................................4-5
4.3.4 Pixel Serializer...........................................................................................4-6
4.3.5 How Pixels are Stored in Memory.............................................................4-6
4.3.6 Palette RAM ..............................................................................................4-8
4.3.6.1 Grayscale Algorithm...........................................................................4-9
4.3.6.2 Interrupts ............................................................................................4-9
4.3.6.3 LCD Panel Resolutions ......................................................................4-9
4.3.7 LCD Data Multiplexing.............................................................................4-12
4.3.8 LCD Interface Timing Signals..................................................................4-13
4.3.8.1 LCD Horizontal Timing Signals.........................................................4-13
4.3.8.2 LCD Vertical Timing Signals.............................................................4-14
4.3.9 LCD Power Sequencing at Turn-On and Turn-Off..................................4-15
4.3.9.1 Minimizing a Retained Image on the LCD........................................4-16
4.3.10 Interrupts...............................................................................................4-16
4.4 Advanced LCD Interface................................................................................4-17
4.4.1 ALI Theory of Operation..........................................................................4-18
4.4.2 ALI Operating Modes ..............................................................................4-18
4.4.2.1 Bypass Mode....................................................................................4-18
4.4.2.2 Active Mode......................................................................................4-18
4.5 CLCDC Register Reference...........................................................................4-19
4.5.1 Enabling the CLCDC...............................................................................4-19
4.5.2 CLCDC Memory Map..............................................................................4-19
4.5.3 CLCDC Register Descriptions.................................................................4-20
4.5.3.1 Horizontal Timing Panel Control Register (TIMING0) ......................4-20
4.5.3.2 Vertical Timing Panel Control Register (TIMING1)...........................4-22

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4.5.3.3 Clock and Signal Polarity Control Register (TIMING2).....................4-24
4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE)........4-26
4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) ........4-27
4.5.3.6 Interrupt Enable Register (INTREN).................................................4-28
4.5.3.7 CLCDC Control Register (CTRL) .....................................................4-29
4.5.3.8 Raw Interrupt Status Register (STATUS).........................................4-32
4.5.3.9 Masked Interrupt Status Register (INTERRUPT).............................4-33
4.5.3.10 Interrupt Clear Register (INTCLR)..................................................4-34
4.5.3.11 LCD Upper Panel and Lower Panel Frame Buffer Current
Address Register (UPCURR and LPCURR) ............................................4-35
4.5.3.12 256 × 16-bit Color Palette Register (PALETTE).............................4-36
4.5.4 ALI Register Reference...........................................................................4-38
4.5.5 ALI Memory Map.....................................................................................4-38
4.5.6 ALI Register Descriptions........................................................................4-38
4.5.6.1 Setup Register (ALISETUP).............................................................4-38
4.5.6.2 Control Register (ALICTRL) .............................................................4-39
4.5.6.3 Timing Delay Register 1 (ALITIMING1)............................................4-40
4.5.6.4 Timing Delay Register 2 (ALITIMING2)............................................4-41
4.6 Timing Waveforms .........................................................................................4-42
4.6.1 STN Horizontal Timing ............................................................................4-42
4.6.2 STN Vertical Timing ................................................................................4-42
4.6.3 TFT Horizontal Timing.............................................................................4-42
4.6.4 TFT Vertical Timing.................................................................................4-42
4.6.5 AD-TFT/HR-TFT Horizontal Timing Waveforms......................................4-42
4.6.6 AD-TFT/HR-TFT Vertical Timing Waveforms..........................................4-42
Chapter 5 – Direct Memory Access Controller
5.1 Theory Of Operation.........................................................................................5-2
5.1.1 Use for SSP and UART.............................................................................5-3
5.1.2 Changing Mode from Memory to Peripheral .............................................5-3
5.1.3 Interrupt, Error, and Status Registers........................................................5-4
5.1.3.1 Interrupts ............................................................................................5-4
5.1.4 External DMA Handshake Signal Timing ..................................................5-4
5.2 Register Reference ..........................................................................................5-5
5.2.1 Memory Map .............................................................................................5-5
5.2.2 Register Definitions ...................................................................................5-6
5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI)....................5-6
5.2.2.2 Destination Base Registers (DESTLO and DESTHI).........................5-7
5.2.2.3 Maximum Count Register (MAX)........................................................5-8
5.2.2.4 Control Register (CTRL).....................................................................5-9
5.2.2.5 Current Source Registers (CURSHI and CURSLO).........................5-12
5.2.2.6 Current Destination Registers (CURDHI and CURDLO)..................5-13
5.2.2.7 Terminal Count Register (TCNT)......................................................5-14
5.2.2.8 Interrupt Mask Register (MASK).......................................................5-15
5.2.2.9 Interrupt Clear Register (CLR)..........................................................5-16
5.2.2.10 Status Register (STATUS) .............................................................5-17

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Chapter 6 – Ethernet MAC Controller
6.1 Theory of Operation .........................................................................................6-2
6.1.1 Operational Overview................................................................................6-3
6.1.1.1 Setup..................................................................................................6-4
6.1.1.2 Statistics.............................................................................................6-4
6.1.1.3 Detailed Descriptions..........................................................................6-4
6.1.2 Memory Interface ......................................................................................6-4
6.1.2.1 FIFO ...................................................................................................6-4
6.1.2.2 Receive Buffers..................................................................................6-4
6.1.2.3 Transmit Buffer...................................................................................6-7
6.1.3 Receive Block............................................................................................6-9
6.1.4 Transmit Block...........................................................................................6-9
6.1.4.1 Pause Frame Support ......................................................................6-10
6.1.5 Address Checking Block .........................................................................6-11
6.1.5.1 Broadcast Address...........................................................................6-12
6.1.5.2 Hash Addressing..............................................................................6-12
6.1.5.3 Copy All Frames (Promiscuous Mode).............................................6-12
6.1.5.4 Type ID Checking.............................................................................6-13
6.1.5.5 VLAN Support...................................................................................6-13
6.2 Programming Model.......................................................................................6-13
6.2.1 Initialization..............................................................................................6-14
6.2.1.1 Receive Buffer List ...........................................................................6-14
6.2.1.2 Transmit Buffer List ..........................................................................6-16
6.2.1.3 Transmitting Frames.........................................................................6-16
6.2.1.4 Local Loop Back Mode.....................................................................6-16
6.2.1.5 PHY Maintenance.............................................................................6-17
6.2.1.6 Interrupts ..........................................................................................6-17
6.3 Register Reference ........................................................................................6-18
6.3.1 Memory Map ...........................................................................................6-18
6.3.2 Control, Configuration, And Status Register Definitions..........................6-20
6.3.2.1 Network Control Register (NETCTL)................................................6-20
6.3.2.2 Network Configuration Register (NETCONFIG)...............................6-22
6.3.2.3 Network Status Register (NETSTATUS)..........................................6-24
6.3.2.4 Transmit Status Register (TXSTATUS)............................................6-25
6.3.2.5 Receive Buffer Queue Pointer (RXBQP)..........................................6-27
6.3.2.6 Transmit Buffer Queue Pointer (TXBQP).........................................6-28
6.3.2.7 Receive Status Register (RXSTATUS) ............................................6-29
6.3.2.8 Interrupt Status Register (INSTATUS) .............................................6-30
6.3.2.9 Interrupt Enable Register (ENABLE)................................................6-32
6.3.2.10 Interrupt Disable Register (DISABLE)............................................6-33
6.3.2.11 Interrupt Mask Register (MASK).....................................................6-34
6.3.2.12 PHY Maintenance Register (PHYMAINT)......................................6-35
6.3.2.13 Pause Time Register (PAUSETIME)..............................................6-36
6.3.2.14 Transmit Pause Quantum (TXPAUSEQUAN)................................6-36
6.3.3 Statistics Register Definitions..................................................................6-37
6.3.3.1 Pause Frames Received (PAUSEFRRX).........................................6-37
6.3.3.2 Frames Transmitted OK (FRMTXOK)..............................................6-38

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6.3.3.3 Single Collision Frames (SINGLECOL)............................................6-38
6.3.3.4 Multiple Collision Frames (MULTFRM) ............................................6-39
6.3.3.5 Frames Received OK (FRMRXOK)..................................................6-39
6.3.3.6 Frame Check Sequence Errors (FRCHK)........................................6-40
6.3.3.7 Alignment Errors (ALIGNERR).........................................................6-40
6.3.3.8 Deferred Transmission Frames (DEFTXFRM).................................6-41
6.3.3.9 Late Collisions (LATECOL) ..............................................................6-41
6.3.3.10 Excessive Collisions (EXCOL) .......................................................6-42
6.3.3.11 Transmit Underrun Errors (TXUNDER)..........................................6-42
6.3.3.12 Carrier Sense Errors (SENSERR)..................................................6-43
6.3.3.13 Receive Resource Errors (RXRERR).............................................6-44
6.3.3.14 Receive Overrun Errors (RXOVERR).............................................6-44
6.3.3.15 Receive Symbol Errors (RXSYMERR)...........................................6-45
6.3.3.16 Excessive Length Error Register (LENERR)..................................6-45
6.3.3.17 Receive Jabbers (RXJAB)..............................................................6-46
6.3.3.18 Undersize Frames (UNDERFRM)..................................................6-46
6.3.3.19 SQE Test Errors (SQERR).............................................................6-47
6.3.3.20 Received Length Field Mismatch (RXLEN)....................................6-47
6.3.3.21 Transmitted Pause Frames (TXPAUSEFM)...................................6-48
6.3.4 Matching Registers..................................................................................6-49
6.3.4.1 Hash Register Bottom (HASHBOT)..................................................6-49
6.3.4.2 Hash Register Top (HASHTOP).......................................................6-49
6.3.4.3 Specific Address 1 Bottom (SPECAD1BOT)....................................6-50
6.3.4.4 Specific Address 1 Top (SPECAD1TOP).........................................6-50
6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT)....................................6-51
6.3.4.6 Specific Address 2 Top (SPECAD2TOP).........................................6-51
6.3.4.7 Specific Address 3 Bottom (SPECAD3BOT)....................................6-52
6.3.4.8 Specific Address 3 Top (SPECAD3TOP).........................................6-52
6.3.4.9 Specific Address 4 Bottom (SPECAD4BOT)....................................6-53
6.3.4.10 Specific Address 4 Top (SPECAD4TOP).......................................6-53
6.3.4.11 Type ID Checking (IDCHK) ............................................................6-54
Chapter 7 – External Memory Controller
7.1 Theory of Operation .........................................................................................7-1
7.1.1 External Memory Map ...............................................................................7-3
7.1.1.1 nCS1 Memory Configuration..............................................................7-3
7.2 Static Memory ..................................................................................................7-3
7.2.1 Static Memory Operation...........................................................................7-3
7.2.2 Hardware Design.......................................................................................7-5
7.2.2.1 Address Connectivity..........................................................................7-5
7.2.3 Software Design........................................................................................7-9
7.2.3.1 Simple Shifting Subroutine.................................................................7-9
7.2.4 Static Memory Device Selection..............................................................7-10
7.2.4.1 Static Memory Timing Control..........................................................7-10
7.2.4.2 Bus Turnaround................................................................................7-16
7.2.4.3 Byte Lane Control.............................................................................7-16
7.2.4.4 Write Protection................................................................................7-16
7.2.4.5 nWAIT Transfers ..............................................................................7-16

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7.2.4.6 Extended Wait Transfers..................................................................7-17
7.3 Interfacing with NAND Flash..........................................................................7-17
7.3.1 Booting Example .....................................................................................7-17
7.3.2 General NAND Flash Access..................................................................7-20
7.3.2.1 Transaction Example........................................................................7-20
7.3.2.2 16-bit Example Transaction..............................................................7-21
7.3.2.3 Address Examples............................................................................7-21
7.4 Dynamic Memory ...........................................................................................7-22
7.4.1 Write-protection.......................................................................................7-22
7.4.2 Access Sequencing and Memory Width..................................................7-22
7.4.3 Bus Address Mapping .............................................................................7-22
7.4.4 Data Mask Signals ..................................................................................7-27
7.5 Register Reference ........................................................................................7-28
7.5.1 Memory Map ...........................................................................................7-28
7.5.2 Register Definitions .................................................................................7-30
7.5.2.1 Control Register (CONTROL)...........................................................7-30
7.5.2.2 Status Register (STATUS) ...............................................................7-31
7.5.2.3 Configuration Register (CONFIG) ....................................................7-32
7.5.2.4 Dynamic Memory Control Register (DYNMCTRL)...........................7-33
7.5.2.5 Dynamic Refresh Register (DYNMREF) ..........................................7-34
7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON).......7-35
7.5.2.7 Dynamic Precharge Command Period Register (PRECHARGE) ....7-36
7.5.2.8 Dynamic Memory Active to Precharge Command Period
Register (DYNM2PRE).............................................................................7-37
7.5.2.9 Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)........7-38
7.5.2.10 Dynamic Memory Last Data Out to Active Time
Register (DOACTIVE) ..............................................................................7-39
7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE).....7-40
7.5.2.12 Dynamic Memory Write Recovery Time Register (DWRT) ............7-41
7.5.2.13 Dynamic Memory Active to Active Command
Period Register (DYNACTCMD) ..............................................................7-42
7.5.2.14 Dynamic Memory Auto-Refresh Period, and Auto-Refresh
to Active Command Period Register (DYNAUTO) ...................................7-43
7.5.2.15 Dynamic Memory Exit Self-Refresh to Active Command
Time Register (DYNREFEXIT).................................................................7-44
7.5.2.16 Dynamic Memory Active Bank A to Active Bank B
Time Register (DYNACTIVEAB) ..............................................................7-45
7.5.2.17 Dynamic Memory Load Mode Register to
Active Command Time Register (DYNAMICTMRD) ................................7-46
7.5.2.18 Static Memory Extended Wait Register (WAIT) .............................7-47
7.5.2.19 Dynamic Configuration Register for nDCS0
and nDCS1 (DYNCFGx)...........................................................................7-48
7.5.2.20 Dynamic Memory RAS and CAS Delay Register for
nDCS0 and nDCS1 (DYNRASCASx).......................................................7-51
7.5.2.21 Static Memory Configuration Register (SCONFIGx)......................7-52
7.5.2.22 Static Memory Write Enable Delay Registers (SWAITWENx)........7-54
7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx)......7-55

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7.5.2.24 Static Memory Read Delay Registers (SWAITRDx).......................7-56
7.5.2.25 Static Memory Page Mode Read Delay Registers
(SWAITPAGEx)........................................................................................7-57
7.5.2.26 Static Memory Write Delay Registers (SWAITWRx)......................7-58
7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)................7-59
Chapter 8 – General Purpose Input/Output
8.1 Theory of Operation .........................................................................................8-1
8.1.1 Port Configuration .....................................................................................8-1
8.1.1.1 Multiplexing.........................................................................................8-2
8.2 Register Reference ..........................................................................................8-7
8.2.1 Memory Map .............................................................................................8-7
8.2.2 Register Descriptions ................................................................................8-8
8.2.2.1 Port A/C/E/G/I/K/M Data Registers (P1DRx)......................................8-8
8.2.2.2 Port B/D/F/H/J/L/N Data Register (P2DRx)........................................8-9
8.2.2.3 Port A/C/E/G/I/K Data Direction Register (P1DDRx)........................8-10
8.2.2.4 Port B/D/F/H/L/N Data Direction Register ........................................8-11
Chapter 9 – I2C Module
9.1 Theory of Operation .........................................................................................9-2
9.1.1 Setting I2C Clock Timing ...........................................................................9-3
9.1.2 Interrupt Handling......................................................................................9-4
9.1.3 Slave Mode ...............................................................................................9-5
9.1.4 Master Mode .............................................................................................9-5
9.1.5 Resetting a Locked Slave..........................................................................9-5
9.2 Register Reference ..........................................................................................9-6
9.2.1 Memory Map .............................................................................................9-6
9.2.2 Register Definitions ...................................................................................9-7
9.2.2.1 I2C Configuration Register (ICCON)...................................................9-7
9.2.2.2 I2C Slave Address Register (ICSAR) .................................................9-8
9.2.2.3 I2C Upper Slave Address Register (ICUSAR)....................................9-9
9.2.2.4 I2C Data Register (ICDATA)...............................................................9-9
9.2.2.5 I2C Clock High Time Register (ICHCNT)..........................................9-10
9.2.2.6 I2C Clock Low Time Register (ICLCNT)...........................................9-10
9.2.2.7 I2C Status Register (ICSTAT)...........................................................9-11
Chapter 10 – I2S Converter
10.1 Theory of Operation .....................................................................................10-3
10.1.1 Conversion ............................................................................................10-3
10.1.2 Driving/Latching Edges .........................................................................10-4
10.1.3 Transmission.........................................................................................10-5
10.1.3.1 Master Mode Transmission............................................................10-5
10.1.3.2 Slave Mode Transmission..............................................................10-6
10.1.4 Reception ..............................................................................................10-7
10.1.4.1 Master Mode Reception .................................................................10-7
10.1.4.2 Slave Mode Reception ...................................................................10-9
10.1.5 Suppression of SSPFSSIN..................................................................10-10
10.1.6 Channel Management.........................................................................10-10
10.1.7 Interrupts.............................................................................................10-11