Sharp XG-V10WU User manual

XG-V10WU
XG-V10WE
1
TECHNICAL MANUAL
TX0L1XG-V10WU
MODELS XG-V10WU
XG-V10WE
This Technical Manual is now prepared to help servicing the
LCD Projector equipped models,and its descriptions are lim-
ited only to“Description of New Circuit”etc.
For more understanding of each model,refer to its respective
Service Manual already issued.
(This Technical Manual is based on Models XG-V10WU and
XG-V10WE.)
LCD PROJECTOR
CONTENTS
Page
1.CVIC INTERNAL BLOCK DIAGRAM ........................... 2
2.CONNECTION BETWEEN CVIC AND SDRAM........... 4
2-1.SDRAM (HY57V653220B-TC7)............................. 6
2-1-1. Description ...................................................... 6
2-1-2. Features .......................................................... 6
2-1-3. Pin layout ........................................................ 7
2-1-4. Pin description ................................................ 7
3.INPUT WIRING DIAGRAM AND ROUTE DIAGRAM ... 8
3-1.IX3434CE (Input section)..................................... 13
3-1-1. Outline........................................................... 13
3-1-2. Internal block diagram................................... 13
3-1-3. Pin description .............................................. 14
3-1-4. Selection of sync signal per input ................. 15
3-2.CXA3516R ........................................................... 15
3-2-1. Outline........................................................... 15
3-2-2. Internal block diagram................................... 15
3-2-3. Pin layout ...................................................... 16
3-2-4. Pin description .............................................. 17
3-2-5. Outline of internal function blocks ................. 19
3-2-6. Timing chart when CXA3516R and
IX3434CE are connected .............................. 22
3-3.SiI151................................................................... 23
3-3-1. Outline........................................................... 23
3-3-2. Internal block diagram................................... 23
3-3-3. Pin layout ...................................................... 24
3-3-4. Pin description .............................................. 25
3-3-5. Timing ........................................................... 26
3-3-6. Power mode .................................................. 27
3-3-7. SiI151 timing chart ........................................ 27
3-4.TLC2933 .............................................................. 28
3-4-1. Outline........................................................... 28
3-4-2. Internal block diagram................................... 28
3-4-3. Pin layout ...................................................... 28
3-4-4. Pin description .............................................. 28
3-5.TLC5733A............................................................ 29
3-5-1. Outline........................................................... 29
3-5-2. Internal block diagram................................... 29
3-5-3. Pin layout ...................................................... 29
3-5-4. Pin description .............................................. 30
3-5-5. Timing ........................................................... 31
3-5-6. V1 line system............................................... 31
4.IX3399 PERIPHERAL IC WIRING DIAGRAM ............ 33
4-1.I/O waveform........................................................ 34
4-2.Block diagram ...................................................... 36
4-3.Pin layout ............................................................. 38
4-4.Pin description ..................................................... 39
4-5.Color irregularity correction.................................. 42
5.D/A PERIPHERAL IC WIRING DIAGRAM ................. 46
5-1.D/A data I/O waveform......................................... 47
5-2.D/A pin layout....................................................... 47
5-3.D/A block diagram................................................ 48
5-4.D/A pin description and I/O pin equivalent circuit 49
6.POWER CONTROL.................................................... 50
6-1.Description of Main-/Sub-microprcessor.............. 51
6-1-1.
Main-microprocessor IC8001 (IX3270CE) pin layout ....... 51
6-1-2.
Main-microprocessor IC8001 (IX3270CE) block diagram 52
6-1-3.
Sub-microprocessor IC2601 (IX3502CE) pin layout ........ 53
6-1-4.
Sub-microprocessor IC2601 (IX3502CE) block diagram . 54
6-2.Data transmission system between
main-microprocessor and sub-microprocessor.... 55
6-3.Simple check of RS-232C OUT port.................... 60
6-4.Key entry detection .............................................. 60
6-5.Detection of remote controller operation.............. 60
6-6.Temperature detection ......................................... 60
6-7.Detection of cooling fan rotation .......................... 61
6-8.
Checking internal temperature and fan rotation all at once ..... 61
6-9.Appendix on power supply................................... 61
Page
SHARP CORPORATION

XG-V10WU
XG-V10WE
2
1. CVIC INTERNAL BLOCK DIAGRAM
Fig. 1 shows the data flow inside of the CVIC.
Figure 1.
Video
input
Video
input
controller
Image
processor
module
Display
output
controller
Video
output
Internal bus
External
bus
controller
External CPU,
etc.
SDRAM
controller
CPU
SDRAM
External I/O

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XG-V10WE
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Video input controller
Video data entrance to CVIC, which performs the following processing.
Conversion of the received video data into CVIC’s internal data structure.
Storage of the converted video data into video buffer memory (SDRAM).
Collecting data to detect resolution or refresh rate of the received video data.
Collecting data for automatic synchronization.
Display output controller
Video data exit from CVIC.
External output of the video data read out from the video buffer memory (SDRAM) at the preset timing.
Conversion of the CVIC data structure into the one suitable for external use.
Gamma correction.
Overlapping OSD (On Screen Display) onto the video data.
In the OSD overlapping, any transparency can be set arbitrarily out of 256 grades.
External bus controller
Connecting unit between CVIC and external microprocessor or ROM.
Data interchange with 16-bit width.
External microprocessor or ROM can access the SDRAM data to read/write them.
Video buffer memory (SDRAM) data in CVIC can be read/written.
OSD buffer memory (SDRAM) data can be read/written.
External microprocessor or ROM can communicate with internal CPU of CVIC via the 32-bit width register.
Transfer of the program for CVIC, as well as the bit map data and the font data for OSD.
CPU
Executes the programs in SDRAM and controls each block (module) inside of CVIC.
SDRAM controller
Connecting unit between CVIC and external SDRAM.
Data input/output with 128-bit width data bus.
Operational clock frequency is 100MHz.
Image processor module
Video data converting unit.
IP conversion, enlarge/reduce of the video data, and filtering are performed.

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2. CONNECTION BETWEEN CVIC AND SDRAM
CVIC and SDRAM are connected in 128-bit data width as shown in the figure below.
1514131211109876543210
127-120 119-112 111-104 103-96 95-88 87-80 79-72 71-64 63-56 55-48 47-40 39-32 31-24 23-16 15-8 7-0
DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 DQM1 DQM0
119-96 95-72 71-48 47-24 23-0
127-96 95-64 63-32 31-0
MSB LSB
Byte
Bit
DQM
Pixel
32-bit access
The following signals coming out from CVIC are common for each SDRAM: CLK, XCS, XRAS, XCAS, XWE,
SD_BA0, SD_BA1, and SDA0 to SDA10.
The data bus (SDD0 ~ SDD127) is allocated to the four SDRAMs in every 32 bits.
Due to CVIC’s internal data structure, DQM0 ~ DQM7 is allocated irregularly as shown in the figure below.
Figure 2-1.
Figure 2-2.
CKE is tied to the high level (3.3V).
SDRAM
IC8319
IC8320
IC8321
IC8322
CVIC
IC8025

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5
The connection with each SDRAM is shown in the figures below.
The numerals in each SDRAM box designate the pin numbers.
Figure 2-3.
Between CVIC and IC8319
CVIC
IC8025 SDRAM
IC8319
CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
A0
˜ A10
DQM0
DQM1
DQM2
DQM3
DQ0
˜ DQ31
CLK
XCS
XRAS
XCAS
XWE
SD_BA0
SD_BA1
SDA0
˜ SDA10
DQM0
DQM1
SDD0
˜ SDD31
68
20
19
18
17
22
23
16
71
28
59
Figure 2-4.
Between CVIC and IC8321
CVIC
IC8025 SDRAM
IC8321
CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
A0
˜ A10
DQM0
DQM1
DQM2
DQM3
DQ0
˜ DQ31
CLK
XCS
XRAS
XCAS
XWE
SD_BA0
SD_BA1
SDA0
˜ SDA10
DQM2
DQM3
SDD32
˜ SDD63
68
20
19
18
17
22
23
16
71
28
59
Figure 2-5.
Between CVIC and IC8320
CVIC
IC8025 SDRAM
IC8320
CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
A0
˜ A10
DQM0
DQM1
DQM2
DQM3
DQ0
˜ DQ31
CLK
XCS
XRAS
XCAS
XWE
SD_BA0
SD_BA1
SDA0
˜ SDA10
DQM4
DQM5
SDD64
˜ SDD95
68
20
19
18
17
22
23
16
71
28
59
Figure 2-6.
Between CVIC and IC8322
CVIC
IC8025 SDRAM
IC8322
CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
A0
˜ A10
DQM0
DQM1
DQM2
DQM3
DQ0
˜ DQ31
CLK
XCS
XRAS
XCAS
XWE
SD_BA0
SD_BA1
SDA0
˜ SDA10
DQM6
DQM7
SDD96
˜ SDD127
68
20
19
18
17
22
23
16
71
28
59

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XG-V10WE
6
2-1. SDRAM (HY57V653220B-TC7)
2-1-1. Description
The HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which
require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input.The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1, 2, 4, 8 or full page), and the burst count sequence
(sequential or interleave).A burst of read or write cycles in progress can be terminated by a burst terminate command
or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not
restricted by a `2N` rule.)
2-1-2. Features
»JEDEC standard 3.3V power supply
»All device pins are compatible with LVTTL interface
»JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch
»All inputs and outputs referenced to positive edge of system clock
»Data mask function by DQM0, 1, 2 and 3
»Internal four banks operation
»Auto refresh and self refresh
»4096 refresh cycles / 64ms
»Programmable Burst Length and Burst Type
-1, 2, 4, 8 or full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
»Programmable CAS Latency; 2, 3 Clocks
»Burst Read Single Write operation

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2-1-3. Pin layout
Figure 2-7.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
86pin TSOP II
400mil x 875mil
0.5mm pin pitch
2-1-4. Pin description
Pin Pin Name Description
The system clockinput.All other inputs are registered to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during / RAS activity
Selects bank to be read/written during /CAS activity
Row Address:RA0 ~ RA10, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
/RAS, /CAS and /VVE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in
write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
CLK Clock
CKE Clock Enable
/CS Chip Select
BA0, BA1 Bank Address
A0~A10 Address
/RAS, /CAS, /WE Row Address Strobe
Column Address Strobe
Write Enable
DQM0 ~ 3 Data Input/Output Mask
DQ0 ~ DQ31 Data Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
NC No Connection
Remarks: CKE is tied to the high level (3.3V).

XG-V10WU
XG-V10WE
8
3. INPUTWIRING DIAGRAM AND ROUTE DIAGRAM
»Wiring diagram
IX3434CE (Input section)
Sync detect, clock control, color space conversion, data structure conversion, and auto sync adjustment.
CXA3516R
3ch 8-bit 165MSPS A/D converter with built-in amplifier and PLL.
SiI151
Receiver for DVI digital input
TLC2933
PLL for V1 lines
TLC5733A
3ch 8-bit A/D converter (for component/composite signals of 480I/580I)
Figure 3-1.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 – RA7
RB0 – RB7
GA0 – GA7
GB0 – GB7
BA0 – BA7
BB0 – BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
SiI151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
R(Video)
G(Video)
B(Video)
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit

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XG-V10WE
9
* V0 lines are connected to CXA3516R and SiI151, whileV1 lines to TLC2933 and TLC5733A.
» Route diagram
(a) NTSC, PAL, 480I/580I
component signal input
(b) DVI digital signal input
Figure 3-2.
Figure 3-3.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
R(Video)
G(Video)
B(Video)
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit

XG-V10WU
XG-V10WE
10
(c) DVI analog signal input
Figure 3-4.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
R(Video)
G(Video)
B(Video)
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit
(d)RGB Sync On Green signal
input
Figure 3-5.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit

XG-V10WU
XG-V10WE
11
(e) DTV (other than 480I/580I)
component signal input
Figure 3-6.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit
(f) Mac C sync signal input
Figure 3-7.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit

XG-V10WU
XG-V10WE
12
(g) Other input (PC input, etc)
than described above
(a)~(f)
Figure 3-8.
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_VDCLK_I[TTL]
V0_PVDCLK/NVDCLK[ECL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V0_VDCLK_O[TTL]
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_VDCLK_I[TTL]
V1_PVDCLK/NVDCLK[ECL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
V1_VDCLK_O[TTL]
RA0 –RA7
RB0 –RB7
GA0 –GA7
GB0 –GB7
BA0 –BA7
BB0 –BB7
1/2CLK
DSYNC/DIVOUT
HOLD
EVEN/ODD
SYNCIN1
SYNCIN2
CLPIN
G/YIN1
G/YIN2
B/CbIN1
B/CbIN2
R/CrIN1
R/CrIN2
IC8325
CX3516R
1C1 1Y
1C0
G(Analog)
IC8004
IC8025 CVIC
(VIC section)
IX3434CE
IC8334, IC8335,
IC8336, IC8337
P8012
AIN
BIN
CIN
CLK
AD1-8
BD1-8
CD1-8
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
FIN_A
PFD_INHIBIT
FIN_B VCO_OUT
EN1
IC8298
IC8328
TLC2933
TLC5733A
Sil151
IC8000
IC8323,
IC8324,
IC8326
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
VV_IN
VH_IN
CSYNC
IH_CON 1Y
2Y
1C1
2C3
IC8302
IV_CON
1C2
2C2
1C0
1C3
2C0
2C1
DVI_RO
DVI_GO 2
1
P8001
10
9
18
17
23
24
C2
C3
C4
C1
8
DVI_BO
IC8331
IC8330
36
36
Noise filter,
Peak clamp for
Sync On Green
V0 lines
V1 lines

Clamp
circuit

XG-V10WU
XG-V10WE
13
3-1. IX3434CE (Input section)
3-1-1. Outline
Sync detect, clock control and data structure conversion are performed against the signals received.
Input lines consist ofV0 and V1 lines. V1 lines are dedicated to the processing of component and composite signals of
480I/580I, while V0 lines are to the processing of signals with other resolutions.
3-1-2. Internal block diagram
Figure 3-9.
Sync detect
Checks the received sync signal to detect its resolution level.
Frequency divider
Generates the horizontal sync signal in accordance with the ratio of frequency division. (V1_HSYNF)
Clamp signal generation
Generates the clamp signal in accordance with the received sync signal.
Clock control
In V0 lines, the clock received at V0_VDCLK_I for 2-phase data is used also for data latching. In V1 lines, the 4 x
sampling clock frequency (V1_VDCLK_I) received fromTLC2933 is divided to 1/4 to send it out fromV1_VDCLK_O
and use it at TLC5733A.
Color space conversion
Data matrix conversion is performed.
V0_HSYNC, V0_VSYNC
V0_CSYNC, V0_GSYNC
V0_PDEN, V0_CLP
V0_HSYNR
V0_HSYNC2, V0_VAL
V0_RA0
˜
7,V0_GA0
˜
7
V0_BA0
˜
7
V0_RB0
˜
7,V0_GB0
˜
7
V0_BB0
˜
7
V0_VDCLK_I
V1_HSYNC, V1_VSYNC
V1_PDEN, V1_CLP
V1_HSYNR, V1_HSYNF
V1_RA0
˜
7, V1_GA0
˜
7
V1_BA0
˜
7
V1_VDCLK_I
V1_VDCLK_O
HS_A, VS_A
DATA_A
DE_A
HACT_A
VACT_A
PCLK_A
HS_B, VS_B
DATA_B
DE_B
HACT_B
VACT_B
PCLK_B
Input section
V0 lines
Synchronization
Sync detect
Frequency
divider
Clamp signal
generation
Sync detect
Frequency
divider
Clamp signal
generation
Synchronization
Synchronization
Data
Synchronization
Data
Data processing
» Color space
conversion
» Sync delay
» Interrupt signal
generation
Control signal
Data
Data
Clock
control
Clock
control
Auto sync
adjustment
V1 lines
Synchronization Synchronization
Data processing
» Color space
conversion
» Sync delay
» Interrupt signal
generation
Control signal
Clock
Clock

XG-V10WU
XG-V10WE
14
3-1-3. Pin description
Name I/O Bit Width Description
V0_ACT I 1 Tied GND
V0_VAL I 1 Data validity indicator signal
V0_HSYNC I 1 Horizontal sync signal
V0_VSYNC I 1 Vertical sync signal
V0_CSYNC I 1 Composite sync signal
V0_GSYNC I 1 Sync On Green signal
V0_HSYNC2 I 1 Horizontal sync signal synchronized with V0_VDCLKI
V0_PVCLK/NVCLK I 1 Tied GND
V0_PVDCLK/NVDCLK I 1 Tied GND
V0_VDCLK_I I 1 Clock for data latch [TTL]
V0_RA I 8 Input data R (Cr, Pr) (Single phase)
V0_GA I 8 Input data G (Y) (Single phase)
V0_BA I 8 Input data B (Cb, Pb) (Single phase)
V0_RB I 8 Input data R (Cr, Pr) (Two phase)
V0_GB I 8 Input data G (Y) (Two phase)
V0_BB I 8 Input data B (Cb, Pb) (Two phase)
V1_ACT I 1 Tied GND
V1_VAL I 1 Tied GND
V1_HSYNC I 1 Horizontal sync signal
V1_VSYNC I 1 Vertical sync signal
V1_CSYNC I 1 Tied GND
V1_GSYNC I 1 Tied GND
V1_HSYNC2 I 1 Tied GND
V1_PVCLK/NVCLK I 1 Tied GND
V1_PVDCLK/NVDCLK I 1 Tied GND
V1_VDCLK_I I 1 4 x frequency clock from TLC2933 [TTL]
V1_RA I 8 Input data R
V1_GA I 8 Input data G
V1_BA I 8 Input data B
V1_RB I 8 Tied GND
V1_GB I 8 Tied GND
V1_BB I 8 Tied GND
V0_PDEN O 1 Signal to stop external PLL phase comparison (Low-active)
V0_HSYNF O 1 OPEN
V0_HSYNR O 1 Horizontal sync signal for reference (Active low)
V0_PADRST/NADRST O 1 OPEN
V0_PADCLK/NADCLK O 1 OPEN
V0_VDCLK_O O 1 OPEN
V0_CLP O 1 Clamp pulse signal (Active high. Outputted from trailing edge of the horizontal sync pulse.)
V1_PDEN O 1 Signal to stop external PLL phase comparison (Active high)
V1_HSYNF O 1 Horizontal sync signal for feedback (Active low)
* Used to control the dot clock frequency generated by external PLL.
V1_HSYNR O 1 Horizontal sync signal for reference (Active low)
V1_PADRST/NADRST O 1 OPEN
V1_PADCLK/NADCLK O 1 OPEN
V1_VDCLK_O O 1 External A/D converter operation clock [TTL]
V1_CLP O 1 Clamp pulse signal (Active high [1µs pulse width].Outputted from leading edge
of the horizontal sync pulse.)
Sync delay
Delays the sync signal for horizontal/vertical positioning of synchronization in the user menu.
Interrupt signal generation
Generates the interrupt signal for IX3434CE’s internal use.
Auto sync adjustment
Automatically adjusts clock, horizontal phase, horizontal position and vertical position in the user menu synchroni-
zation on the basis of the received sync signal and data.

XG-V10WU
XG-V10WE
15
3-1-4. Selection of sync signal per input
Sync signal is selected according to the input. IC8302 IC8325
DVI analog input 1C2 2C2 1C1
DVI digital input 1C3(*1) 2C3(*1) 1C1
Component/composite 1C0 2C0 1C1
input of 480I/580I
Mac C sync input 1C1 2C1 1C0
Other than above 1C1 2C1 1C1
(In normal operation)
Connect to
V0_HSYNC Connect to V0_VSYNC Connect to SYNCIN1
INPUT
(*1) To make sync check inV0 lines.
3-2. CXA3516R
3-2-1. Outline
3h 8-bit 165MSPS A/D converter with built-in amplifier and PLL. The received RGB analog signals are given the level
control and then converted into the digital data with the clock generated by PLL to be outputted inTTL level. Operates
with the maximum conversion speed of 165MHz.
3-2-2. Internal block diagram
»TOP block diagram
Figure 3-10.
Sub Contrast (8)
Sub Brightness (8)
Cr Offset (6)
AMP R
SW
ADC R RB7
˜
RB0
RA7
˜
RA0
SW
R
R/CrIN1
R/CrIN2
CLPIN R/CrOUT
SW
G/YOUT B/CbOUT
SW VRT
DATA MODE
VRT
VRB
VRB
R/CrCLP
Sub Contrast (8)
Sub Brightness (8)
AMP G ADC G GB7
˜
GB0
GA7
˜
GA0
SW
G
G/YIN1
G/YIN2
G/YCLP
Sub Contrast (8)
Sub Brightness (8)
Cb Offset (6)
Main Contrast (8)
AMP B ADC B BB7
˜
BB0
BA7
˜
BA0
CLK
XCLK
1/2CLK
1/2XCLK
DSYNC/DIVOUT
SW
B
SW
SYNCIN
PD VCO DIV
1,2,4,8
CP (3) FINE
DELAY
(6)
SYNCTIP
CLP
SW
SOGP
SW
SOGT
Width
(2)
COUNTER (12) 1/2DIV
PLL
COARSE
DELAY (2)
SW
PLL
SW
SOGO REGISTER
B/CbIN1
B/CbIN2
SYNCSEP
SYNCSEP
V TH (4) V HYS (2)
SYNCSEP
SOGIN1
SYNCIN2
SYNCIN1
XPOWER SAVE
ADDRESS
SDA
SCL
XSENABLE
SEROUT
SOGOUT
3WIRE/I
2
C
EVEN/ODD
UNLOCK
HOLD
RC1 RC2
XTLOAD
SOGIN2
B/CbCLP

XG-V10WU
XG-V10WE
16
3-2-3. Pin layout
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108 107 105 104103 102 101100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
XCLKIN
CLKIN
SYNCIN1
SYNCIN2
CLPIN
DV
CC PLL
DGNDPLL
AV
CC VCO
AGNDVCO
RC1
RC2
AVccIR
IREF
DPGND
AGNDIR
G/YIN1
AV
CC AMPG
G/YIN2
AGNDAMPG
G/YCLP
B/CbCLP
R/CrCLP
DPGND
SOGIN1
B/CbIN1
AV
CC AMPB
SOGIN2
B/CbIN2
AGNDAMPB
DPGND
R/CrIN1
AV
CC AMPR
R/CrIN2
AGNDMPR
G/YOUT
DACTESTOUT
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GA4
GA3
GA2
GA1
GA0
DGNDADTTL
DGNDAD3
DV
CC ADTTL
BB7
BB6
BB5
BB4
BB3
GNDAD3
BB2
BB1
BB0
DGNDADTTL
DV
CC ADTTL
BA7
BA6
BA5
DGNDAD3
BA4
BA3
BA2
BA1
BA0
DGNDADTTL
DGNDAD3
DV
CC ADTTL
RB7
RB6
RB5
RB4
RB3
B/CbOUT
ADDRESS
R/CrOUT
NC NC
XPOWER SAVE
DGNDREG
DV
CC
REG
SDA
SCL
XSENABLE
SEROUT
3WIRE/I
2
C
DPGND
AV
CC
ADREF
AV
CC
AD3
VRT
DV
CC
AD3
DV
CC
ADTTL
DGNDADTTL
RA0 RA1
DGNDAD3
RA2 RA3 RA4 RA5 RA6
AGNDAD3
DGNDAD3
RA7
DV
CC
ADTTL
DGNADTTL
RB0 RB1 RB2
EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL DV
CC
PLLTTL
AGNDADREF AV
CC
AD3
VRB DV
CC
AD3
DV
CC
AD
DV
CC
ADTTL
DGNDADTTL GB7 GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 DGNDAD3 GB0 DGNDADTTL DV
CC
ADTTL
GA7 GA6 GA5
106 91
12 4567891011121314151617 192021222324252627282930313233343536
318
Figure 3-11.

XG-V10WU
XG-V10WE
17
3-2-4. Pin description
Pin No. Name I/O Standard Signal Description
1 B/CbOUT O 1.7V Amplifier output signal monitor
2 ADDRESS I –I2C slave address setting
3 R/CrOUT O 1.7V Amplifier output signal monitor
4NC ––No connection
5NC ––No connection
6 XPOWER SAVE I TTL Power save setting
7 DGNDREG –GND Tied GND
8 DVCCREG –5V Tied 5V
9SDA I–Control register data input
10 SCL I –Control register clock input
11 XSENABLE I TTL Tied GND
12 SEROUT O TTL OPEN
13 3WIRE/I2CI –Selection of either I2C or 3-wire bus mode
15 AVCCADREF –5V Power supply for reference voltage of ADC
16,94 AVCCAD3 –3.3V Analog power supply of ADC
17 VRT O 2.9V Top reference voltage output of ADC
18,92 DVCCAD3 –3.3V Digital power supply of ADC
19, 32, 42, 54, 65, 76, 90 DVCCADTTL –5V Power supply for TTL output of ADC
20, 33, 44, 55, 67, 77, 89 DGNDADTTL –GND Ground for TTL output of ADC
21, 22, 24~28, 31 RA0~RA7 O TTL R channel port A data output
23,30, 43, 50,59, 66, 79, 86 DGNDAD3 –GND Digital ground of A/D converter
29, 80 AGNDAD3 –GND Analog ground of A/D converter
34~41 RB0~RB7 O TTL R channel port B data output
45~49, 51~53 BA0~BA7 O TTL B channel port A data output
56~58, 60~64 BB0~BB7 O TTL B channel port B data output
68~75 GA0~GA7 O TTL G channel port A data output
78, 81~85, 87, 88 GB0~GB7 O TTL G channel port B data output
91 DVCCAD –5V Digital power supply of ADC
93 VRB O 1.9V Bottom reference voltage output of ADC
95 AGNDADREF –GND Ground for reference voltage of ADC
96 DVCCPLLTTL –5V Power supply for TTL output of PLL
97 DGNDPLLTTL –GND Ground for TTL output of PLL
98 XCLK O TTL OPEN
99 CLK O TTL OPEN
100 1/2XCLK O TTL 1/2 inverted clock output
101 1/2CLK O TTL 1/2 clock output
103 DSYNC/DIVOUT O TTL DSYNC signal output/DIVOUT signal output
104 UNLOCK O OPEN COLLECTOR UNLOCK signal output pin
105 SOGOUT O TTL OPEN
106 HOLD I TTL Phase comparison disable signal input
107 XTLOAD I TTL OPEN
108 EVEN/ODD I TTL Sampling clock inverted pulse input of ADC
109 XCLKIN I PECL OPEN
110 CLKIN I PECL OPEN

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18
111 SYNCIN1 I TTL Sync signal input 1
112 SYNCIN2 I TTL Sync signal input 2
113 CLPIN I TTL Clamp pulse input
114 DVCCPLL –5V Digital power supply for PLL
115 DGNDPLL –GND Digital ground for PLL
116 AVCCVCO –5V Analog power supply for VCO of PLL
117 AGNDVCO –GND Analog ground for VCO of PLL
118 RC1 –2.1V Pin for external PLL loop filter
119 RC2 –2V~4.5V Pin for external PLL loop filter
120 AVCCIR 5V Analog power supply for IREF
121 IREF I 1.2V Current setting
123 AGNDIR GND Analog ground for IREF
124 G/YIN1 I –G/Y signal input 1
125 AVCCAMPG –5V Power supply for G amplifier
126 G/YIN2 I –G/Y signal input 2
127 AGNDAMPG –GND Ground for G/Y amplifier
128 G/YCLP ––Connector pin of clamp condenser for brightness
129 B/CbCLP ––Connector pin of clamp condenser for brightness
130 R/CrCLP ––Connector pin of clamp condenser for brightness
132 SOGIN1 I 2.8V Sync On Green signal input 1
133 B/CbIN1 I –B/Cb signal input 1
134 AVCCAMPB –5V Power supply for B/Cb amplifier
135 SOGIN2 I 2.8V Sync On Green signal input 2
136 B/CbIN2 I –B/Cb signal input 2
137 AGNDAMPB –GND Ground for B/Cb amplifier
139 R/CrIN1 I –R/Cr signal input 1
140 AVCCAMPR –5V Power supply for R/Cr amplifier
141 R/CrIN2 I –R/Cr signal input 2
142 AGNDAMPR –GND Ground for R/Cr amplifier
143 G/YOUT O 1.7V Amplifier output signal monitor
144 DAC TEST OUT O 5V Test output pin of DAC for amplifier control register
14, 102, 122, 131, 138 DPGND –GND GND
Pin No. Name I/O Standard Signal Description

XG-V10WU
XG-V10WE
19
Component Signal User Menu Setting (User Setting) Process Setting
input DTV
(Excluding 480I/580I) Item Range Process Menu Item Range
CONTRAST CXA3516 main contrast 0~255 –––
BRIGHT Add to DTV R/G/B 0~180 DTV G-BRIGHT CXA3516 G 0~75
sub-bright sub-bright
COLOR G/A1 -30~30 –––
TINT G/A1 -30~30 –––
RED Add to DTV CR-OFFSET 0~30 DTV CR-OFFSET CXA3516 Cr offset 0~33
BLUE Add to DTV CB-OFFSET 0~30 DTV CB-OFFSET CXA3516 Cb offset 0~33
3-2-5. Outline of internal function blocks
» AMP block
3-channel amplifier optimizes, for ADC input, RGB analog input signal connected to condenser andYCbCr
analog input signal. Analog input signal connected to condenser is given a sync clamp on its pedestal level by
the clamp pulse received externally (CLPIN pin (113)).
There are 2 lines in analog input signal. One is any of INPUT1 to 6 selected and excluding 480i/580I composite
signals, while another is DVI analog input signal.
In the RGB input mode, the clamp level for black level adjustment is adjusted by sub-brightness in 256 grades for
each of the 3 channels independently. In the component input mode, the adjustment is made using the median
point of ADC input dynamic range as its middle point.
User menu setting and process setting
RGB input User Menu Setting (User setting) Process Setting
Item Range Process Menu Item Range
CONTRAST CXA3516 main contrast 0~255 –––
BRIGHT Add to AD R/G/B 0~180 AD R/G/B-BRIGHT CXA3516 R/G/B 0~75
sub-bright sub-bright
RED Add to AD R-D 0~80 AD R-D CXA3516 R contrast 0~175
BLUE Add to AD B-D 0~80 AD B-D CXA3516 B contrast 0~175
» SYNC block
Horizontal sync signal used for PLL is any of the signals selected among SYNCIN1 pin (111), SYNCIN2 pin
(112) and G/YIN1 pin (124) after sync separation.
Input pin Connection Condition for selection
SYNCIN1 External horizontal sync In normal operation
SYNCIN2 Horizontal sync output (V0_HSYNR pin (406)) ·No signal
from IX3434CE (input section) ·DTV component signal input
G/YIN1 Analog input (G/Y) RGB Sync On Green input
·The sync signal inputted to IX3434CE (input section) can be observed with SYNCIN2.

XG-V10WU
XG-V10WE
20
In the case of RGB Sync On Green input, G/YIN1 pin (124) signal passes through the noise filter and the peak
clamp circuit and goes into V0_GSYNC pin (316) of IX3434CE, same as DTV component input. IX3434CE
(input section) carries out the mode detect and clamp generation to output G/YIN1 pin (124) at V0_CLP pin (128)
where the signal is given a pedestal clamp. The signal thus processed is then given a sync separation by
CXA3516R to operate the PLL.
In the case of DTV component input, G/YIN1 pin (124) signal carrying horizontal sync data passes through the
noise filter and the peak clamp circuit and goes into V0_GSYNC pin (316) of IX3434CE. Then, IX3434CE (input
section) carries out the mode detect, clamp generation and sync separation. The signal after sync separation
coming out from V0_HSYNR pin (406) then goes into SYNCIN2 pin (112) of CXA3516R to operate the PLL.
Figure 3-12.
SYNC OUT SW
1bit
SW
SOGO
SOG OUT POL
1bit
1bit
SOG Enable
SOGOUT
PLL
POL
POL
TTL
OUT
1bit
SYNC POL
SW
SOGP
SYNCIN1
PEDESTAL
CLAMP
AMP
BLOCK PLL BLOCK
SYNC
SEP
SYNC
SEP
SYNC
SEP
1bit
SYNCP/HSYNC
4bit
V
TH
2bit
V
HYS
1bit
RGB IN 1/2 Select
SW
PLL
1bit
HSYNC1/2
SW
SYNCIN
SW
SOGT
SOGIN1
B/CbIN1
G/YIN1 SYNCP1
SYNCT1
R/CrIN1
H1
B1
G1
R1
SYNCIN2
SOGIN2
B/CbIN2
G/YIN2 SYNCP2
SYNCT2
R/CrIN2
H2
B2
G2
R2
PEDESTAL
CLAMP
SYNC TIP
CLAMP
SYNC TIP
CLAMP
Analog input (G/Y)
Noise filter,
Peak clamp
»Sync detect
»Clamp signal
generation
»Sync separation
RGB Sync On Green input
DTV component input
IX3434CE
V0_HSYNC2 (107pin)
V0_GSYNC (316pin)
CXA3516R
G/YIN1 (124pin)
SYNCIN2 (112pin)
CLPIN (113pin)
DSYNC (103pin)
V0_CLP (218pin)
V0_HSYNR (406pin)