Shugart SA4600 User manual

SA4600 ©
Fixed Disk Controller I
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SA4600 ©
Fixed Disk Controller I
Copyright 1979 Shugart Associates
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Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
Introduction . . . .
Specification Summary
SA4000 Drive Interface Description
Host
CPU Interface Description
4.1 Reset.....
4.2 Controller Select .
4.3 Address
4.4
Read ...
4.5 Write...
4.6 Data Bus 0-7 .
4.7
DMA Request .
4.8
DMA Acknowledge .
4.9
Interrupt.....
Host CPU Interface Register Description.
5.1 Command Register . . . . .
5.2 Parameter Register . . . . .
5.3 Status Register. . . . . . .
5.3.1 Command Busy and Command
Reg Full. .
5.3.2 Parameter
Reg Full
5.3.3 Result Reg Full . . .
5.3.4
Interrupt......
5.4 Result Register. . . .
5.4.1 Result Byte Description
5.4.1.1 Good Completion. . . .
5.4.1.2 Sub System Error. . .
5.4.1.3 Operator Intervention .
5.4.1.4 Command Erroi . .
Command Description. . . . .
6.1 Control Commands. .
6.1.1 Initialize ..... .
6.1.1.1 Sector Interleave Code.
6.1.2 Recalibrate.....
6.1.3 Seek........
6.1.4 Terminating Sector Request. .
6.2 ReadlWrite Commands
6.2.1 Format Cylinder .
6.2.2
WriteID ....
6.2.3 Write Data . . . .
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
VVrite Data Special
Read ID ....
Read Data . . .
Read Data and Special.
Search Data Equal . .
Search Data Equal and Special.
Search Data High or Equal . .
Search Data High or Equal and Special.
Search Data Low or Equal . . . . .
Search Data Low or Equal and Special.
2
2
2
3
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
10
10
10
11
1 1
I I
11
11
11
12
13
13
13
13
14
14
14
1A
I"T
14
14
14
14
15
15
15
15
15

Table of Contents
7.0
8.0
9.0
10.0
11.0
12.0
6.2.14
6.3
6.3.1
6.3.2
Verify
Data. . . .
Control Read/Write. .
Read Diagnostic
Write
Buffer.
Command Procedure . .
Optional Host CPU Interface Configurations
8.1 Rand WJumper Description .
8.2
RQ and A Jumper Description.
8.3 F Jumper Description .
SA4000 Drive Option Description
9. 1 Control PCB. . . . . .
9.1.1 Drive Select. . . . .
9.1.2 Byte Clock/Sector Mark
9.1.3
Miscellaneous....
9.1.4 Sector Counter Options
9. 1.5 Cable Termination Description
9.2
Data Separator PCB. .
Format Description. .
Error Retry. . . .
Physical Description.
12.1 PC Board.
12.2 Connectors
12.2.1 50
Pin Connectors
12.2.2 20
Pin Connectors
12.2.3 Power Connector.
Appendix A -
General Microcode Flowchart.
Appendix B - Schematics . . . . . . . .
ii
15
15
15
15
15
16
16
17
17
17
. . .' 17
17
18
18
18
18
18
18
19
19
19
20
20
20
20
22
24

List of Illustrations
1.
2.
3.
4.
5.
6.
7.
7.1
8.
9.
10.
11.
12.
SA4600 Interface Block Diagram. . . .
Pin Assignments
for J1 and J2 Thru J5
Pin Assignments for Host CPU I/O (J6)
Host
CPU Control Interface Timing. . .
Host
CPU DMA Interface Timing. . .
Optional Host CPU Interface Connection
RQ Jumper Option Timing (Read Mode) .
A Jumper
Option Timing (Write Mode)
SA4600 Format . . . . . .
P.C.B. Physical
Layout Drawing .
50 Pin Connector Drawing ....
20 Pin Connector Drawing
DC Connector Drawing .
List of Tables
1.
2.
3.
4.
5.
6.
7.
8.
Interface Register Map. .
Command Code Chart .
Parameter
Description.
Status Register Map. .
Resu It Register Map. .
Initialize Parameter Map .
Interleave Code . . .
Sector Counter Options .
3
4
5
6
7
16
17
17
19
20
21
21
21
4
8
9
9
10
12
13
18
iii

1.0 INTRODUCTION
The SA4600 Disk Controller is a complete preprogrammed microprocessor based controller
for the Shugart SA4000 series disk drives and SA800/8S0 Floppy Disk Drive.
The SA4600 Disk Controller is designed to perform asyncronous
data transfers between the
SA4000 and a host CPU.
The SA4600 features a general purpose DMA type interface designed to easily adapt to com-
mercially available DMA controller chips.
Several optional configurations also make this interface adaptable to virtually any
type of
mini or micro computer. Some main features of this controller are as follows:
A) Control of one to four SA4000 drives and one to four SA800/8S0 Floppy Disk Drives.
B) Asyncronous DMA transfer with full sector buffering.
C) Four user selectable formats -32 sectors of S12 bytes, 60 sectors of 2S6 bytes, 104
sectors of 128 bytes, or 26 sectors of 2S6 bytes (Floppy option only).
D) Overlap seek operation (up to four drives).
E) Single five volt supply.
2.0 SPECIFICATION SUMMARY
Environmental Limits
Ambient temperature =
O°C to SO°C
= 20% to 80%
Relative humidity
OC Voltage Requirements
+S VDC ± S% 7.0A typical 7.S maximum (with floppy option)
Heat Disipation = 120 BTU/hr. typical
Mechanical Dimensions (reference Figure 8)
Length = 18" (4S.72cm)
Width =
l2.S" (31.7Scm)
Height = 1" (2.S4cm)
3.0 SA4000 DRIVE INTERFACE DESCRIPTION (Reference Figure 1)
The SA4000 drives are interfaced through connectors Jl, J2, J3, J4 and JS.
Jl is a SO pin ribbon cable type edge connector which connects the SA4000 drives in a daisy
chain configuration. Up
to four drives may be bussed together on this cable. This cable
should
not exceed 20 feet (6 meters). Refer to section 9.l.S -Cable Termination
Description.
J2 through JS are 20 pin ribbon cable type edge connectors which are the radial connectors
for
up to four drives. J2 is the radial connector for Drive 1. J3 is the radial connector for
Drive
2, etc. These cables should not exceed 20 feet (6 meters). Refer to Figure 2 for a
diagram
of the pinouts for J1 and J2 through JS.
Refer
to section 12.2 for Connector Physical Description.
2

HOST CPU
CONTROL
HOST CPU
DATA
J6
50 PIN
SA4600
J6
50 PIN
Jl
50 PIN
J2
20 PIN
J3
20 PIN
J4
20 PIN
J5
20 PIN
w
.....J
co
«
u
z
«
I
u
>-
U)
«
Cl
w
>
cr:
Cl
Figure 1. SA4600 Interface Block Diagram
4.0 HOST CPU INTERFACE DESCRIPTIOr\l
Jl
SA4000
DRIVE 1
J2
Jl
SA4000
DRIVE 2
J2
Jl
SA4000
DRIVE 3
J2
Jl
SA4000
DRIVE 4
J2
The SA4600 host CPU interface is a general purpose DMA type interface which is accom-
plished
through connector J6. J6 is a 50 pin ribbon type cable edge connector. Refer to
Figure 3 for pin assignments. All signals to the CPU interface are TTL negative true, 48MA.
This cable should
not exceed 10 feet (3 meters).
A description of the CPU interface lines follows:
4.1 Reset
This line will cause the controller
to cease all operation, clear local ram memory, reset the
command, status, and result registers, and go into a normal wait loop. A reset during a write
operation may cause improper data to be written. The RESET pulse width must be at least
200 nanoseconds. The SA4600 will not accept a command for 3 milliseconds after a reset.
The
host CPU must time out for 3 ms.
4.2 Controller Select
This signal functions as a device select and should only be active when one of the four
registers in the controller are
to be operated on.
4.3 Address
The address line selects which register will be read/written. See Table
1.
3

J1
Ground 1 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Ground 49 50
4.4 Read
-Head Select 1
-Head Select 2
-Head Select 4
-Head Select 8
-Index
-Ready
-Sector Mark
-Drive Select 1
-Drive Select 2
-Drive Select 3
-Drive Select 4
-Direction
-Step
-Fault Clear
-Write Gate
-Track 00
-Write Fault
-Read Gate
!\I/C
NIC
-Index
-Ready
-Byte Clk Sector
-Seek Complete
+WRT Data
Ground
-Write Clock
+PLO Clock
Ground
-Read Data
Figure 2.
Pin Assignments for J1 and J2 Thru J5
J2 -J5
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
Ground
Ground
Ground
Ground
-WRT Data
+WRT Clock
Ground
-PLO Clock
+Read Data
Ground
When this line is active along with controller select, one of two read only registers will be
read onto the data bus. See Table 1 and host interface timing, Figure
4.
4.5 Write
When this line is active along with controller select, one of two write only registers will be
written to from the data bus. See Table 1 and Figure
4.
4.6 Data Bus 0-7
The data bus consists of 8 bit bi-directional tri-state lines with data bus bit 0 being the least
significant bit. See Section 8.0 for an optional configuration.
Table 1. Interface Register Map
READ ONLY REGISTERS WRITE ONLY REGISTERS
-ADDRESS =1 STATUS COMMAND
-ADDRESS =0 RESULT PARAMETER
4

4.7 DMA Request
Ground I 1 I 'l I
I £
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
•
Ground
48
49
50
A nnnr-rat""
J-\U U n c;);)
READ
WRITE
CONTROL SELECT
INTERRUPT
DMA REQUEST
DMA ACKNOWLEDGE
RESET
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
*
*
*
*
*
*
*
*
All signals are negative true.
*See Section 8. 0 for optional configuration.
Figure 3. Pin Assignments for Host CPU I/O (J6)
After a data transfer command has been received and data is ready to be transferred, the
controller will make this line active to request a memory
cyde. Refer to Figure 5 (DMA
timing), See Section 8.0 for optional configuration.
4.8 DMA Acknowledge
This signal is made active by the host CPU to indicate that a memory cycle has been granted,
and
that data is either present on the data bus or data has been written into memory from
the data bus. The data bus
is active during acknowledge for either a read or write operation.
Refer
to Figure 5 (DMA timing). See Section 8.0 for optional configuration.
4.9 Interrupt
This signal is made active by the controller to indicate that an operation has terminated and
it
is in need of service for presenting the ending result byte. The interrupt is reset when the
result register
is read. All commands end with an interrupt.
5

CONTROL SELECT- \ /
Ij IIII ~l!j!IJIJ /III !II! \ ~~j P. m !/!/IIJl(//J11I11!/ /IJ/ !!If//;
I I I
\ /~I--
j.-10 NS MIN.
ADDRESS
READ
~~~~~~~~~~~~~~~~~~~~~~
DATA BUS *
CONTROL SELECT \ /
ADDRESS
71 (//II fJ!/HfJJ/ / /II ///';:y ~ qp 7!) /I I/IJ/ mp;; 1/1/1 I /I !//
WRITE ONS I I L A I
MIN.~ --.\ F-15 NS MIN. j.-10 NS MIN.
DATA BUS*
Figure 4. Host CPU Control Interface Timing
5.0 HOST CPU INTERFACE REGISTER DESCRIPTION
There are four registers in the controller (shown in Table I) that provide the control func-
tions. They are the command, parameter, status, and result registers. These registers are
available
on the data bus when the associated read, write, and address lines are activated
(see Figure 4).
5.1 Command Register
This is a 8 bit write only register that when loaded signifies the beginning of a command
sequence. This register may
not be reloaded until a result has been presented to the host
CPU. Table 2 lists the commands executed by the controller and their binary bit patterns.
Section 6.0 describes each command in detail.
5.2 Parameter Register
All commands issued to the controller require additional data to be executable. The param-
eter register
is a 8 bit write only register that serves to transfer the parameter data to the
controller. Table 2 lists the number
of parameter bytes required for each command and
Table 3 describes the usage for each
of the four possible parameters.
Commands will not be executed until the last parameter byte has been transferred.
6

nl\JI~ Q~()II~CT
_,WI" .,L-,"""VL-Vl
~ I
._------,
\
\
DMA ACKNOWLEDGE
--I' 70 NS MI~.:_J~:::- _ ___r-~_:_i __ L_~_~_~~S
READ (OPTIONAL)*
DATA BUS
DMA REQUEST
DMA ACKNOWLEDGE
WRITE (OPTIONAL)*
70NS iAX;O NS MAX.
4 (RJUMPER
REMOVED)*
\"----1\ ___ ~-=-1_~
~ 70NSMIN. ~ -.j
---'-5-NS-M-'-N-. -.~I----~D=------- 7
40 NS
MIN.
40 NS
MIN.
(R JUMPER
REMOVED)*
\----
I
I 280 NS
/---(MIN.)
,..,..,..,..,..,..,...,..,...,..,..,..,a.,-,...,....
DATA BUS
55 NS MIN. --I
(W JUMPER
REMOVED)*
*Refer to Section 8.0 for Optional Configurations.
Figure 5. Host CPU DMA Interface Timing
5.3 Status Register
55 NS
. MIN.
1---55 NS
MIN.
(W JUMPER
REMOVED)*
The status register provides the means for control information to be passed between the
host CPU and the controller. Contents of the status register is not valid during DMA transfer.
The status register bit assignment is
as follows:
5.3.1 Command Busy and Command Reg Full
When the Host CPU sets a command into the command register, both the command full and
command busy bits will be set. When the controller reads the command and begins execu-
tion, it will reset the command register full bit. During execution, the command busy bit
remains set. The controller will then set interrupt
at the completion of the command
sequence and reset command busy after the result register has been read. The exception to
this rule is the seek command where command busy
is reset when the seek is implemented
so that overlapped seeks may be performed.
5.3.2 Parameter Reg Full
When the Host CPU loads a byte into the parameter register this bit \vill be set. The con-
troller will reset this bit after the parameter register has been read, at which time the Host
CPU may send the next parameter byte.
7

Table 2. Command Code Chart
MSB
BIT LSB #
7 6 5 4 3 2 1 0 Parameter
1
Read ID
X 0 1 0 0 0 0 0 1
I.
2.
Read Diagnostic X 0 0 0 0 0 0 1 3
3.
Verify Data X X X 0 0 0 0 3-4
4.
Verify Data and Special X X X 0 0 0 1 1 3-4
5.
Seek
X 0 0 0 0 0 0 2
6. Recalibrate 0 0 0 0 0 0 1
7.
Terminating Sector Request 0 0 0 0 0 1 1 1 1
8.
Read Data X X X 0 0 0 0 3-4
9.
Read Data and Special X X X 0 0 0 1 3-4
10. Search Data Equal X X X 0 0 0 3-4
11. Search Data Equal and Special X X X 0 0 1 3-4
12. Search High
or Equal X X X 0 0 0 3-4
13. Search High
or Equal and Special X X X 0 0 1 3-4
14. Search
Low or Equal X X X 0 '1 0 3-4
15. Search
Low or Equal and Special X X X 0 1 1 1 3-4
16. Write ID 0 0 0 0 0 0 0 3
17. Format Cylinder 0 0 0 0 0 0 1 2
18.
Initialize
0 0 0 0 0 1 0 3 (SPECIAL)
19. Write Data X X X 0 0 0 3-4
20. Write Special Data X X X 0 0 1 3-4
21. Write
Buffer
a x I 0 0 3-4
Inhibits Retry When set~ I
Multiple Sector Gp. When Set -----l ~
Inhibits Imbedded Seek When Set
5.3.3 Result Reg Full
This bit is set at the completion of a command sequence to indicate that the Host CPU
must read the result register. This bit is reset when the result register is read by the Host
CPU. The result register is only valid when this bit is set.
5.3.4 Interrupt
The controller will set this bit when it requires service. This bit will also activate the inter-
rupt line (Figure 3). The interrupt bit and line will be reset when the result register is read
by the Host CPU.
5.4 Result Register
The result is loaded after the completion of a command sequence. Its content indicates any
abnormal occurance during
the execution of the command. Certain commands may be
retried
if an error occurs (see Section 11.0). If a retry was successful, only the good com-
pletion result will be sent. However,
if after 2 retries (3 attempts including the initial
execution)
the error still exists, the error result is sent. See Table 5 for the result byte
configuration.
8

9
7 6 5
7 6 5
I
7 6 5
L'
Not Used
7
I 6
LSB
o
5
4
4
4
4
Table 3. Parameter Description
Bit
3 2 1 0
L:'
I • Drive Address: Drive 0-3 are
fixed disks,
4- 7 are floppy disks..
Not Used
Head Address: Bit 4
is the second side
for 2 sided
floppy's.
Fixed Head: The head address is interpreted
as the fixed head address.
3 2 0
I •
Cylinder Address
3 2 0
I
.. Starting Sector Address
3 2 0
c=:.
I r
Multiple Sector Count
Table 4. Status Register Map
2 3 4 5 6
MSB
7
LLLNotUsed
Not Used
Not Used
L-- __ Interrupt
'----- Result Reg Full
Parameter Reg Full
Command Reg Full
'---- Command Busy

5.4.1 Result Byte Description
There are four types of result bytes that are further broken down to give more specific
information. These are shown by the completion codes (bits
6, 5, and 4 respectively). Refer
to Table 5.
5.4.1.1 Good Completion (Completion Type 00)
000 -Command completed without error.
001 Srch Not Met -The specified argument and the specified sector(s) did not
satisfy the search command.
010 Srch Met Equal- The argument and the sector contents are identical where specified.
011 Srch Met High or Low -The unequal search was satisfied.
100 thru III -Seek complete -Result byte issued after a seek command is complete
and drive
is ready to read or write.
5.4.1.2 Sub-System Error (Completion Type 01)
This type of error indicates an error occurred in the drive or control unit.
000 -Seek Error -Posted only for imbedded seeks when the control unit cylinder or
head register does
not match the cylinder or head address read off the disk in
the
ID field of a sector. The control unit will re-calibrate and re-seek the head
arm if retry is not inhibited before posting this result.
001 - CRC Error ID Field -The control unit detected a CRC error in an ID field.
Comp
Code
Table 5. Result Register Map
Result Reg
MSB 7 ---- Not Used
4
65
J,----
r- Completion Code
. Completion Type
3
2
]f----
---- Speciai Data Found
LSB
o ---- Defective ID Found
Completion
Type
letion
000
001
010
011
100
101
110
111
Good Sub-System Operator Command
00 Completion
01
Error
10 Intervention
11
Error
Good Completion Seek Error* Drive Not Ready Illegal Length
Srch Not Met CRC
Error I D* Write Protection Check Record Not
Field
(floppy only)
Found*
Srch Met Equal CRC
Error*
Restore Error
Invalid Command
Data Field
Srch Met High Sector
Error Write Fault
Late DMA
or Levv
Seek Complete ID Sync
Err*
Drive 1
Seek Complete Data Sync Err*
Drive 2
Seek Complete
Drive 3
Seek Complete
Drive 4
*With inhibit retry bit in command not set these error conditions are retried 2 times before
result
is sent. With seek inhibit set in the command these errors will not be retried.
10

010 -CRC Error Data Field -The controller was unable to read the data field. If
retry is inhibited this result will be sent after the DMA transfer of the data in
error has been sent. When
retry is enabled the controller will attempt to read
the
data twice and if this is not successful the result will be posted before any
DMA transfer of data takes place.
all -Sector Error -The controller has determined that the time between sectors
does
not agree with the maximum sector code sent in the initialize command.
100 -ID Sync Error - The controller was unable to find the sync byte for an ID
field within a 4
byte tolerance.
101 -Data Sync Error -The controller was unable to find the sync byte for a data
field within a 4 byte tolerance.
5.4.1.3 Operator Intervention (Completion Type 10)
This type of error cannot be resolved without outside help.
100 -Drive Not Ready -The ready line from the disk is not active after the drive is
selected.
101 -Write Protection Check -This error can only occur on a floppy disk write
operation when the diskette is write protected.
110 -Restore Error -While stepping the maximum number of cylinders during a
recal
command the controller was unable to detect track 00 line active.
111 -Write Fault -The write fault line was active at the end of a write operation.
The controller will reset the write fault
at the beginning of a new command.
5.4.1.4 Command Error (Completion Type 11)
This type of result is sent when the control unit cannot execute the command as specified.
000 -Illegal Length -The parameters for the command exceed the maximum
cylinder, head or sector capacity of the drive as specified by the initialize
command for that drive.
00 1 - Record Not Found -The specified sector did not occur in any of the ID fields
read from the track. Cylinder and head numbers did match.
a 10 -Invalid
Command -The command code is undefined.
all -Late DMA -Can only occur on ::l write operation where the host DMA has not
supplied a byte of data before it was required. The data field does not contain
the desired
data and should be re-written.
6.0 COMMAND DESCRIPTION
The commands are organized into three groups: (1) control, (2) read/write and (3) control
read/write. There are three optional bits set with the certain command codes: Inhibit retry,
multiple sector and inhibit
imbedded seek. Refer to table 2. If retry is inhibited, controller
will
only try operation for one revolution, instead of three. If imbedded seek is inhibited,
the
controller will not accept a new head address, but will use the head address from the
previous command.
6.1 Control Commands
6.1.1 Initialize
The initialize command is used by the system to specify to the controller what the physical
characteristics
of the drives are at each address. This command has different parameters
than those used for all other commands. They are listed in table 6.
11

Table 6. Initialize Parameter Map
Parameter #1 7 6 5 4 3 2 0
I I I I Drive Address
I I Number
of Moveable Heads
Set When Fixed Heads are Installed
Parameter #2 7 6 5 4 3 2 0
I I I I Maximum Cylinder Code
o = 202 (fixed disk)
77
(floppy disk)
1 = Future Use
Maximum Sector Code
o = 128 bytes
1 = 256 bytes
2 = 512 bytes
3 = Floppy Format
Parameter
#3
7 6 5 4 3 2 0
I I Sector Interleave Code
(See Table 7)
The initialize command must be issued to each drive attached to the controller after a power
on
or a reset. The sector interleave code is specified by this command and is discussed in
Section 6.1.1.1. The sector interleave codes allow for slow DMA transfer
of data to take
place
without waiting for a complete revolution of the disk on a multiple sector operation.
Care should be taken to insure that the code issued for the initialize command matches that
on the disk when a reformat of disk is not going to be done.
6.1.1.1 Sector Interleave Code
A sector interleave code
must be specified during an initialize command allowing for mul-
tiple sector reads
or writes to occur without having to wait one revolution of the disk for
each sector transfer. Sequential sector transfers are
not possible due to timing limitations
of the controller firmware:
The sector interleave code specifies
the spacing between logical sectors. The following
example shows an interleave code
of 7 with a 32 sector format:
Physical Sector: 0 1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27 28 29 30 31
Logical Sector: 0 7 14 21 28 1 8 15 22 29 2 9 16 23 30 3 10 17
24 31 24 31 4 11 18 25 5 12 19 26 6 13 20 27
Note
that this interleave code has 4 sectors between consecutive sectors at the beginning of
the track but only 3 toward the end. This example is given to show that the interleave code
must be chosen carefully.
Several codes for each sector size
option that give a constant number of interleaved sectors
are shown in
the following table:
12

Table 7. Interleave Code
Sectors/Track Interleave Code Interleave
32
16
32
11 2
32
8 3
60 30
60
20 2
60 15
3
60 12 4
104
52
1
104
35 2
104
26 3
104
21 4
6.1.2 Recalibrate
A recalibrate will step the head arm towards track
00 until the drive sends the track 00
indication. After each step the controller waits for seek complete. This is different than a
seek
to zero in that the controller does not calculate and then issue the required number of
step pUlses. The controller will reset its cylinder register with this command. An interrupt
is set upon completion of a recalibrate.
6.1.3 Seek
A seek command will move the head arm assembly the required
number of cylinders to
position over the addressed track and select the desired head. A seek command will not
read an ID field to verify operation, however, track 00 switch is monitored for errors.
After issuing a seek
on a fixed disk drive the controller will drop command busy and is free
to accept a command
to another drive. An interrupt is set upon completion of the seek with
a seek complete result byte. Note
that command busy bit is not set with this interrupt.
6.1.4 Terminating Sector Request
This command is valid after a read, write, search
Of verify uata command. There are seven
bytes DMA transferred
to the CPU memory. The first three bytes are the cylinder, head and
sector for the last sector
the controller operated on. If an error occurred that was associated
with
the ID field for that sector, the last four bytes transferred are the flag, cylinder, head
and sector
bytes read from the disk. Note that the last four bytes are only valid after a
defective ID found, an ID CRC error,
or a seek error.
The first three bytes are used
to determine:
A) At what sector a search was met.
B) At what sector an error occurred on a multiple sector command.
Mter DMA is complete an interrupt is sent and a good completion result is set.
6.2 ReadIWrite Commands
Read and write commands transfer data
to or from CPU memory via DMA transfer. A full
sector buffer (512 bytes)
is used in the controller to avoid data overruns. Two CRC bytes
with a generator polynomial
of X16 + X12 +XS + 1 are appended to all records on the track
for error detection.
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All read/write commands, unless otherwise specified, will perform a seek to the specified
cylinder and head and search for the desired sector before attempting
to read or write the
data field. Any errors encountered during this procedure cause a retry (maximum
of two)
before the error
is posted. Retry may be inhibited with a bit in the command code. Read/
write operations may be single or multiple sector transfers. An interrupt
is set after DMA
transfer is complete.
6.2.1 Format Cylinder
A seek to the specified cylinder will be performed by the controller and the ID fields
written according to the interleave code specified in the initialize command. All heads in
that cylinder are formatted. Data fields are
not written. With the fixed head bit set all
fixed heads are formatted.
6.2.2 Write ID
A write ID command will orient to the field specified in the parameters according to the
interleave code and write the ID field with the
DMA data. The data field will not be changed.
For the fixed disk drives, a flag, cylinder, head and sector byte must be transferred. See
Section 10.0 for flag byte definition. For a floppy disk four bytes are required; cylinder,
head, sector, and a record size byte. Refer
to Section 10.0 track formats. An interrupt is
set when command is complete.
6.2.3 Write Data
This command will write the data field of the length specified in the initialize command.
Data transfer from memory will begin filling the sector buffer before the sector
is under the
read/write head and
DMA overrun will be checked during the write operation.
6.2.4 Write Data Special
This command operates the same as a write data except a unique address mark is written at
the beginning of the data field.
6.2.5 Read ID
A Read ID will transfer the first ID field encountered back to the CPU. This command will
not perform an imbedded seek. This command
is intended as a diagnostic and for alternate
sector assignment.
6.2.6 Read Data
The specified data is DMA transferred to memory. If a special sync byte is encountered, no
data for
that sector is transferred and the special data found bit is set in the result. After
DMA transfer is complete for all sectors an interrupt is sent and result reg full is set.
See Section 11.0 for retry conditions.
6.2.7 Read Data and Special
This command operates the same as a write data except a special sync byte is written at the
beginning
of the data field
6.2.8 Search Data Equal
This command will read the specified sector(s) and compare this data with the data in
memory. Once the data in memory
is DMA transferred to the sector buffer no further
transfer
is required. Any hex 'FF' byte will not be compared; all others will be compared
for equivalence. Special data fields will be ignored.
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6,2,9 Search Data Equa! and Special
Special data will also be compared.
6.2.10 Search Data High or Equal
A comparison where data on the disk is of greater binary value or equal to that in memory
will satisfy this search.
6.2.11 Search Data High or Equal and Special
Special data will also be compared.
6.2.12 Search Data Low or Equal
This search is satisfied if data on the disk is of lower binary value or equal to data in
memory.
6.2.13 Search Data Low or Equal and Special
Special data is included in the search.
6.2.14 Verify Data
No DMA transfer of data will occur, however, data will be read into the sector buffer and
the CRC checked for errors.
6.3 Control Read/Write
6.3.1
Read Diagnostic
This command is used when an ID field is unreadable. When issued the controller will orient
to
the specified track and sector then skip over the ID field, and transfer the data field to
memory.
6.3.2 Write Buffer
This command provides the system with the capability to copy a sector on one drive to an
equal length sector
on the same or different drive without transferring data through
memory. The sector address specified in this command will be a physical sector address.
The write buffer command writes the present contents of the sector buffer to the sPecified
sector. The sector buffer may be filled with a read data, write data or verify data command.
7.0 COMMAND PROCEDURE
The controller operates on one command at a time except in the case of a seek
where all 4 drives may be seeking. In general
the following description gives the
sequence of events for a command. The controller is designed to be used with DMA logic
located
at the CPU.
A) The CPU sets up its DMA logic for the transfer of data if the command calls for it.
B) The CPU then checks the status reg for a zero condition and initiates the command,
the controller in
turn sets the command full and busy bits in the status register.
C) The controller will read the command and reset the command full bit.
D) The CPU will then send the required number of parameters for the particular com-
mand. Each time a parameter
is sent, the parameter full bit in the status is set. After
the controller reads the parameter
it will reset this bit.
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