Shugart SA4600 User manual

SA4600 ©
Fixed Disk Controller I
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SA4600 ©
Fixed Disk Controller I
Copyright 1979 Shugart Associates
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Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
Introduction . . . .
Specification Summary
SA4000 Drive Interface Description
Host
CPU Interface Description
4.1 Reset.....
4.2 Controller Select .
4.3 Address
4.4
Read ...
4.5 Write...
4.6 Data Bus 0-7 .
4.7
DMA Request .
4.8
DMA Acknowledge .
4.9
Interrupt.....
Host CPU Interface Register Description.
5.1 Command Register . . . . .
5.2 Parameter Register . . . . .
5.3 Status Register. . . . . . .
5.3.1 Command Busy and Command
Reg Full. .
5.3.2 Parameter
Reg Full
5.3.3 Result Reg Full . . .
5.3.4
Interrupt......
5.4 Result Register. . . .
5.4.1 Result Byte Description
5.4.1.1 Good Completion. . . .
5.4.1.2 Sub System Error. . .
5.4.1.3 Operator Intervention .
5.4.1.4 Command Erroi . .
Command Description. . . . .
6.1 Control Commands. .
6.1.1 Initialize ..... .
6.1.1.1 Sector Interleave Code.
6.1.2 Recalibrate.....
6.1.3 Seek........
6.1.4 Terminating Sector Request. .
6.2 ReadlWrite Commands
6.2.1 Format Cylinder .
6.2.2
WriteID ....
6.2.3 Write Data . . . .
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
VVrite Data Special
Read ID ....
Read Data . . .
Read Data and Special.
Search Data Equal . .
Search Data Equal and Special.
Search Data High or Equal . .
Search Data High or Equal and Special.
Search Data Low or Equal . . . . .
Search Data Low or Equal and Special.
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Table of Contents
7.0
8.0
9.0
10.0
11.0
12.0
6.2.14
6.3
6.3.1
6.3.2
Verify
Data. . . .
Control Read/Write. .
Read Diagnostic
Write
Buffer.
Command Procedure . .
Optional Host CPU Interface Configurations
8.1 Rand WJumper Description .
8.2
RQ and A Jumper Description.
8.3 F Jumper Description .
SA4000 Drive Option Description
9. 1 Control PCB. . . . . .
9.1.1 Drive Select. . . . .
9.1.2 Byte Clock/Sector Mark
9.1.3
Miscellaneous....
9.1.4 Sector Counter Options
9. 1.5 Cable Termination Description
9.2
Data Separator PCB. .
Format Description. .
Error Retry. . . .
Physical Description.
12.1 PC Board.
12.2 Connectors
12.2.1 50
Pin Connectors
12.2.2 20
Pin Connectors
12.2.3 Power Connector.
Appendix A -
General Microcode Flowchart.
Appendix B - Schematics . . . . . . . .
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List of Illustrations
1.
2.
3.
4.
5.
6.
7.
7.1
8.
9.
10.
11.
12.
SA4600 Interface Block Diagram. . . .
Pin Assignments
for J1 and J2 Thru J5
Pin Assignments for Host CPU I/O (J6)
Host
CPU Control Interface Timing. . .
Host
CPU DMA Interface Timing. . .
Optional Host CPU Interface Connection
RQ Jumper Option Timing (Read Mode) .
A Jumper
Option Timing (Write Mode)
SA4600 Format . . . . . .
P.C.B. Physical
Layout Drawing .
50 Pin Connector Drawing ....
20 Pin Connector Drawing
DC Connector Drawing .
List of Tables
1.
2.
3.
4.
5.
6.
7.
8.
Interface Register Map. .
Command Code Chart .
Parameter
Description.
Status Register Map. .
Resu It Register Map. .
Initialize Parameter Map .
Interleave Code . . .
Sector Counter Options .
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7
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iii

1.0 INTRODUCTION
The SA4600 Disk Controller is a complete preprogrammed microprocessor based controller
for the Shugart SA4000 series disk drives and SA800/8S0 Floppy Disk Drive.
The SA4600 Disk Controller is designed to perform asyncronous
data transfers between the
SA4000 and a host CPU.
The SA4600 features a general purpose DMA type interface designed to easily adapt to com-
mercially available DMA controller chips.
Several optional configurations also make this interface adaptable to virtually any
type of
mini or micro computer. Some main features of this controller are as follows:
A) Control of one to four SA4000 drives and one to four SA800/8S0 Floppy Disk Drives.
B) Asyncronous DMA transfer with full sector buffering.
C) Four user selectable formats -32 sectors of S12 bytes, 60 sectors of 2S6 bytes, 104
sectors of 128 bytes, or 26 sectors of 2S6 bytes (Floppy option only).
D) Overlap seek operation (up to four drives).
E) Single five volt supply.
2.0 SPECIFICATION SUMMARY
Environmental Limits
Ambient temperature =
O°C to SO°C
= 20% to 80%
Relative humidity
OC Voltage Requirements
+S VDC ± S% 7.0A typical 7.S maximum (with floppy option)
Heat Disipation = 120 BTU/hr. typical
Mechanical Dimensions (reference Figure 8)
Length = 18" (4S.72cm)
Width =
l2.S" (31.7Scm)
Height = 1" (2.S4cm)
3.0 SA4000 DRIVE INTERFACE DESCRIPTION (Reference Figure 1)
The SA4000 drives are interfaced through connectors Jl, J2, J3, J4 and JS.
Jl is a SO pin ribbon cable type edge connector which connects the SA4000 drives in a daisy
chain configuration. Up
to four drives may be bussed together on this cable. This cable
should
not exceed 20 feet (6 meters). Refer to section 9.l.S -Cable Termination
Description.
J2 through JS are 20 pin ribbon cable type edge connectors which are the radial connectors
for
up to four drives. J2 is the radial connector for Drive 1. J3 is the radial connector for
Drive
2, etc. These cables should not exceed 20 feet (6 meters). Refer to Figure 2 for a
diagram
of the pinouts for J1 and J2 through JS.
Refer
to section 12.2 for Connector Physical Description.
2

HOST CPU
CONTROL
HOST CPU
DATA
J6
50 PIN
SA4600
J6
50 PIN
Jl
50 PIN
J2
20 PIN
J3
20 PIN
J4
20 PIN
J5
20 PIN
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Figure 1. SA4600 Interface Block Diagram
4.0 HOST CPU INTERFACE DESCRIPTIOr\l
Jl
SA4000
DRIVE 1
J2
Jl
SA4000
DRIVE 2
J2
Jl
SA4000
DRIVE 3
J2
Jl
SA4000
DRIVE 4
J2
The SA4600 host CPU interface is a general purpose DMA type interface which is accom-
plished
through connector J6. J6 is a 50 pin ribbon type cable edge connector. Refer to
Figure 3 for pin assignments. All signals to the CPU interface are TTL negative true, 48MA.
This cable should
not exceed 10 feet (3 meters).
A description of the CPU interface lines follows:
4.1 Reset
This line will cause the controller
to cease all operation, clear local ram memory, reset the
command, status, and result registers, and go into a normal wait loop. A reset during a write
operation may cause improper data to be written. The RESET pulse width must be at least
200 nanoseconds. The SA4600 will not accept a command for 3 milliseconds after a reset.
The
host CPU must time out for 3 ms.
4.2 Controller Select
This signal functions as a device select and should only be active when one of the four
registers in the controller are
to be operated on.
4.3 Address
The address line selects which register will be read/written. See Table
1.
3

J1
Ground 1 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Ground 49 50
4.4 Read
-Head Select 1
-Head Select 2
-Head Select 4
-Head Select 8
-Index
-Ready
-Sector Mark
-Drive Select 1
-Drive Select 2
-Drive Select 3
-Drive Select 4
-Direction
-Step
-Fault Clear
-Write Gate
-Track 00
-Write Fault
-Read Gate
!\I/C
NIC
-Index
-Ready
-Byte Clk Sector
-Seek Complete
+WRT Data
Ground
-Write Clock
+PLO Clock
Ground
-Read Data
Figure 2.
Pin Assignments for J1 and J2 Thru J5
J2 -J5
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
Ground
Ground
Ground
Ground
-WRT Data
+WRT Clock
Ground
-PLO Clock
+Read Data
Ground
When this line is active along with controller select, one of two read only registers will be
read onto the data bus. See Table 1 and host interface timing, Figure
4.
4.5 Write
When this line is active along with controller select, one of two write only registers will be
written to from the data bus. See Table 1 and Figure
4.
4.6 Data Bus 0-7
The data bus consists of 8 bit bi-directional tri-state lines with data bus bit 0 being the least
significant bit. See Section 8.0 for an optional configuration.
Table 1. Interface Register Map
READ ONLY REGISTERS WRITE ONLY REGISTERS
-ADDRESS =1 STATUS COMMAND
-ADDRESS =0 RESULT PARAMETER
4

4.7 DMA Request
Ground I 1 I 'l I
I £
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
•
Ground
48
49
50
A nnnr-rat""
J-\U U n c;);)
READ
WRITE
CONTROL SELECT
INTERRUPT
DMA REQUEST
DMA ACKNOWLEDGE
RESET
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
*
*
*
*
*
*
*
*
All signals are negative true.
*See Section 8. 0 for optional configuration.
Figure 3. Pin Assignments for Host CPU I/O (J6)
After a data transfer command has been received and data is ready to be transferred, the
controller will make this line active to request a memory
cyde. Refer to Figure 5 (DMA
timing), See Section 8.0 for optional configuration.
4.8 DMA Acknowledge
This signal is made active by the host CPU to indicate that a memory cycle has been granted,
and
that data is either present on the data bus or data has been written into memory from
the data bus. The data bus
is active during acknowledge for either a read or write operation.
Refer
to Figure 5 (DMA timing). See Section 8.0 for optional configuration.
4.9 Interrupt
This signal is made active by the controller to indicate that an operation has terminated and
it
is in need of service for presenting the ending result byte. The interrupt is reset when the
result register
is read. All commands end with an interrupt.
5