Silicon Laboratories CP2114 Series User manual

Rev. 0.1 10/12 Copyright © 2012 by Silicon Laboratories CP2114-EK
CP2114-EK
CP2114 EVALUATION KIT USER’SGUIDE
1. Kit Contents
The CP2114 Evaluation Kit is available in four configurations shown in Table 1:
This document applies to all CP2114 kits.
2. Software Setup
The example applications as well as additional documentation can be found here: www.silabs.com/CP2114
AN721 Software (AN721SW)
USB and GPIO configuration utility: See AN721 for more information on customizing USB and GPIO settings.
Audio (DAC/CODEC) configuration utility: See Section 4 for more information using the DAC Configuration utility.
CP2114 Data Sheet
CP2114 Evaluation Kit User's Guide
AN433: CP2110/4 HID-to-UART API Specification
AN434: CP2110/4 Interface Specification
CP2114 Quick Start Guide
Table 1. Evaluation Kits
Kit Name Components
CP2114-EK CP2114 evaluation board
USB cable
RS-232 serial cable
CP2114-CS42L55EK CP2114 evaluation board
Daughter card with Cirrus Logic CS42L55 CODEC
Ear bud headphones
Audio cable (3.5 mm male to male)
USB Cable
RS-232 serial cable
CP2114-WM8523EK CP2114 evaluation board
Daughter card with Wolfson Microelectronics WM8523 DAC
Ear bud headphones
USB Cable
RS-232 serial cable
CP2114-PCM1774EK CP2114 evaluation board
Daughter card with Texas Instruments PCM1774 DAC
Ear bud headphones
USB Cable
RS-232 serial cable
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CP2114-EK
2 Rev. 0.1
3. CP2114 Hardware Interface
For information on using the CP2114, see the CP2114 Quick Start Guide, available at www.silabs.com/CP2114.
Figure 1, Figure 2, Figure 3, and Figure 4 show each evaluation board as well as important features.
Figure 1. CP2114 Evaluation Board Features
Daughter
Card
Connector
Microphone Input
Path
Volume Control
Buttons
TX and RX
Toggle LEDs
USB
Connector
DAC Select
Jumpers USB Active
and Suspend
LEDs
RS-232
Connector
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CP2114-EK
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Figure 2. CS42L55 Daughter Card Features
Figure 3. WM8523 Daughter Card Features
Headphone
Out
Connector Daughter
Card
Connector
Analog
Input
Connector
Line Out
Connector
CS42L55
Codec
Headphone
Out
Connector Daughter
Card
Connector
Line Out
Connector
WM8523
DAC
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CP2114-EK
4 Rev. 0.1
Figure 4. PCM1774 Daughter Card Features
Headphone/
Line Out
Connector
Daughter
Card
Connector
Analog
Input
Connector
PCM1774
DAC
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4. DAC Configuration Application (AN721SW)
The DAC Configuration utility is an application within the AN721 software (AN721SW) package that allows audio
configuration strings to be sent to the CP2114 one-time programmable memory or RAM. The audio string is used
by the CP2114 to configure the DAC/CODEC. To access the DAC Configuration utility, run the AN721SW and
connect to the CP2114 device.
After connecting to the device, select Advanced Configuration, then DAC Configuration. After this, the DAC
Configuration utility shown in Figure 5 will appear. This AN721SW package is available at www.silabs.com/CP2114.
Figure 5. AN721: DAC Configuration
4.1. Application Command Descriptions
4.1.1. Get CP2114 Capabilities
This button will report the current configuration of the one-time programmable memory. With the default pin
configuration and no jumpers installed on GPIO.5, GPIO.6, GPIO.7, or GPIO.8, the utility will display the following:
* CP2114 Caps
AvailableBootIndices: 0x20
AvailableOtpConfigs: 0x1D
CurrentBootConfig: 0xFF
AvailableOtpConfigSpace: 0x1532
The AvailableBootIndices: 0x20 parameter indicates that all 32 boot index slots are available for programming.
The AvailableOtpConfigs: 0x1D parameter indicates that there are 29 CP2114 configurations available in the
one-time programmable memory.
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The CP2114 EVB ships with three default configurations in OTP at the following indices:
Index 0: Audio out and audio in streams both set to Asynchronous with CS42L55 DAC settings.
Index 1: Audio out and audio in streams both set to Asynchronous with WM8523 DAC settings.
Index 2: Audio out and audio in streams both set to Asynchronous with PCM1774 DAC settings.
The CurrentBootConfig parameter with a value of 0xFF indicates the CP2114 will not configure any DAC devices
on a reset or boot.This occurs when
DAC select input feature is turned on and no jumpers are installed on GPIO.5, GPIO.6, GPIO.7, and
GPIO.8.
DAC select input feature is turned on and the GPIO value is set to “Use OTP Boot Config” while no valid
boot config entry is found in the one-time programmable memory.
DAC select input feature is turned off and there is no valid Boot Config entry in the one-time programmable
memory.
The CP2114 has 32 programmable boot configuration entries by default. (The CP2114 boot configuration can be
changed up to a total of 32 times.)
The final parameter, AvailableOtPConfigSpace: 0x1532 indicates there are 0x1532 (5426) bytes of
programmable memory available to support new configurations.
4.1.2. Reset Device
This button forces a CP2114 reset.
4.1.3. Load Config Text from File
Loads configuration text from a file into the Config Text window.
4.1.4. Save Config Text to File
Saves the text in the Config Text window to a file.
4.1.5. Write Config Text to RAM
Writes the configuration displayed in the Config Text window into the CP2114 RAM. The DAC configurations are
also written to the DAC. This operation will cause the CP2114 to disconnect and reconnect on the USB bus. This
configuration is not retained on device reset.
4.1.6. Write Config Text to OTP
Writes the configuration in the Config Text window to the one-time programmable memory. The configuration does
not become the active configuration in RAM unless it’s specified in CP2114 Boot Config or via DAC select GPIO
pins followed by power cycling or resetting the device.
4.1.7. Read CP2114 Config from OTP
After specifying the configuration number in the text box to the right of the button and clicking the button, the utility
will display the one-time programmable memory configuration in the output window.
4.1.8. Set CP2114 Boot Config
After specifying the configuration number in the text box to the right of the button and clicking the button, the boot
configuration index is programmed into the one-time programmable memory space.
Note: The CP2114 boot configuration index can be changed up to 32 times.
4.1.9. Get DAC Registers
Displays one or more DAC registers in the output window. To display a contiguous range of DAC registers enter the
starting register address in the Start Address field and the number of registers to read in the Num Registers field.
Click Get DAC Registers and the register values will be displayed in the status window as hex comma-separated
values.
4.1.10. Save Final Device Customization to File
Save the final 5.5 kB of customized data into a file for one-time programming in production.
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4.2. Using the Application
Use the following steps to program the CP2114 using the DAC configuration utility:
1. Click Get CP2114 Capabilities and note the boot index, available OTP boot index slots, and available OTP
config space.
2. Click Load Config Text from File if there is one available; otherwise write the config text into the Config
Text window directly.
3. Click Write Config Text to RAM. This will cause CP2114 to re-enumerate over USB. Once CP2114 device
is seen by the Host again, verify the device's audio functionalities including volume control and mute
control. Adjust the value in Config Text if necessary and repeat Write Config Text to RAM until desired
result is achieved.
4. Verify the DAC registers have the desired setting by entering the Start Address and Num Registers and
clicking Get DAC Registers.
5. Click Save Config Text to File to save a copy of the text in the Config Text window.
6. Click Write Config Text to OTP after all functionalities have been completely verified in RAM. The new
config will consume one Boot Config index slot and some one-time programmable config space. The index
of this new config should be the next available index. For example, if Get CP2114 Capabilities returned
AvailableOtpConfigs of 0x1D, this Configuration index will be 3.
7. Enter the index of the new config and click Read CP2114 Config from OTP. Verify the data returned is as
expected.
8. Click Get CP2114 Capabilities and verify the available OTP config space is (2+Config Data bytes) less
than the previous value. The firmware inserts 2-byte length before the Config Data when writing to OTP.
Available OTP Configs should be 1 less than the previous value.
9. Enter the Configuration index of the new Config and click Set CP2114 Boot Config to make CP2114 to
boot from the new Config.
10. Reset the CP2114.
11. Verify CP2114 boots up properly with DAC functioning properly. Verify volume and mute integration with
the Host. Click Save Final Device Configuration to File for OTP programming in production.
4.3. Audio Configuration String Format
The audio configuration string input format is comma or space-separated hex values (a combination of comma and
space separation is not allowed).The CP2114 data sheet available at www.silabs.com/CP2114 discusses the audio
configuration string in detail.
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5. Evaluation Board Overview
5.1. CP2114-EB Overview
The CP2114 Evaluation Kit includes an evaluation board with a CP2114 device pre-installed for user evaluation and
software development. Numerous input/output (I/O) connections are provided to facilitate prototyping using the eval-
uation board. Refer to
Figure 6 for the locations of the various I/O connectors.
J1 Daughter card connector
J2 USB connector for USB interface
J3 DB9 connector for RS-232 interface
JP00-JP30 CP2114 pin connector
JP40 VIO power connector
JP41 REGIN Power Connector and Self-Powered Mode Connector
JP42 Test point connector
JP43 Si500 enable connector
JP44 SCKIN to SCK connector
JP45 DAC selection connector
JP46 Green USB ACTIVE LED connector
JP47 Red USB SUSPEND LED connector
JP48 Daughter card reset connector
JP49 CP2114 GPIO signal header
JP50, JP52 Daughter card GPIO signal header
D2 Red record mute LED
D3 Red receive toggle LED
D4 Red transmit toggle LED
D5 Red USB SUSPEND LED
D6 Green USB ACTIVE LED
SW1-SW4 Audio control buttons
SW5 Reset button
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CP2114-EK
Rev. 0.1 9
Figure 6. CP2114 Evaluation Board with Default Shorting Blocks Installed
5.1.1. Daughter Card Connector (J1)
The J1 connector is used to connect to a CP2114 daughter card.
5.1.2. Universal Serial Bus (USB) Interface (J2)
A Universal Serial Bus (USB) connector (J2) is provided to facilitate connections to the USB interface on the
CP2114. See Table 2 for the USB pin definitions.
Table 2. USB Connector Pin Descriptions
Pin # Description
1 VBUS
2D–
3D+
4 GND (Ground)
J2
J3
D2
VOL +
S2
VOL -
S1
REC MUTE
S4
PB MUTE
S3
CP2114
U1
JP43
D3RXT
D4TXT
RESET
S5
JP41 JP42
JP40
JP10
JP11
JP14
JP15
JP16
JP17
JP12
JP13
JP44 JP00
JP03
JP02
JP01
JP04 JP05 JP06
JP07
JP20
JP21
JP24 JP25 JP26 JP30
JP22 JP23
JP46
JP47
D6
ACTIVE D5
SUSPEND
JP49
JP52 JP50
DAC Select
JP45
www.silabs.com
SILICON LABS
CP2114-EB
JP48
J1
Si500
U3
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5.1.3. UART Signals (J3)
An RS-232 transceiver circuit and DB9 connector (J3) are provided on the evaluation board to connect the CP2114
to external serial devices. See Table 3 for the RS-232 J3 pin descriptions.
5.1.4. CP2114 Pin Connectors (JP00-JP30)
The JP00-JP30 connectors connect and disconnect CP2114 pins from external circuits. By default, all of these
jumpers are populated.
5.1.5. VIO Power Connector (JP40)
This header (JP40) is included on the evaluation board to provide VIO power options. Populating the shorting block
connects the CP2114 VIO input (pin 6) to CP2114 VDD (pin 7). Remove the shorting block to power VIO from an
external source and connect the power source to pin 2 of the header.
5.1.6. REGIN Power Connector and Self-Powered Mode Connector (JP41)
The JP41 header is used to connect the CP2114 REGIN pin (pin 8) to the VBUS source from the USB connector
(default) or to the CP2114 VDD pin (pin 7). When connected to the VBUS source, the device is intended for bus-
powered operation. When connected to the CP2114 VDD pin, the device is intended for self-powered operation. In
self-powered operation, an external power source can be connected to the JP41 header to power the VDD pin
directly.
5.1.7. Test Point Connector (JP42)
The JP42 header contains test points and is not used in normal operation.
5.1.8. Si500 Enable Connector (JP43)
The JP43 header controls the power to the Si500 CMOS clock. Shorting pin 1 to pin 2 on the header will connect
CP2114 VDD (pin 7) to the Si500. Shorting pin 2 to pin 3 on the header will place the Si500 in powerdown mode.
The setting of JP43 depends on the desired clocking mode.
5.1.9. SCK to SCKIN Connector (JP44)
The JP44 jumper should be left installed.
5.1.10. DAC Selection Connector (JP45)
The JP45 header is used to select the CP2114 boot configuration after a reset. When a jumper is populated, the
corresponding GPIO pin in connected to ground. When a jumper is removed, the corresponding GPIO pin is
weakly pulled high.
Note: If any of the four DAC select pins are configured for a function other than DAC selection, the CP2114 will not use the
DAC select pins to choose a boot configuration.
5.1.11. Green USB ACTIVE LED and Connector (JP46, D6)
The JP46 header is used to connect the CP2114 SUSPEND pin (pin 18) to the D6 green LED. When the LED is on,
the device has enumerated with the PC operating normally. When the LED is off, the device has not yet
enumerated or is in the USB Suspend state.
5.1.12. .Red USB SUSPEND LED and Connector (JP47, D5)
Table 3. RS-232 Pin Descriptions
Pin Signal CP2114
Direction Description
2 RXD Input Receive Data
3 TXD Output Transmit Data
5 GND Ground
7 RTS Output Request to Send
8 CTS Input Clear to Send
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The JP47 header is used to connect the CP2114 SUSPEND pin (pin 17) to the D5 red LED. When the LED is on,
the device has enumerated with the PC operating normally. When the LED is off, the device has not yet
enumerated or is in the USB Suspend state.
5.1.13. Daughter Card Reset Connector (JP48)
The JP48 header connects reset to the GPIO4_C pin on the daughter card connector (J1). On the CS42L55
daughter card, GPIO4_C is connected to the CS42L55 RESET pin. The GPIO4_C pin is unconnected on the
WM8523 and PCM1774 daughter cards because the DACs do not have a hardware reset input.
5.1.14. CP2114 GPIO Signal Connector (JP49)
The connector JP49 provides easy access to all of the CP2114 GPIO signals.
5.1.15. Daughter Card Signal Header (JP50, JP52)
The headers JP50 and JP52 allow the connection of GPIO0-4 signals to the corresponding daughter card signals
(GPIOx_C). These jumpers can be used to route the appropriate GPIO signals to a custom daughter card.
5.1.16. Audio Control Buttons and Red Record Mute LED (SW1-SW4, D2)
SW1 through SW4 send audio control commands when pressed. In addition, the red record mute LED (D2) will
turn on when the record mute button is pressed (SW4).
5.1.17. Red Receive Toggle and Transmit Toggle LEDs (D3, D4)
The LEDs D3 and D4 will toggle when transmitting and receiving UART data. In order to use this functionality, the
GPIO pins must first be configured for TX Toggle and RX Toggle modes. By default, these pins are used for DAC
select 0 and DAC select 1.
5.1.18. Reset Button (SW5)
SW5 externally pulls the CP2114 reset pin (pin 10) low when pressed. If SW5 is held down, the CP2114 will remain
in reset until the button is released.
Table 4. Audio Control Buttons
LED Pins
S1 Volume –
S2 Volume +
S3 Playback Mute
S4 Record Mute
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CP2114-EK
12 Rev. 0.1
5.2. CS42L55-EB Overview
The CS42L55 evaluation board contains a pre-installed CS42L55 for evaluation and preliminary software develop-
ment with the CP2114 evaluation board. Refer to
Figure 7 for the locations of the various I/O connectors on the
CS42L55-EB.
P1 Daughter card connector
P2 Analog input connector
P3 Line output connector
P4 Headphone output connector
J1-J5 I2S/I2C signal connectors
J9, J10 I2S/I2C signal connectors
Figure 7. CS42L55 Evaluation Board with Default Shorting Blocks Installed
5.2.1. Daughter Card Connector (P1)
The P1 connector is used to connect to a CP2114 evaluation board (CP2114-EB). The CS42L55-EB must be
plugged into a CP2114 evaluation board to function properly.
5.2.2. Analog Input Connector (P2)
The P2 connector is used to connect an input device to the CS42L55 evaluation board.
5.2.3. Line Output Connector (P3)
The P3 connector is used to connect powered speakers to the CS42L55 evaluation board.
5.2.4. Headphone Output Connector (P4)
The P4 connector is used to connect headphones to the CS42L55 evaluation board.
5.2.5. I2S/I2C Signal Connectors (JP1-JP5, JP9, JP10)
Connectors JP1 through JP7, JP9, and JP10 are provided to allow access to the I2S/I2C signals between the
CP2114 and CS42L55. Placing a shorting block between pins 1 and 2 will connect the CP2114 to the CS42L55.
Placing a shorting block between pins 2 and 3 will connect the corresponding CS42L55 pin to ground. When
monitoring the I2S signals, connect the scope probe ground lead to the adjacent ground pin.
CS42L55
U1
www.silabs.com
SILICON LABS
CP2114-CS42L55-EVB
P1
P3
P4
J1
J2
J4
J3
J10
J5
J9
P2
AIN
HP OUT
LINE OUT
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5.3. WM8523-EB Overview
The WM8523 evaluation board contains a pre-installed WM8523 for evaluation and preliminary software develop-
ment with the CP2114 evaluation board. Refer to
Figure 8 for the locations of the various I/O connectors on the
WM8523 -EB.
J1 Daughter card connector
J2 Line output connector
J3 Headphone output connector
JP2-JP10 I2S and I2C signal connectors
JP11 Voltage regulator input connector
JP12 WM8253 supply voltage header
JP13 WM8253 supply voltage connector
JP14 Headphone amplifier SHDN header
JP15 Ground header
JP16-JP20 GPIO header for SHDN control
Figure 8. WM8253 Evaluation Board with Default Shorting Blocks Installed
5.3.1. Daughter Card Connector (J1)
The J1 connector is used to connect to a CP2114 evaluation board (CP2114-EB). The WM8253-EB must be
plugged into a CP2114 evaluation board to function properly.
5.3.2. Line Output Connector (J2)
The J2 connector is used to connect powered speakers to the WM8253 evaluation board.
5.3.3. Headphone Output Connector (J3)
The J3 connector is used to connect headphones to the WM8253 evaluation board.
5.3.4. I2S/I2C Signal Connectors (JP2-JP10)
Connectors JP2 through JP10 are provided to allow access to the I2S/I2C signals between the CP2114 and
WM8253. Placing a shorting block between pins 1 and 2 will connect the CP2114 to the WM8253. Placing a
shorting block between pins 2 and 3 will connect the corresponding WM8253 pin to ground. When monitoring the
I2S signals, connect the scope probe ground lead to the adjacent ground pin.
WM8523
U1
www.silabs.com
SILICON LABS
CP2114-WM8523-EVB
J1
J3
J2
JP13
JP9
JP10
JP14
JP7
JP8
JP5
JP6
JP3
JP4
JP2
JP15
JP12
JP19
JP20
JP16
JP17
JP18
HP OUT
LINE OUT JP11
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CP2114-EK
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5.3.5. Voltage Regulator Connector (JP11)
The JP11 connector is used to connect the VBUS signal being supplied to the CP2114 to the input of the voltage
regulator on the WM8253 evaluation board. Installing this jumper connects the VBUS signal to the regulator output.
If another voltage supply is used, JP11 should be removed and the supply should be connected to pin 2 of the
header.
5.3.6. WM8253 Supply Voltage Header (JP12)
The JP12 header provides access to the WM8253 supply voltage.
5.3.7. WM8253 Supply Voltage Connector (JP13)
This header (JP13) is included on the evaluation board to provide several power options for the WM8253. The
following describes the function of each pin:
Shorting pins 1,2: Connects the regulator output on the WM8253-EB to the supply of the WM8253.
Shorting pins 2,3: Connects the CP2114 VDD (CP2114 pin 7) to the supply of the WM8253.
5.3.8. Headphone Amplifier SHDN Header (JP14, JP16–JP20)
The jumpers JP14 and JP16-JP20 control the headphone amplifier shutdown (SHDN) pin. The headphone
amplifier is enabled when SHDN is high and disabled when SHDN is low. In the default configuration (jumper
shorting pins1 and 2), the headphone amp is always enabled. Shorting pins 2 and 3 on JP14 will disable the
headphone amplifier. Removing JP14 and connecting one of JP16-JP20 allows the host to control the headphone
amp via GPIO pin. In this case, the corresponding GPIO-GPIO_C jumper must also be installed on the CP2114-EK
board.
5.3.9. Ground Header (JP15)
The JP15 header provides access to ground.
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5.4. PCM1774-EB Overview
The PCM1774 evaluation board includes contains a pre-installed a PCM1774 for evaluation and preliminary soft-
ware development with the CP2114 evaluation board. Refer to
Figure 9 for the locations of the various I/O connec-
tors on the
PCM1774 -EB.
J1 Daughter card connector
J2 Headphone/line output connector
J3 Analog input connector
JP1-JP7 I2S signal connectors
JP8 Voltage regulator connector
JP9 PCM1774 supply voltage connector
JP15, JP16 External capacitor connectors
Figure 9. PCM1774 Evaluation Board with Default Shorting Blocks Installed
5.4.1. Daughter Card Connector (J1)
The J1 connector is used to connect to a CP2114 evaluation board (CP2114-EB). The PCM1774-EB must be
plugged into a CP2114 evaluation board to function properly.
5.4.2. Headphone/Line Output Connector (J2)
The J2 connector is used to connect headphones or powered speakers to the PCM1774 evaluation board.
5.4.3. Analog Input Connector (J3)
The J3 connector is used to connect an input device to the PCM1774 evaluation board.
5.4.4. I2S/I2C Signal Connectors (JP1–JP7)
Connectors JP1 through JP7 are provided to allow access to the I2S/I2C signals between the CP2114 and
PCM1774. Placing a shorting block between pins 1 and 2 will connect the CP2114 to the PCM1774. Placing a
shorting block between pins 2 and 3 will connect the corresponding PCM1774 pin to ground. When monitoring the
I2S signals, connect the scope probe ground lead to the adjacent ground pin.
5.4.5. Voltage Regulator Connector (JP8)
The JP8 connector is used to connect the VBUS signal being supplied to the CP2114 to the input of the voltage
regulator on the PCM1774 evaluation board. Installing this jumper connects the VBUS signal to the regulator
output. If another voltage supply is used, JP8 should be removed and the supply should be connected to pin 2 of
the header.
PCM1774
U1
www.silabs.com
SILICON LABS
CP2114-PCM1774-EVB
J1
J3
J2
JP9
JP6
JP7
JP4
JP2
JP3
JP1
JP5
JP15 JP16
ANALOG IN
HP/LINE OUT JP8
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CP2114-EK
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5.4.6. PCM1774 Supply Voltage Connector (JP9)
This header (JP9) is included on the evaluation board to provide several power options for the PCM1774. The
following describes the function of each pin:
Shorting pins 1,2: Connects the regulator output on the PCM1774-EB to the supply of the PCM1774.
Shorting pins 2,3: Connects the CP2114 VDD (CP2114 pin 7) to the supply of the PCM1774.
5.4.7. External Capacitor Connectors (JP15, JP16)
The JP15 and JP16 connectors allow external capacitors to be connected to the HP/LINE OUT connector. For best
low frequency response (35 Hz cutoff), remove the jumpers on JP15 and JP16. For maximum power output (45 Hz
cutoff), place the jumpers on JP15 and JP16.
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CP2114-EK
Rev. 0.1 17
6. Schematics
Figure 10. CP2114 Evaluation Board Schematic
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CP2114-EK
18 Rev. 0.1
Figure 11. CS42L55 Evaluation Board Schematic
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CP2114-EK
Rev. 0.1 19
Figure 12. WM8523 Evaluation Board Schematic
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CP2114-EK
20 Rev. 0.1
Figure 13. PCM1774 Evaluation Board Schematic
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