IDT 89EBPES16NT2 User manual

®
November 2007
6024 Silver Creek Valley Road, San Jose,California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2007 Integrated Device Technology,Inc.
IDT™89EBPES16NT2
Evaluation Board Manual
(Eval Board: 18-642-000)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patentrights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unlessa specific written agreementpertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use providedin the labeling, can be reasonably expected toresult in a significant injury to the user.
2.A criticalcomponentisany componentsof alifesupportdeviceor systemwhosefailure toperformcanbe reasonablyexpected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT,the IDT logo, and Integrated Device Technologyare trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
EB16NT2 Eval Board Manual i November 13, 2007
Table of Contents
®
Description of the EB16NT2 Eval Board
Introduction.....................................................................................................................................1-1
Board Features...............................................................................................................................1-2
Hardware................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-2
Installation of the EB16NT2 Eval Board
EB16NT2 Installation......................................................................................................................2-1
PCI Express Adapter Card..............................................................................................................2-1
Hardware Description .....................................................................................................................2-1
Reference Clocks............................................................................................................................2-2
Power Sources................................................................................................................................2-3
PCI Express Serial Data Transmit Termination Voltage Converter........................................2-3
PCI Express Digital Power Voltage Converter........................................................................2-3
PCI Express Analog Power Voltage Converter......................................................................2-3
Core Logic Voltage Converter................................................................................................2-3
3.3V I/O Power Module...........................................................................................................2-3
Power-up Sequence...............................................................................................................2-3
Required Jumpers..................................................................................................................2-3
Reset...............................................................................................................................................2-3
Fundamental Reset................................................................................................................2-4
Boot Configuration Vector...............................................................................................................2-4
SMBus Interfaces............................................................................................................................2-5
SMBus Slave Interface...........................................................................................................2-6
SMBus Master Interface.........................................................................................................2-6
JTAG Header..................................................................................................................................2-7
Miscellaneous Jumpers, Headers...................................................................................................2-7
LEDs...............................................................................................................................................2-7
PCI Express Edge Connector.........................................................................................................2-8
PCI Express Cable x8 Wire Connections...............................................................................2-9
PCI Express Cable x8 Connector Definition.........................................................................2-11
EB16NT2 Eval Board Figure.........................................................................................................2-13
Software for the EB16NT2 Eval Board
Introduction.....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics.....................................................................................................................................4-1

IDT Table of Contents
EB16NT2 Eval Board Manual ii November 13, 2007
Notes

Notes
EB16NT2 Eval Board Manual iii November 13, 2007
List of Tables
®
Table 2.1 Clock Source Selection .......................................................................................................2-2
Table 2.2 Clock Frequency Selection .................................................................................................2-2
Table 2.3 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.4 Boot Configuration Vector Signals ......................................................................................2-4
Table 2.5 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1) ...........................................2-5
Table 2.6 Slave SMBus Interface Connector ......................................................................................2-6
Table 2.7 SMBus Slave Interface Address Configuration ...................................................................2-6
Table 2.8 JTAG Connector Pin Out ....................................................................................................2-7
Table 2.9 Miscellaneous Jumpers, Headers .......................................................................................2-7
Table 2.10 LED Indicators ....................................................................................................................2-7
Table 2.11 PCI Express x8 Edge Connector Pinout .............................................................................2-8
Table 2.12 PCI Express Cable x8 Wire Connections ...........................................................................2-9
Table 2.13 PCI Express x8 Connector Definitions ..............................................................................2-11

IDT List of Tables
EB16NT2 Eval Board Manual iv November 13, 2007
Notes

Notes
EB16NT2 Eval Board Manual v November 13, 2007
List of Figures
®
Figure 1.1 Function Block Diagram of the EB16NT2 Eval Board ........................................................1-1
Figure 2.1 PCIe Adapter Card .............................................................................................................2-1

IDT List of Figures
EB16NT2 Eval Board Manual vi November 13, 2007
Notes

Notes
EB16NT2 Eval Board Manual 1 - 1 November 13, 2007
®
Chapter 1
Description of the EB16NT2
Eval Board
Introduction
The 89HPES16NT2 switch (also referred to as PES16NT2 in this manual) is a member of IDT’s PCI
Express® standard (PCIe®) based line of products.It is a 16-lane,2-port peripheral chip that provides high-
performance switching and non-transparent bridging (NTB) function between an upstream port and an NTB
downstream port.
The 89EBPES16NT2 Evaluation Board (also referred to as EB16NT2 in this manual) provides an evalu-
ation platform for the PES16NT2 switch. It is designed to functionas an add-on card to beplugged into a x8
PCIe slot available on a motherboard hosting an appropriate root complex, microprocessor(s), and an NTB
downstream port to be connected to another root complex, microprocessor(s) via a PCI Express cable. The
EB16NT2 is a vehicle to test and evaluate the functionality of the PES16NT2 chip. Customers can use this
board to get a headstart on software development prior to the arrival of their own hardware. The EB16NT2
is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure
1.1 illustrates the functional block diagram representing the main parts of the EB16NT2 board.
Figure 1.1 Function Block Diagram of the EB16NT2 Eval Board
JTAG
Header
Main
Reset
24LC512
SMBUS
HEADER
PES16NT2
PCI Express
Switch
x8
25 MHz
SSC Clock
Buffer
Clock
Fanout
SMBus
Voltages on board
+12V, +3.3V, +1.5V, +1.0V
Power
Module
PTH08T240
EEPROM
x8 PCI Express Connector
x8
PCIe x8 Upstream Edge

IDT Description of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 1 - 2 November 13, 2007
Notes Board Features
Hardware
PES16NT2 PCIe 2-port Non-Transparent switch
– Two ports, 16 PCIe lanes
– PCIe Base Specification Revision 1.0a compliant
– 8 GBps (64Gbps) aggregate switching capacity
– Up to 2048 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x8, x4, x2,x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Transparent/Non-Transparent Port
– One edge connector on the upstream port, to be plugged into a slot with x8 capable on a host
motherboard
– Transparent or Non-Transparent port via x8 PCI Express connector
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates
– Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
Push button for Warm Reset
Several LEDs to display status, reset, power, etc.
One 10-pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board in transparent mode. However, useful software
is provided along with the Evaluation Board to facilitate configuration and evaluation of the PES16NT2
within host systems running popular operating systems. In non-transparent mode, IDT provides Windows
XP or a Linux device driver for PES16NT2 Non-Transparent Bridge endpoints. This driver includes two
separate drivers, PCI endpoint driver and NDIS Ethernet miniport driver. Please contact [email protected]
for additional information.
Installation programs
– Operating Systems Supported: Windows2000, WindowsXP, Linux
GUI-based application for Windows and Linux
– Allows users to view and modify registers in the PES16NT2
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is required to firmly hold in place the four endpoints plugged into the EB16NT2
board.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB16NT2 board for specific test points.
Revision History
November 13, 2007: Initial publication of board manual.

Notes
EB16NT2 Eval Board Manual 2 - 1 November 13, 2007
®
Chapter 2
Installation of the EB16NT2
Eval Board
EB16NT2 Installation
This chapter discusses the steps required to configure and install the EB16NT2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Insert the evaluation board into the host system (motherboard with root complex chipset).
3. Connect the NTB port to a remote system via a PCI Express® cable. An PCI Express adapter card
to PCI Express Cable connector can be used on a remote system.
4. Apply power to the host system.
The EB16NT2 board is shipped with all jumpers and switches configured to their default settings. In
most cases, the board does not require further modification or setup.
PCI Express Adapter Card
The PCI Express adapter card is an x8 link PCI Express card. It can be installed in a remote system. A
(x8 lane) PCIe® cable is used to connect a remote system to EB16NT2 NTB port. See Figure 2.1 for the
graphical presentation of this connection.
Figure 2.1 PCIe Adapter Card
Hardware Description
The 89HPES16NT2 is a member of theIDT PRECISE™ family of PCI Express switching solutions offering
the next-generation I/O interconnect standard. The PES16NT2 is a 16-lane, 2-port peripheral chip that pro-
vides high-performance switching and non-transparentbridging (NTB) functions between a PCIe upstream
x8
x8 (upstream)
x8 (NTB)
PES16NT2
PCIe Connector
(x8) PCIe Cable
Tx
Rx
EB16NT2 Eval Board Install in Host PC PCI Express Adapter Card Install
inRemote PC

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 2 November 13, 2007
Notes port and an NTB downstream port. The PES16NT2 is a part of the IDT PCIe System Interconnect
Products family and is intended to be used with IDT PCIe System Interconnect Switches. Together, the
chipset targets multi-host and intelligent I/O applications such as communications, storage, and blade serv-
ers, where inter-domain communication is required.
The EB16NT2 non-transparent port is accessible through x8 PCI Express cable connectors.
Basic requirements for the board to run are:
–Host system with a PCI Express root complex supporting x8 configuration througha PCI Express
x8 slot.
–AsecondaryremotesystemwithaPCIExpressrootcomplex supportingx8 configuration through
a PCI Express x8 slot.
Reference Clocks
The PES16NT2 requires a pair of differential reference clocks. The EB16NT2 derives these clocks from
a common source which is user-selectable. The common source can be either the host system’sreference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1. Typical
usage model for the EB16NT2 in non-transparent mode includes two root complexes: one connects to the
upstream port and the other connects to a NTB port. Each root complex most likely will have its own clock
source. SSC (Spread Spectrum Clock) must be disabled in this configuration.
The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB16NT2 allows selection between multiple
clock rates via DIP switches as described in Table 2.2.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.3. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Clock Configuration Stuffing Option
W7 and W8 Clock Source
Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection
Clock Frequency Switch - S2[2:1]
S2[2] S2[1] Clock Frequency
OFF OFF Reserved
OFF ON 125 MHz
ON OFF 100 MHz (Default)
ON ON <Reserved>
Table 2.2 Clock Frequency Selection
Onboard Reference Clock Output (Differential) – J2, J3
J2 Positive Reference Clock
J3 Negative Reference Clock
Table 2.3 SMA Connectors - Onboard Reference Clock

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 3 November 13, 2007
Notes Power Sources
The EB16NT2 is powered from the upstream port slot power.
PCI Express Serial Data Transmit Termination Voltage Converter
A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown
as VPETVTT) to the PES16NT2.
PCI Express Digital Power Voltage Converter
A separate DC-DC converter (U3) provides a 1.0V PCI Express digital power voltage (VDDPE) to the
PES16NT2.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (7) provides a 1.0V PCI Express analog power voltage (shown as
VDDPEA) to the PES16NT2.
Core Logic Voltage Converter
A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES16NT2.
3.3V I/O Power Module
A 12V to 3.3V power module (U26) provides the 3.3V I/O voltage (VDD_3V3) to the PES16NT2.
Power-up Sequence
The power-up sequence must be as following:
1. VDDIO - 3.3V
2. VDDCORE, VDDPEA, VDDPE - 1.0V
3. VTTPE - 1.5V
When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in
the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations
between sequential valid power level requirements. To insure that the sequencing requirements are met, a
0.015UF is used at the SOFTSTART cap on the VTTPE and VTTPEA voltage converter (U3 and U7 pin 36)
in the EB16NT2.
Required Jumpers
To deliver power to the PES16NT2 switch, the following jumpers must be shunted: W10, W22-W25.
These jumpers were implemented so that the power consumption of the PES16NT2 can be measured.
Reset
The PES16NT2 supports two types of reset mechanisms as described in the PCI Express specification:
–Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES16NT2, and the endpoints.
–Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES16NT2
User Manual. The EB16NT2 evaluation board provides seamless support for Hot Reset.

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 4 November 13, 2007
Notes Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB16NT2 evaluation board:
–Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES16NT2.
–Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
•Pressing a push-button switch (S1) locatedon EB16NT2 board
•The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB16NT2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the resistor from pin 1-2 to pin 2-3 on W27.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16NT2 while power is on.
An external side fundamental reset is initiated when the switch is configured to operatein non-trans-
parent mode and the PCI Express Non-Transparent Bridge Reset (PENTBRST#) signal is asserted. This
results in the resetting of the transaction, datalink, and PHY layers associated with the external side of the
non-transparent bridge. The initialization of all registers associated with the external side of the non-trans-
parent bridge are set to their initial values except those with a read and write when unlocked attribute and
those associated with the non-transparent bridge configuration capability structure.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.4 is sampled by the PES16NT2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S5 and S6 as defined in Table 2.5.
Signal Description
CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the SlotClock Configuration bit inall of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the down-
stream port’s PCIELSTS register. Default: 0x1
CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is
using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Default: 0x1
MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
RSTHALT Reset Halt. When thissignal is asserted during a PCI Express fundamental reset, the
PES16NT2 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
Table 2.4 Boot Configuration Vector Signals (Part 1 of 2)

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 5 November 13, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
SWMODE[2:0] SwitchMode.Theseconfigurationpinsdeterminethe PES16NT2switchoperatingmode.
Default: 0x1
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode serial EEPROM initialization
0x7 - 0xF Reserved
Default: 0x0
REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-
erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0] MasterSMBus Address. Thesepinsdeterminethe SMBusaddressoftheserialEEPROM
from which configuration information is loaded. Default: 0x0
Signal Description Default
S6[1] CCLKDS OFF
S6[2] CCLKUS OFF
S6[3] SWMODE[3] ON
S6[4] SWMODE[2] ON
S6[5] SWMODE[1] ON
S6[6] SWMODE[0] ON
S6[7] Not Used ON
S6[8] Not Used ON
S5[1] MSMBADDR[4] ON
S5[2] MSMBADDR[3] ON
S5[3] MSMBADDR[2] ON
S5[4] MSMBADDR[1] ON
S5[5] REFCLKM ON
S6[6] RSTHALT# ON
S6[7] MSMBSMODE ON
S5[8] Not Used ON
Table 2.5 Boot Configuration Vector Switches S7 & S8 (ON=0, OFF=1)
Signal Description
Table 2.4 Boot Configuration Vector Signals (Part 2 of 2)

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 6 November 13, 2007
Notes The PES16NT2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter-
face. The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all
software-visible registers. The Master SMBus interface provides connection to the external serial
EEPROMs used for initialization.
SMBus Slave Interface
On the PES16NT2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.6.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R74 and R75.
.
A fixed slave SMBus address (0b1110_111) specified by the SSMBADDR[5,3:1] pins is used.
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
–Byte and Word Write/Read
–Block Write/Read
SMBus Master Interface
The seven bits address for the selected EEPROM device is 0b1010_000 by default.
Slave SMBus Interface Connector
J10
Pin Signal
1N/C
2SCL
3GND
4SDA
Table 2.6 Slave SMBus Interface Connector
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
40
5 SSMBUSADDR[5]
61
71
Table 2.7 SMBus Slave Interface Address Configuration

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 7 November 13, 2007
Notes JTAG Header
The PES16NT2 provides a JTAG connector J4 for access to the PES16NT2 JTAG interface. The
connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.8 for the JTAG Connector J4
pin out.
Miscellaneous Jumpers, Headers
LEDs
There are several LED indicators on the EB16NT2 which convey status feedback. A description of each
is provided in Table 2.10.
JTAG Connector J5
Pin Signal Direction Pin Signal Direction
1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —
Table 2.8 JTAG Connector Pin Out
Miscellaneous Jumpers, Headers
Ref.
Designator Type Default Description
W12 Header Shunted Disable EEPROM Write protect feature (Default)
W2 Header Open Force remote (PCIe Cable) power on
W32 Header Open Tie PCIe Cable 3.3V power to on board VCC_3V3
Table 2.9 Miscellaneous Jumpers, Headers
Location Color Definition
DS2 Green VCC_3V3Power indicator
DS1 Red Reset
DS4 Green GPIO0
DS29 Green GPIO3
DS30 Green GPIO5
DS31 Green GPIO7
DS33 Green GPIO2
DS34 Green GPIO4
DS35 Green GPIO5
DS29 Green GPIO9
Table 2.10 LED Indicators (Part 1 of 2)

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 8 November 13, 2007
Notes
PCI Express Edge Connector
DS30 Green GPIO10
DS31 Green GPIO12
DS32 Green GPIO15
Pin Side B Side A
1 +12V 12V power PRSNT1# Hot-Plug presence detect
2 +12V 12V power +12V 12V power
3 RSVD Reserved +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clki/p
6 SMDAT SMBus Data JTAG TDI (Test Data Input)
7 GND Ground JTAG TDO (Test Data Output)
8 +3.3V 3.3V power JTAG TMS (Test Mode Select)
9 JTAG1 TRST#(Test/Reset)resets
JTAG i/f +3.3V 3.3V power
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# Signal for Link reactivation PERST# Fundamental Reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ REFCLK Reference clock
14 PETp0 Transmitter differential REFCLK- (differential pair)
15 PETn0 pair, Lane 0 GND Ground
16 GND Ground PERp0 Receiver differential
17 PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0
18 GND Ground GND Ground
19 PETp1 Transmitter differential RSVD Reserved
20 PETn1 pair, Lane 1 GND Ground
21 GND Ground PERp1 Receiver differential
22 GND Ground PERn1 pair, Lane 1
23 PETp2 Transmitter differential GND Ground
24 PETn2 pair, Lane 2 GND Ground
25 GND Ground PERp2 Receiver differential
26 GND Ground PERn2 pair, Lane 2
Table 2.11 PCI Express x8 Edge Connector Pinout (Part 1 of 2)
Location Color Definition
Table 2.10 LED Indicators (Part 2 of 2)

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 9 November 13, 2007
Notes
PCI Express Cable x8 Wire Connections
27 PETp3 Transmitter differential GND Ground
28 PETn3 pair, Lane 3 GND Ground
29 GND Ground PERp3 Receiver differential
30 RSVD Reserved PERn3 pair, Lane 3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
33 PETp4 Transmitter differential RSVD Reserved
34 PETn4 pair, Lane 4 GND Ground
35 GND Ground PERp4 Receiver differential
36 GND Ground PERn4 pair, Lane 4
37 PETp5 Transmitter differential GND Ground
38 PETn5 pair, Lane 5 GND Ground
39 GND Ground PERp5 Receiver differential
40 GND Ground PERn5 pair, Lane 5
41 PETp6 Transmitter differential GND Ground
42 PETn6 pair, Lane 6 GND Ground
43 GND Ground PERp6 Receiver differential
44 GND Ground PERn6 pair, Lane 6
45 PETp7 Transmitter differential GND Ground
46 PETn7 pair, Lane 7 GND Ground
47 GND Ground PERp7 Receiver differential
48 PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7
49 GND Ground GND Ground
Pin# Cable Side A CableSide B Pin#
A1 A4 A7 A10 A13
A16 A22 A25 A28
A31 A34 B1 B4 B7
B10 B13 B22 B25
B28 B31 B34
GND Drain Wires GND A1 A4 A7 A10 A13
A16 A22 A25 A28
A31 A34 B1 B4 B7
B10 B13 B22 B25
B28 B31 B34
A2 PETp0 Differential Pair PERp0 B2
A3 PETn0 PERn0 B3
A5 PETp1 Differential Pair PERp1 B5
A6 PETn1 PERn1 B6
Table 2.12 PCI Express Cable x8 Wire Connections (Part 1 of 3)
Pin Side B Side A
Table 2.11 PCI Express x8 Edge Connector Pinout (Part 2 of 2)

IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 10 November 13, 2007
Notes
A8 PETp2 Differential Pair PERp2 B8
A9 PETn2 PERn2 B9
A11 PETp3 Differential Pair PERp3 B11
A12 PETn3 PERn3 B12
A14 CREFCLKp Differential Pair CREFCLKp A14
A15 CREFCLKn CREFCLKn A15
A17 RSVD NC RSVD A17
A18 RSVD NC RSVD A18
A19 SB_RTN Hook-up Wire SB_RTN A19
A20 CPRSNT Hook-up Wire CPRSNT A20
A21 CPWRON Hook-up Wire CPWRON A21
A23 PETp4 Differential Pair PERp4 B23
A24 PETn4 PERn4 B24
A26 PETp5 Differential Pair PERp5 B26
A27 PETn5 PERn5 B27
A29 PETp6 Differential Pair PERp6 B29
A30 PETn6 PERn6 B30
A32 PETp7 Differential Pair PERp7 B32
A33 PETn7 PERn7 B33
B2 PERp0 Differential Pair PETp0 A2
B3 PERn0 PETn0 A3
B5 PERp1 Differential Pair PETp1 A5
B6 PERn1 PETn1 A6
B8 PERp2 Differential Pair PETp2 A8
B9 PERn2 PETn2 A9
B11 PERp3 Differential Pair PETp3 A11
B12 PERn3 PETn3 A12
B14 PWR NW PWR B14
B15 PWR NW PWR B15
B16 PWR NW PWR B16
B17 PWR_RTN NW PWR_RTN B17
B18 PWR_RTN NW PWR_RTN B18
B19 PWER_RTN NW PWER_RTN B19
B20 CWAKE# Hook-up Wire CWAKE# B20
B21 CPERST# Kook-up Wire CPERST# B21
B23 PERp4 Differential Pair PETp4 A23
B24 PERn4 PETn4 A24
Pin# Cable Side A CableSide B Pin#
Table 2.12 PCI Express Cable x8 Wire Connections (Part 2 of 3)