Silicon Laboratories SI4734/35-B20 User manual

Rev. 1.0 4/08 Copyright © 2008 by Silicon Laboratories Si4734/35-B20
Si4734/35-B20
BROADCAST AM/FM/SW/LW RADIO RECEIVER
Features
Applications
Description
The Si4734/35 is the first digital CMOS AM/FM/SW/LW radio receiver IC that
integrates the complete tuner function from antenna input to audio output.
Functional Block Diagram
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support (2.3–21.85 MHz)
LW band support (153–279 KHz)
Excellent real-world performance
Freq synthesizer with integrated VCO
Automatic frequency control (AFC)
Automatic gain control (AGC)
Integrated LDO regulator
Digital FM stereo decoder
Programmable de-emphasis
Adaptive noise suppression
AM/FM/SW/LW digital tuning
No manual alignment necessary
Adjustable channel filters
EN55020 complaint
Programmable reference clock
Digital volume control
Adjustable soft mute control
RDS/RBDS processor (Si4735 only)
Optional digital audio out (Si4735 only)
2-wire and 3-wire control interface
2.7 to 5.5 V supply voltage
Wide range of ferrite loop sticks and air
loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
zPb-free/RoHS compliant
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Portable media players
Boom boxes
Cellular handsets
Modules
Clock radios
Mini HiFi
Entertainment systems
ADC
ADC
Si4734/35
DSP
DAC
DAC
FMI
FM / SW
ANT
VIO
1.5-3.6V
SCLK
SDIO
CONTROL
INTERFACE
SEN
RST
ROUT
LOUT
LDO
VDD
GND
2.7 - 5.5 V
RDS
(Si4735)
AM / LW
ANT RFGND
AMI
LNA
LNA
LOW-IF
DIGITAL
AUDIO
(Si4735)
DOUT
DFS
GPO/DCLK
AGC
AGC
AFC
RCLK
Patents pending
Notes:
1. To ensure proper operation and
receiver performance, follow the
guidelines in “AN383: Antenna
Selection and Universal Layout
Guide.” Silicon Laboratories will
evaluate schematics and layouts for
qualified customers.
2. Place Si4734/35 as close as
possible to antenna jack and keep
the FMI and AMI traces as short as
possible.
Ordering Information:
See page 31.
Pin Assignments
GND
PAD
1
2
3
17181920
11
12
13
14
6789
4
5
16
10
15
GPO2/INT
VIO
DOUT
LOUT
ROUT
GNDRST
NC
AMI
RCLK
SDIO
VDD
FMI
RFGND
GPO3/DCLK NC GPO1 DFS
SCLK
SEN
Si4734/35-GM
(Top View)

Si4734/35-B20
2 Rev. 1.0

Si4734/35-B20
Rev. 1.0 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Si4734/35-B20
4 Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage VDD 2.7 — 5.5 V
Interface Supply Voltage VIO 1.5 — 3.6 V
Power Supply Powerup Rise Time VDDRISE 10 — — µs
Interface Power Supply Powerup Rise Time VIORISE 10 — — µs
Ambient Temperature TA–20 25 85 °C
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter Symbol Value Unit
Supply Voltage VDD –0.5 to 5.8 V
Interface Supply Voltage VIO –0.5 to 3.9 V
Input Current3IIN 10 mA
Input Voltage3VIN –0.3 to (VIO + 0.3) V
Operating Temperature TOP –40 to 95 °C
Storage Temperature TSTG –55 to 150 °C
RF Input Level40.4 VpK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.

Si4734/35-B20
Rev. 1.0 5
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
FM Mode
Supply Current IFM —19.222mA
Supply Current1IFM Low SNR level — 19.8 23 mA
RDS Supply Current2IFM —19.923mA
Supply Current2IFMD Digital Output Mode — 18.0 20.5 mA
AM/SW/LW Mode
Supply Current IAM Analog Output Mode — 17.3 20.5 mA
Supply Current2IAMD Digital Output Mode — 15.5 20.5 mA
Supplies and Interface
Interface Supply Current IIO —320600µA
VDD Powerdown Current IDDPD —1020µA
VIO Powerdown Current IIOPD SCLK, RCLK inactive — 1 10 µA
High Level Input Voltage3VIH 0.7 x VIO —V
IO +0.3 V
Low Level Input Voltage3VIL –0.3 — 0.3 x VIO V
High Level Input Current3IIH VIN = VIO = 3.6 V –10 — 10 µA
Low Level Input Current3IIL VIN =0V,
VIO =3.6V –10 — 10 µA
High Level Output Voltage4VOH IOUT = 500 µA 0.8 x VIO ——V
Low Level Output Voltage4VOL IOUT = –500 µA — — 0.2 x VIO V
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Si4734/35-B20
6 Rev. 1.0
Figure 1. Reset Timing Parameters for Busmode Select
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Min Typ Max Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST↑4tSRST 100 — — µs
GPO1, GPO2/INT Hold from RST↑tHRST 30 — — ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 MΩdevices (active while RST is low) to pull GPO1 high and
GPO2 low.
70%
30%
GPO1 70%
30%
GPO2/
INT 70%
30%
tSRST
RST
tHRST

Si4734/35-B20
Rev. 1.0 7
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency fSCL 0—400kHz
SCLK Low Time tLOW 1.3 — — µs
SCLK High Time tHIGH 0.6 — — µs
SCLK Input to SDIO ↓Setup
(START) tSU:STA 0.6 — — µs
SCLK Input to SDIO ↓Hold (START) tHD:STA 0.6 — — µs
SDIO Input to SCLK ↑Setup tSU:DAT 100 — — ns
SDIO Input to SCLK ↓Hold4,5 tHD:DAT 0—900ns
SCLK input to SDIO ↑Setup (STOP) tSU:STO 0.6 — — µs
STOP to START Time tBUF 1.3 — — µs
SDIO Output Fall Time tf:OUT —250ns
SDIO Input, SCLK Rise/Fall Time tf:IN
tr:IN
—300ns
SCLK, SDIO Capacitive Loading Cb— — 50 pF
Input Filter Pulse Suppression tSP — — 50 ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high)
does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated
as long as all other timing parameters are met.
20 0.1 Cb
1pF
-----------
+
20 0.1 Cb
1pF
-----------
+

Si4734/35-B20
8 Rev. 1.0
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
SCLK 70%
30%
SDIO 70%
30%
START STARTSTOP
tf:IN
tr:IN
tLOW tHIGH tHD:STA tSU:STA tSU:STO
tSP tBUF
tSU:DAT
tr:IN tHD:DAT tf:IN,
tf:OUT
SCLK
SDIO
START STOPADDRESS + R/W ACK DATA ACK DATA ACK
A6-A0,
R/W D7-D0 D7-D0

Si4734/35-B20
Rev. 1.0 9
Figure 4. 3-Wire Control Interface Write Timing Parameters
Figure 5. 3-Wire Control Interface Read Timing Parameters
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency fCLK 0—2.5MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLK↑ Setup tS20 — — ns
SDIO Input to SCLK↑ Hold tHSDIO 10 — — ns
SEN Input to SCLK↓ Hold tHSEN 10 — — ns
SCLK↑ to SDIO Output Valid tCDV Read 2 — 25 ns
SCLK↑ to SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF— — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK 70%
30%
SEN 70%
30%
SDIO A7 A0
70%
30%
tS
tS
tHSDIO tHSEN
A6-A5,
R/W,
A4-A1
Address In Data In
D15 D14-D1 D0
tHIGH tLOW
tRtF
½ Cycle Bus
Turnaround
SCLK 70%
30%
SEN 70%
30%
SDIO 70%
30%
tHSDIO tCDV tCDZ
Address In Data Out
A7 A0
A6-A5,
R/W,
A4-A1 D15 D14-D1 D0
tS
tStHSEN

Si4734/35-B20
10 Rev. 1.0
Figure 6. SPI Control Interface Write Timing Parameters
Figure 7. SPI Control Interface Read Timing Parameters
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency fCLK 0—2.5MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLK↑ Setup tS15 — — ns
SDIO Input to SCLK↑ Hold tHSDIO 10 — — ns
SEN Input to SCLK↓ Hold tHSEN 5——ns
SCLK↓ to SDIO Output Valid tCDV Read 2 — 25 ns
SCLK↓ to SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF— — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK 70%
30%
SEN 70%
30%
SDIO C7 C0
70%
30%
tS
C6–C1
Control Byte In 8 Data Bytes In
D7 D6–D1 D0
tS
tHSDIO tHIGH tLOW tHSEN
tF tR
Bus
Turnaround
SCLK 70%
30%
SEN 70%
30%
SDIO 70%
30%
tHSDIO
Control Byte In
C7 C0C6–C1
tStHSEN
tS
tCDZ
tCDV
16 Data Bytes Out
(SDIO or GPO1)
D7 D6–D1 D0

Si4734/35-B20
Rev. 1.0 11
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Table 8. Digital Audio Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
DCLK Cycle Time tDCT 26 — 1000 ns
DCLK Pulse Width High tDCH 10 — — ns
DCLK Pulse Width Low tDCL 10 — — ns
DFS Set-up Time to DCLK Rising Edge tSU:DFS 5——ns
DFS Hold Time from DCLK Rising Edge tHD:DFS 5——ns
DOUT Propagation Delay from DCLK Falling
Edge tPD:DOUT 0—12ns
DCLK
DFS
tDCT
tPD:OUT
tSU:DFS tHD:DFS
DOUT
tDCH tDCL

Si4734/35-B20
12 Rev. 1.0
Table 9. FM Receiver Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency fRF 76 — 108 MHz
Sensitivity with Headphone
Network3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF
Sensitivity with 50 ΩNetwork3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF
RDS Sensitivity6Δf = 2 kHz,
RDS BLER < 5% —15—µVEMF
LNA Input Resistance6,7 345kΩ
LNA Input Capacitance6,7 456pF
Input IP36,8 100 105 — dBµV EMF
AM Suppression3,4,6,7 m = 0.3 40 50 — dB
Adjacent Channel Selectivity ±200 kHz 35 50 — dB
Alternate Channel Selectivity ±400 kHz 60 70 — dB
Spurious Response Rejection6In-band 35 — — dB
Audio Output Voltage3,4,7 72 80 90 mVRMS
Audio Output L/R Imbalance3,7,9 —— 1 dB
Audio Frequency Response Low6–3 dB — — 30 Hz
Audio Frequency Response High6–3 dB 15 — — kHz
Audio Stereo Separation7,9 25 — — dB
Audio Mono S/N3,4,5,7,10 55 63 — dB
Audio Stereo S/N4,5,7,10,11 —58— dB
Audio THD3,7,9 —0.10.5 %
De-emphasis Time Constant6FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Audio Output Load Resistance6,10 RLSingle-ended 10 — — kΩ
Audio Output Load Capacitance6,10 CLSingle-ended — — 50 pF
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD =1kHz,75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. Δf = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF =1mV.
8. |f2– f1| > 2 MHz, f0=2xf
1– f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
9. Δf = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature (25°C).

Si4734/35-B20
Rev. 1.0 13
Seek/Tune Time6RCLK tolerance
=100ppm — — 80 ms/channel
Powerup Time6From powerdown — — 110 ms
RSSI Offset12 Input levels of 8 and
60 dBµV at RF Input –3 — 3 dB
Table 9. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD =1kHz,75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. Δf = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF =1mV.
8. |f2– f1| > 2 MHz, f0=2xf
1– f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
9. Δf = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature (25°C).

Si4734/35-B20
14 Rev. 1.0
Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency fRF 64 — 75.9 MHz
Sensitivity with Headphone
Network2,3,4,5 (S+N)/N = 26 dB — 4.0 — µV EMF
LNA Input Resistance5,6 345kΩ
LNA Input Capacitance5,6 456pF
Input IP35,7 100 105 — dBµV EMF
AM Suppression2,3,5,6 m = 0.3 40 50 — dB
Adjacent Channel Selectivity5±200 kHz — 50 — dB
Alternate Channel Selectivity5±400 kHz — 70 — dB
Audio Output Voltage2,3,5,6 72 80 90 mVRMS
Audio Output L/R Imbalance2,6,8 —— 1 dB
Audio Frequency Response Low5–3 dB — — 30 Hz
Audio Frequency Response High5–3 dB 15 — — kHz
Audio Mono S/N2,3,4,5,6,9 55 63 — dB
Audio THD2,5,6,8 —0.10.5 %
De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Audio Common Mode Voltage90.7 0.8 0.9 V
Audio Output Load Resistance5,9 RLSingle-ended 10 — — kΩ
Audio Output Load Capacitance5,9 CLSingle-ended — — 50 pF
Seek/Tune Time5RCLK tolerance
=100ppm — — 80 ms/channel
Powerup Time From powerdown — — 110 ms
RSSI Offset10 Input levels of 8 and
60 dBµV EMF –3 — 3 dB
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. Tested at
RF = 98.1 MHz.
2. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
3. Δf = 22.5 kHz.
4. BAF = 300 Hz to 15 kHz, A-weighted.
5. Guaranteed by characterization.
6. VEMF = 1 mV.
7. |f2– f1| > 2 MHz, f0= 2 x f1– f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
8. Δf = 75 kHz.
9. At LOUT and ROUT pins.
10. At temperature 25 °C.

Si4734/35-B20
Rev. 1.0 15
Table 11. AM/SW/LW Receiver Characteristics1
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency fRF
Long Wave (LW) 153 — 279 kHz
Medium Wave (AM) 520 — 1710 kHz
Short Wave (SW) 2.3 — 21.85 MHz
Sensitivity2,3,4,5, 6 (S+N)/N = 26 dB — 25 35 µV EMF
Large Signal Voltage Handling5,7 THD < 8% — 300 — mVRMS
Power Supply Rejection Ratio ΔVDD =100mV
RMS, 100 Hz — 40 — dB
Audio Output Voltage2,8 54 60 67 mVRMS
Audio S/N2,3,4,6,8 50 56 — dB
Audio THD2,4,8 — 0.1 0.5 %
Antenna Inductance Long Wave (LW) — 2800 — µH
Medium Wave (AM) 180 — 450
Powerup Time From powerdown — — 110 ms
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. BAF = 300 Hz to 15 kHz, A-weighted.
4. fRF = 1000 kHz, Δf = 10 kHz.
5. Guaranteed by characterization.
6. Analog audio output mode.
7. See “AN388: Evaluation Board Test Procedure” for evaluation method.
8. VIN = 5 mVrms.
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.

Si4734/35-B20
16 Rev. 1.0
Table 12. Reference Clock and Crystal Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Reference Clock
RCLK Supported Frequencies*31.130 32.768 40000.0 kHz
RCLK Frequency Tolerance –50 — 50 ppm
REFCLK_PRESCALE 1 — 4095
REFCLK 31.130 32.768 34.406 kHz
Crystal Oscillator
Crystal Oscillator Frequency — 32.768 — kHz
Crystal Frequency Tolerance* –100 — 100 ppm
Board Capacitance — — 3.5 pF
*Note: The Si4734/35 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details.

Si4734/35-B20
Rev. 1.0 17
2. Typical Application Schematic
Notes:
1. Place C1 close to VDD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
8. See “AN382: Si4734/35 Designer’s Guide” for further recommendations.
20 19 18 17 16
U1
Si4734/35-GM
NC
FMI
RFGND
AMI
RST
DOUT
LOUT
ROUT
GND
VDD
NC
GPO1 GPO2 GPO3
DFS
SEN SCLK SDIO RCLK VIO
SEN
SCLK
SDIO
1
2
3
4
5
15
14
13
12
11
6 7 8 9
10
RST
RCLK
C1 VBATTERY
2.7 to 5.5 V
VIO
1.5 to 3.6 V
FMI
C2 C3
X1 RCLK
GPO3
Optional: for crystal oscillator option
C5
L1
L2 LOUT
ROUT
GPO1
GPO2/INT
DCLK
DFS
DOUT
Optional: Digital Audio Output
R1
R2
R3
C4

Si4734/35-B20
18 Rev. 1.0
3. Bill of Materials
Component(s) Value/Description Supplier
C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata
C4 Capacitor, 18 pF, ±20%, Z5U/X7R Murata
C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata
L1 Ferrite loop stick, 180–450 µH Jiaxin
L2 4.7 µH Coilcraft
U1 Si4734/35 AM/FM Radio Tuner Silicon Laboratories
Optional Components
C2, C3 Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option) Venkel
X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson
R1, R2 Resistor, 2 kΩVenkel
R3 Resistor, 600 ΩVenkel

Si4734/35-B20
Rev. 1.0 19
4. Functional Description
4.1. Overview
Figure 9. Functional Block Diagram
The Si4734/35 is the industry's first fully integrated,
100% CMOS AM/FM/SW/LW radio receiver IC. Offering
unmatched integration and PCB space savings, the
Si4734/35 requires minimal external components and
less than 20 mm2of board area, excluding the antenna
inputs. The Si4734/35 AM/FM/SW/LW radio provides
the space savings and low power consumption
necessary for portable devices while delivering the high
performance and design simplicity desired for all
AM/FM/SW/LW solutions.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4734/35 delivers
superior RF performance and interference rejection in
AM, FM, and short wave and long wave bands. The
high integration and complete system production test
simplifies design-in, increases system quality, and
improves manufacturability.
The Si4734/35 is a feature-rich solution including
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, and FM stereo processing. In addition, the
Si4734/35 provides analog or digital audio output and a
programmable reference clock. The device supports
I2C-compatible 2-wire control interface, SPI, and a
Si4700/01 backwards-compatible 3-wire control
interface.
The Si4734/35 utilizes digital processing to achieve high
fidelity, optimal performance, and design flexibility. The
chip provides excellent pilot rejection, selectivity, and
unmatched audio performance, and offers both the
manufacturer and the end-user extensive
programmability and flexibility in the listening
experience.
The Si4735 incorporates a digital processor for the
European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS),
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using RDS, the Si4735 enables broadcast
data such as station identification and song name to be
displayed to the user.
ADC
ADC
Si4734/35
DSP
DAC
DAC
FMI
FM / SW
ANT
VIO
1.5-3.6V
SCLK
SDIO
CONTROL
INTERFACE
SEN
RST
ROUT
LOUT
LDO
VDD
GND
2.7 - 5.5 V
RDS
(Si4735)
AM / LW
ANT RFGND
AMI
LNA
LNA
LOW-IF
DIGITAL
AUDIO
(Si4735)
DOUT
DFS
GPO/DCLK
AGC
AGC
AFC
RCLK

Si4734/35-B20
20 Rev. 1.0
4.2. Operating Modes
The Si4734/35 operates in either an FM receive or an
AM/SW/LW receive mode. In FM mode, radio signals
are received on FMI (pin 2) and processed by the FM
front-end circuitry. In AM/SW/LW mode, radio signals
are received on AMI (pin 4) and processed by the AM
front-end circuitry. In addition to the receiver mode, a
clocking mode allows the Si4734/35 to be clocked from
a reference clock or crystal. On the Si4735, an audio
output mode is available as analog and/or digital audio
output. In the analog audio output mode, pin 13 is
ROUT, pin 14 is LOUT, pin 17 is GPO3. In the digital
audio mode, pin 15 is DOUT, pin 16 is DFS, and pin 17
is DCLK. Concurrent analog/digital audio output mode
requires pins 13, 14, 15,16, and 17. The receiver mode
and the audio output mode are set by the POWER_UP
command listed in Table 12. Si473x Command
Summary.
4.3. FM Receiver
The Si4734/35's patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The Si4734/35 receiver
supports the worldwide FM broadcast band (76 to 108
MHz) as well as an extended FM band (64 to 76 MHz),
which may include region-specific programming such as
educational channels, emergency alerts, and/or
television audio. An automatic gain control (AGC) circuit
controls the gain of the integrated low noise amplifier
(LNA) to optimize sensitivity and rejection of strong
interferers. An image-reject mixer downconverts the RF
signal to low-IF. The quadrature mixer output is
amplified, filtered, and digitized with high resolution
analog-to-digital converters (ADCs). This advanced
architecture allows the Si4734/35 to perform channel
selection, FM demodulation, and stereo audio
processing to achieve superior performance compared
to traditional analog architectures.
4.4. AM Receiver
The highly integrated Si4734/35 supports worldwide AM
band reception from 520 to 1710 kHz using a digital low-
IF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering, offering excellent selectivity and noise
suppression. The DSP also provides 9 or 10 kHz
channel selection, AM demodulation, soft mute, and
additional features such as adjustable channel
bandwidth settings. Similar to the FM receiver, the
integrated LNA and AGC optimize sensitivity and
rejection of strong interferers allowing better reception
of weak stations.
The Si4734/35 provides highly accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–450 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor, the inductance is increased by 25 times,
easily supporting all typical AM air loop antennas which
generally vary between 10 and 20 µH.
4.5. SW Receiver
The Si4734/35 is the first fully integrated IC to support
AM and FM, as well as short wave (SW) band reception
from 2.3 to 21.85 MHz fully covering the 120 meter to
13 meter bands. The Si4734/35 offers extensive
shortwave features such as continuous digital tuning
with minimal discrete components and no factory
adjustments. Other SW features include adjustable
channel step sizes in 1 kHz increments, adjustable
channel bandwidth settings, advanced seek algorithm,
and soft mute.
The Si4734/35 uses the FM antenna to capture short
wave signals. These signals are then fed directly into
the AMI pin in a wide band configuration. See “AN382:
Si4734/35 Designer’s Guide” for more details.
4.6. LW Receiver
The Si4734/35 supports the long wave (LW) band from
153 to 279 kHz. The highly integrated Si4734/35 offers
continuous digital tuning with minimal discrete
components and no factory adjustments. The Si4734/35
also offers adjustable channel step sizes in 1 kHz
increments, adjustable channel bandwidth settings,
advanced seek algorithm, and soft mute.
The Si4734/35 uses a separate ferrite bar antenna to
capture long wave signals.