Silicon Laboratories Si4330 User manual

Preliminary Rev 0.2 2/09 Copyright © 2009 by Silicon Laboratories Si4330
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si4330
Si4330 ISM RECEIVER
Features
Applications
Description
Silicon Laboratories’ Si4330 highly integrated, single chip wireless ISM receiver is
part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete
line of transmitters, receivers, and transceivers allowing the RF system designer
to choose the optimal wireless part for their application.
The Si4330 offers advanced radio features including continuous frequency
coverage from 240–960 MHzThe Si4330’s high level of integration offers reduced
BOM cost while simplifying the overall system design. The extremely low receive
sensitivity (–118 dBm) ensures extended range and improved link performance.
Built-in antenna diversity and support for frequency hopping can be used to
further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte RX FIFO, automatic packet handling, and preamble detection
reduce overall current consumption and allow the use of lower-cost system
MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset
(POR), and GPIOs further reduce overall system cost and size.
The Si4330’s digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance. This digital architecture simplifies
system design while allowing for the use of lower-end MCUs.
Frequency Range = 240–960 MHz
Sensitivity = –118 dBm
Low Power Consumption
18.5 mA receive
Data Rate = 1 to 128 kbps
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-up timer
Auto-frequency calibration (AFC)
Clear channel assessment
Programmable RX BW 2.6–620 kHz
Programmable packet handler
Programmable GPIOs
Embedded antenna diversity
algorithm
Configurable packet structure
Preamble detector
RX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
FSK, GFSK, and OOK modulation
Low BOM
Power-on-reset (POR)
Remote control
Home security & alarm
Teleme tr y
Personal data logging
Toy control
Tire pressure monitoring
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
Patents pending
Ordering Information:
See page 139.
Pin Assignments
VDD_RF 1
2
3
4
15
14
13
12
6789
19 18 1720
NC
RXp
RXn
SCLK
SDI
SDO
VDD_DIG
NC
GPIO_0 GPIO_1 GPIO_2
XIN XOUT SDN nIRQ
Metal
Paddle
511VR_IF NC
10
16
VDR nSEL
Si4330

Si4330
2 Preliminary Rev 0.2
Functional Block Diagram
LPF CP
N
Mixers PGA
AGC Control
VCO
SPI, & Controller
Digital Logic
PFD
RFn
GPIO_2 GPIO_1 Xout
Xin
Digital Modem
Digital LDO
RC 32K OSC
30M XTAL
OSC
RF LDO
IF LDO
VCO LDO PLL LDO
BIAS
SDN
ANTDIV
Low Power
Digital LDO
POR
Temp
Sensor
VR_DIG
GPIO_0
VDD_DIG
SDO
SDI
SCLK
VDD_DIG
VR_IF
LBD
nSEL
VDD_RF
8Bit
ADC
RFp ADC

Si4330
Preliminary Rev 0.2 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.3. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Si4330
4 Preliminary Rev 0.2
8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Si4330
Preliminary Rev 0.2 5
LIST OF FIGURES
Figure 1. RX Application Example............................................................................................ 14
Figure 2. SPI Timing..................................................................................................................16
Figure 3. SPI Timing—READ Mode ..........................................................................................17
Figure 4. SPI Timing—Burst Write Mode ..................................................................................17
Figure 5. SPI Timing—Burst Read Mode ..................................................................................17
Figure 6. State Machine Diagram..............................................................................................18
Figure 7. RX Timing ..................................................................................................................22
Figure 8. Frequency Deviation ..................................................................................................26
Figure 9. Sensitivity at 1% PER vs. Carrier Frequency Offset ..................................................27
Figure 10. PLL Synthesizer Block Diagram...............................................................................31
Figure 11. FIFO Threshold........................................................................................................33
Figure 12. Packet Structure.......................................................................................................34
Figure 13. Required RX Packet Structure with Packet Handler Disabled .................................34
Figure 14. Multiple Packets in RX Packet Handler....................................................................35
Figure 15. Multiple Packets in RX with CRC or Header Error ...................................................35
Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37
Figure 17. POR Glitch Parameters............................................................................................45
Figure 18. General Purpose ADC Architecture .........................................................................47
Figure 19. ADC Differential Input Example—Bridge Sensor .....................................................48
Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................49
Figure 21. Temperature Ranges using ADC8 ...........................................................................51
Figure 22. WUT Interrupt and WUT Operation..........................................................................54
Figure 23. Low Duty Cycle Mode ..............................................................................................55
Figure 24. RSSI Value vs. Input Power.....................................................................................58
Figure 25. Receiver—Schematic...............................................................................................59
Figure 26. Receiver—Top .........................................................................................................61
Figure 27. Receiver—Top Silkscreen........................................................................................61
Figure 28. Receiver—Bottom ....................................................................................................62
Figure 29. Sensitivity vs. Data Rate ..........................................................................................63
Figure 30. Receiver Selectivity..................................................................................................64
Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ...........................65
Figure 32. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 65
Figure 33. RX LNA Matching.....................................................................................................67
Figure 34. QFN-20 Package Dimensions................................................................................140
Figure 35. QFN-20 Landing Pattern Dimensions .................................................................... 140

Si4330
Preliminary Rev 0.2 6
LIST OF TABLES
Table 1. DC Characteristics .......................................................................................................7
Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8
Table 3. Receiver AC Electrical Characteristics1.......................................................................9
Table 4. Auxiliary Block Specifications1 ...................................................................................10
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ...................................11
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ..............................................11
Table 7. Absolute Maximum Ratings ........................................................................................12
Table 8. Operating Modes ........................................................................................................15
Table 9. Serial Interface Timing Parameters ............................................................................16
Table 10. Operating Modes ......................................................................................................18
Table 11. Frequency Band Selection .......................................................................................24
Table 12. RX Packet Handler Configuration ............................................................................35
Table 13. Packet Handler Registers .........................................................................................36
Table 14. Minimum Receiver Settling Time ..............................................................................38
Table 15. RX Modem Configurations for FSK and GFSK ........................................................39
Table 16. Filter Bandwidth Parameters ....................................................................................41
Table 17. Channel Filter Bandwidth Settings ...........................................................................42
Table 18. ndec[2:0] Settings .....................................................................................................43
Table 19. RX Modem Configuration for OOK with Manchester Disabled .................................44
Table 20. RX Modem Configuration for OOK with Manchester Enabled .................................44
Table 21. POR Parameters ......................................................................................................45
Table 22. Temperature Sensor Range .....................................................................................50
Table 23. Antenna Diversity Control ......................................................................................... 57
Table 24. Receiver Bill of Materials ..........................................................................................60
Table 25. Recommended Crystal Parameters .........................................................................66
Table 26. RX Matching for Different Bands ..............................................................................67
Table 27. Register Descriptions ...............................................................................................68
Table 28. Interrupt or Status 1 Bit Set/Clear Description .........................................................73
Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? .............73
Table 30. Interrupt or Status 2 Bit Set/Clear Description ........................................................75
Table 31. Detailed Description of Status Registers when not Enabled as Interrupts ...............75
Table 32. Internal Analog Signals Available on the Analog Test Bus ....................................114
Table 33. Internal Digital Signals Available on the Digital Test Bus .......................................115

Si4330
Preliminary Rev 0.2 7
1. Electrical Specifications
Table 1. DC Characteristics
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage Range Vdd 1.8 3.0 3.6 V
Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF2—10TBDnA
IStandby Low Power Digital Regulator ON (Register values retained)
and Main Digital Regulator, and RC Oscillator OFF1—400— nA
ISleep RC Oscillator and Low Power Digital Regulator ON
(Register values retained) and Main Digital Regulator OFF1—800— nA
ISensor-LBD Main Digital Regulator and Low Battery Detector ON,
Crystal Oscillator and all other blocks OFF2—1—µA
ISensor-TS Main Digital Regulator and Temperature Sensor ON,
Crystal Oscillator and all other blocks OFF2—1—µA
IReady Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF. Crystal Oscillator buffer disabled1—600— µA
TUNE Mode Current ITune Synthesizer and regulators enabled — 9.5 — mA
RX Mode Current IRX —18.5— mA
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4330
8 Preliminary Rev 0.2
Table 2. Synthesizer AC Electrical Characteristics1
Parameter Symbol Conditions Min Typ Max Units
Synthesizer Frequency
Range
FSYNTH-LB Low Band 240 — 480 MHz
FSYNTH-HB High Band 480 — 960 MHz
Synthesizer Frequency
Resolution2
FRES-LB Low Band — 156.25 — Hz
FRES-HB High Band — 312.5 — Hz
Reference Frequency fREF fcrystal /3 — 10 — MHz
Reference Frequency
Input Level2
fREF_LV When using reference frequency instead
of crystal. Measured peak-to-peak (VPP)
0.7 — 1.6 V
Synthesizer Settling Time2tLOCK Measured from leaving Ready mode with
XOSC running to any frequency includ-
ing VCO Calibration
—200— µs
Residual FM2FRMS Integrated over 250 kHz bandwidth
(500 Hz lower bound of integration)
—2 4kHz
RMS
Phase Noise2L(fM)F = 10 kHz — –80 — dBc/Hz
F = 100 kHz — –90 — dBc/Hz
F = 1 MHz — –115 — dBc/Hz
F = 10 MHz — –130 — dBc/Hz
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4330
Preliminary Rev 0.2 9
Table 3. Receiver AC Electrical Characteristics1
Parameter Symbol Conditions Min Typ Max Units
RX Frequency
Range
FSYNTH-LB Low Band 240 — 480 MHz
FSYNTH-HB High Band 480 — 960 MHz
RX Sensitivity PRX_2 (BER < 0.1%)
(2 kbps, GFSK, BT = 0.5,
f = 5kHz)
2
—–118—dBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)2
— –107 —dBm
PRX_100 (BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)2
— –103 —dBm
PRX_125 (BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)1
— –101 —dBm
PRX_OOK (BER < 0.1%)
(4.8 kbps, 350 kHz BW, OOK)2
—–110—dBm
(BER < 0.1%)
(40kbps,400kHzBW,OOK)
1
— –102 —dBm
RX Bandwidth2BW 2.6 — 620 kHz
Residual BER
Performance2
PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm
Input Intercept Point,
3rd Order2
IIP3RX f1= 915 MHz, f2= 915 MHz,
P1= P2= –40 dBm
—–20—dBm
LNA Input Impedance2
(Unmatched, measured
differentially across RX
input pins)
RIN-RX 915 MHz — 40–55j — 
868 MHz — 44–58j —
433 MHz — 79–110j —
315 MHz — 96–134j —
RSSI Resolution RESRSSI — ±0.5 — dB
1-Ch Offset Selectivity2
(BER < 0.1%)
C/I1-CH Desired Ref Signal 3 dB above sensitivity.
Interferer and desired modulated with
40 kbps F = 20 kHz GFSK with BT = 0.5,
channel spacing = 150 kHz
—–31—dB
2-Ch Offset Selectivity2
(BER < 0.1%)
C/I2-CH —–35—dB
3-Ch Offset Selectivity2
(BER < 0.1%)
C/I3-CH —–40—dB
Blocking at 1 MHz21MBLOCK Desired Ref Signal 3 dB above sensitivity.
Interferer and desired modulated with
40 kbps F = 20 kHz GFSK with BT = 0.5
—–52—dB
Blocking at 4 MHz24MBLOCK —–56—dB
Blocking at 8 MHz28MBLOCK —–63—dB
Image Rejection2ImREJ IF=937 kHz — –30 — dB
Spurious Emissions2POB_RX1 Measured at RX pins
(LO feed through)
— — –54 dBm
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4330
10 Preliminary Rev 0.2
Table 4. Auxiliary Block Specifications1
Parameter Symbol Conditions Min Typ Max Units
Temperature Sensor
Accuracy2
TSAWhen calibrated using temp
sensor offset register
—0.5—°C
Temperature Sensor
Sensitivity2
TSS—5—mV/°C
Low Battery Detector
Resolution2
LBDRES —50—mV
Low Battery Detector
Conversion Time2
LBDCT —250—µs
Microcontroller Clock
Output Frequency
MC Configurable to 30 MHz,
15 MHz, 10 MHz, 4 MHz,
3MHz,2MHz,1MHz,or
32.768 kHz
32.768K — 30M Hz
General Purpose ADC
Accuracy2
ADCENB —8—bit
General Purpose ADC
Resolution2
ADCRES —4—mV
Temp Sensor & General
Purpose ADC Conversion
Time2
ADCCT — 305 — µsec
30 MHz XTAL Start-Up time t30M —1—ms
30 MHz XTAL Cap
Resolution2
30MRES —97—fF
32 kHz XTAL Start-Up Time2t32k —6—sec
32 kHz XTAL Accuracy232KRES —100—ppm
32 kHz RC OSC Accuracy232KRCRES —2500—ppm
POR Reset Time tPOR —16—ms
Software Reset Time2tsoft —100—µs
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4330
Preliminary Rev 0.2 11
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter Symbol Conditions Min Typ Max Units
Rise Time TRISE 0.1 x VDD to 0.9 x VDD, CL= 5 pF — — 8 ns
Fall Time TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF — — 8 ns
Input Capacitance CIN ——1pF
Logic High Level Input Voltage VIH VDD –0.6 — — V
Logic Low Level Input Voltage VIL —0.6 V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Logic High Level Output
Voltage
VOH IOH<1 mA source, VDD=1.8 V VDD –0.6 — — V
Logic Low Level Output Voltage VOL IOL<1 mA sink, VDD=1.8 V — — 0.6 V
Note: All specification guaranteed by production test unless otherwise noted.
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter Symbol Conditions Min Typ Max Units
Rise Time TRISE 0.1 x VDD to 0.9 x VDD,
CL= 10 pF, DRV<1:0>=HH
——8ns
Fall Time TFALL 0.9 x VDD to 0.1 x VDD,
CL= 10 pF, DRV<1:0>=HH
——8ns
Input Capacitance CIN ——1pF
Logic High Level Input Voltage VIH VDD –0.6 — V
Logic Low Level Input Voltage VIL ——0.6V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Input Current If Pullup is Activated IINP VIL=0 V 5 — 25 µA
Maximum Output Current IOmaxLL DRV<1:0>=LL 0.1 0.5 0.8 mA
IOmaxLH DRV<1:0>=LH 0.9 2.3 3.5 mA
IOmaxHL DRV<1:0>=HL 1.5 3.1 4.8 mA
IOmaxHH DRV<1:0>=HH 1.8 3.6 5.4 mA
Logic High Level Output Voltage VOH IOH< IOmax source,
VDD=1.8 V
VDD –0.6 — — V
Logic Low Level Output Voltage VOL IOL< IOmax sink,
VDD=1.8 V
——0.6V
Note: All specification guaranteed by production test unless otherwise noted.

Si4330
12 Preliminary Rev 0.2
Table 7. Absolute Maximum Ratings
Parameter Value Unit
VDD to GND –0.3, +3.6 V
Voltage on Digital Control Inputs –0.3, VDD + 0.3 V
Voltage on Analog Inputs –0.3, VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA–40 to +85 C
Thermal Impedance JA 30 C/W
Junction Temperature TJ+125 C
Storage Temperature Range TSTG –55 to +125 C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Caution: ESD sensitive device.

Si4330
Preliminary Rev 0.2 13
1.1. Definition of Test Conditions
Production Test Conditions:
TA=+25°C
VDD =+3.3VDC
External reference signal (XIN) = 1.0 VPP at 30 MHz, centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si4330 (not the RF module)
Extreme Test Conditions:
TA= –40 to +85 °C
VDD = +1.8 to +3.6 VDC
External reference signal (XIN) = 0.7 to 1.6 VPP at 30 MHz centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si4330 (not the RF module)
Test Notes:
All electrical parameters with Min/Max values are guaranteed by one (or more) of the following test methods.
Electrical parameters shown with only Typical values are not guaranteed.
Guaranteed by design and/or simulation but not tested.
Guaranteed by Engineering Qualification testing at Extreme Test Conditions.
Guaranteed by 100% Production Test Screening at Production Test Conditions.

Si4330
14 Preliminary Rev 0.2
2. Functional Description
The Si4330 is a 100% CMOS ISM wireless receiver with continuous frequency tuning over the complete
240–960 MHz band. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the
Si4330 and ideal solution for battery powered applications.
The Si4330 receiver uses a single-conversion, image-reject mixer to downconvert the 2-level FSK/GFSK/OOK
modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is
converted to the digital domain by a high performance  ADC allowing filtering, demodulation, slicing, error
correction, and packet handling to be performed in the built-in DSP increasing the receiver’s performance and
flexibility versus analog based architectures. The demodulated signal is then output to the system MCU through a
programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO.
A high precision local oscillator (LO) is generated by an integrated VCO and  Fractional-N PLL synthesizer. The
synthesizer is designed to support configurable data rates, output frequency, frequency deviation, and Gaussian
filtering at any frequency between 240–960 MHz.
The Si4330 supports frequency hopping and antenna diversity switch control to extend the link range and improve
performance. Antenna diversity is completely integrated into the Si4330 and can improve the system link budget by
8–10 dB, resulting in substantial range increases depending on the environmental conditions.
The Si4330 is designed to work with a microcontroller, crystal, and a few passives to create a very low cost system.
Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from
+1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with the microcontroller. Three configurable
general purpose I/Os are available for use to tailor towards the needs of the system. A more complete list of the
available GPIO functions is shown in "8. Auxiliary Functions" on page 45 but just to name a few, microcontroller
clock output, Antenna Diversity, Antenna SwitchPOR, and specific interrupts. A limited number of passive
components are needed to match the LNA. Figure 25, “Receiver—Schematic,” on page 59
The application shown in Figure 1 is designed for a system with . The Antenna Diversity Control Algorithm is
completely integrated into the chip.
Figure 1. RX Application Example
X1
30 MHz
Supply Voltage
Microcontroller
VDD
VSS
GP1
GP2
GP3
GP4
100 n
C4
100 p
C5
C3
1 u
L1, C1, and C2 values depend on frequency band, and antenna
impedance.
Programmable load capacitors for X1 are integrated.
VDD_RF SCLK
19 18 17 16
1
2
3
4
15
14
13
7 8 9
10
SDI
SDO
VDD_D
RXn
NC
RFp
GPIO0 GPIO1
VDR
nIRQ
SDN
XOUT
nSEL
GPIO2
5
VR_IF
6
NC
NC
20
XIN
11
12
C10
GP5
1 u
C6
1 u
L1
C1
C2
Si4330

Si4330
Preliminary Rev 0.2 15
2.1. Operating Modes
The Si4330 provides several modes of operation which can be used to optimize the power consumption of the
device application. Depending upon the system communication protocol, the optimal trade-off between the radio
wake time and power consumption can be achieved.
Table 8 summarizes the modes of operation of the Si4330. In general, any given mode of operation may be
classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in
each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the
appropriate commands over the SPI in order to optimize the average current consumption. An “X” in any cell
means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF,
without noticeably affecting the current consumption. The SPI circuit block includes the SPI interface and the
register space. The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal
oscillator, and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and
low-battery detector.
Table 8. Operating Modes
Mode
Name Circuit Blocks
Digital LDO SPI 32 kHz OSC AUX 30 MHz
XTAL PLL RX IVDD
Shutdown OFF
(Register contents lost)
OFF OFF OFF OFF OFF OFF 10 nA
Standby ON
(Register contents retained)
ON OFF OFF OFF OFF OFF 400 nA
Sleep ON ON X OFF OFF OFF 800 nA
Sensor ON X ON OFF OFF OFF 1 µA
Ready ON X X ON OFF OFF 600 µA
Tuning ON X X ON ON OFF 9.5 mA
Receive ON X X ON ON ON 18.5 mA

Si4330
16 Preliminary Rev 0.2
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4330 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU
can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA),
as demonstrated in Figure 2. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control
registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it
signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are
latched into the Si4330 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9.
The SCLK rate is flexible with a maximum rate of 10 MHz.
Figure 2. SPI Timing
To read back data from the Si4330, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative
edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the
selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After the READ
function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit
clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Table 9. Serial Interface Timing Parameters
Symbol Parameter Min (nsec) Diagram
tCH Clock high time 40
tCL Clock low time 40
tDS Data setup time 20
tDH Data hold time 20
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50
tSS Select setup time 20
tSH Select hold time 50
tSW Select high period 80
nSEL
SCLK
SDI
MSB
LSB
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1
D0
A4
xx
xx
A3 RW A7A6
A5
RW
Data
Address
SDI
SCLK
SDO
nSEL
tCL tCH
t
DS tDH tDD
tSS
t
E
N
tSH
t
DE
t
SW

Si4330
Preliminary Rev 0.2 17
Figure 3. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write
transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be
latched into the Si4330 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5.
Figure 4. SPI Timing—Burst Write Mode
Figure 5. SPI Timing—Burst Read Mode
nSEL
SCLK
SDI
First Bit
Last Bit
A0
D7
=X
SDO D7
A1A2
First Bit
Last Bit
A3
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
D6 D5 D4 D3 D2 D1 D0
A4
A5
A6
RW
=0
nSEL
SCLK
SDI
First Bit
A0
D7
=X
A1
A2
A3
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
A4
A5
A6
RW
=1
Last Bit
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
nSEL
SCLK
SDI
First Bit
Last Bit
A0
D7
=X
SDO D7
A1
A2
First Bit
A3
D6
=X
D
5
=X
D
4
=X
D3
=X
D2
=X
D1
=X
D0
=X
D6 D5 D4 D3 D2 D1 D0
A4
A5
A6
RW
=0
D7 D6 D5 D4
D3
D2
D1 D0

Si4330
18 Preliminary Rev 0.2
3.2. Operating Mode Control
There are three primary states in the Si4330 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The
SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different
configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs.
"Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected. The RX
state may be reached automatically from any of the IDLE states by setting the rxon bit in "Register 07h. Operating
Mode and Function Control 1". Table 10 shows each of the operating modes with the time required to reach RX
mode as well as the current consumption of each mode.
The output of the LPLDO is internally connected in parallel to the output of the main digital regulator (and is
available externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks,
including the digital modem, crystal oscillator, and SPI and register space. The LPLDO has extremely low
quiescent current consumption but limited current supply capability; it is used only in the IDLE-STANDBY and
IDLE-SLEEP modes.
Figure 6. State Machine Diagram
Table 10. Operating Modes
State/Mode xtal pll wt LBD or TS Response Time to RX Current in State /Mode [µA]
Shut Down State X X X X 16.21 ms 10 nA
Idle States:
Standby Mode
Sleep Mode
Sensor Mode
Ready Mode
Tune Mode
0
0
0
1
1
0
0
0
0
1
0
1
X
X
X
0
0
1
X
X
1.21 ms
210 µs
200 µs
400 nA
800 nA
1µA
600 µA
9.5 mA
RX State 1 1 X X NA 18.5 mA
SHUT DWN
IDLE*
RX
*Four Differe nt Options for IDLE

Si4330
Preliminary Rev 0.2 19
3.2.1. Shutdown State
The shutdown state is the lowest current consumption state of the device with nominally less than 10 nA of current
consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be
held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost
and there is no SPI access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN.
3.2.2. Idle State
There are four different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and
Function Control 1". All modes have a tradeoff between current consumption and response time to RX mode. This
tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will
default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the
SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly.
3.2.2.1. STANDBY Mode
STANDBY mode has the lowest current consumption possible with only the LPLDO enabled to maintain the
register values. In this mode the registers can be accessed in both read and write mode. The standby mode can be
entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e.,
the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally,
the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption.
3.2.2.2. SLEEP Mode
In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up
the radio at specified intervals. See "8.6. Wake-Up Timer" on page 53 for more information on the Wake-Up-Timer.
Sleep mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an
interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current
consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess
current consumption.
3.2.2.3. SENSOR Mode
In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the
LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 and the temperature
sensor can be enabled by setting ents = 1 in "Register 07h. Operating Mode and Function Control 1". See "8.4.
Temperature Sensor" on page 50 and "8.5. Low Battery Detector" on page 52 for more information on these
features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the
minimum current consumption.
3.2.2.4. READY Mode
READY Mode is designed to give a fast transition time to RX mode with reasonable current consumption. In this
mode the Crystal oscillator remains enabled reducing the time required to switch to the RX mode by eliminating the
crystal start-up time. Ready mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function
Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled. This is
done by setting "Register 62h. Crystal Oscillator/Power-on-Reset Control" to a value of 02h. To exit ready mode,
bufovr (bit 1) of this register must be set back to 0.
3.2.2.5. TUNE Mode
In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give
the fastest response to RX mode as the PLL will remain locked but it results in the highest current consumption.
This mode of operation is designed for Frequency Hopping Systems (FHS). Tune mode is entered by setting pllon
= 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the
internal state machine automatically enables the crystal oscillator.
3.2.3. RX State
The RX state may be entered from any of the Idle modes when the rxon bit is set to 1 in "Register 07h. Operating
Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of
the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX
mode when going from STANDBY mode to RX mode by setting the rxon bit:

Si4330
20 Preliminary Rev 0.2
1. Enable the Main Digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”).
5. Wait until PLL settles to required receive frequency (controlled by timer).
6. Enable receive circuits: LNA, mixers, and ADC.
7. Calibrate ADC (RC calibration).
8. Enable receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed automatically by
the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional)
including sync word, header check, and CRC.
3.2.4. Device Status
The operational status of the chip can be read from "Register 02h. Device Status".
Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.
02 R Device Status ffovfl ffunfl rxffem headerr cps[1] cps[0] —