SONIX SN8P2711A User manual

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version0.1
SN8P2711A
USER’S MANUAL
Version 0.1
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version0.1
AMENDENT HISTORY
Version Date Description
VER 0.1 Jun. 2007 First issue.

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version0.1
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1PRODUCT OVERVIEW................................................................................................................. 7
1.1 FEATURES........................................................................................................................................ 7
1.2 SYSTEM BLOCK DIAGRAM.......................................................................................................... 9
1.3 PIN ASSIGNMENT......................................................................................................................... 10
1.4 PIN DESCRIPTIONS....................................................................................................................... 11
1.5 PIN CIRCUIT DIAGRAMS............................................................................................................. 12
2
2
2CENTRAL PROCESSOR UNIT (CPU) ...................................................................................... 14
2.1 MEMORY MAP............................................................................................................................... 14
2.1.1 PROGRAM MEMORY (ROM)............................................................................................... 14
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 15
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 16
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 18
2.1.1.4 JUMP TABLE DESCRIPTION........................................................................................... 20
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 22
2.1.2 CODE OPTION TABLE.......................................................................................................... 23
2.1.3 DATA MEMORY (RAM) ....................................................................................................... 24
2.1.4 SYSTEM REGISTER .............................................................................................................. 25
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 25
2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 25
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 26
2.1.4.4 ACCUMULATOR ............................................................................................................... 27
2.1.4.5 PROGRAM FLAG............................................................................................................... 28
2.1.4.6 PROGRAM COUNTER....................................................................................................... 29
2.1.4.7 Y, Z REGISTERS................................................................................................................. 32
2.1.4.8 R REGISTERS..................................................................................................................... 33
2.2 ADDRESSING MODE .................................................................................................................... 34
2.2.1 IMMEDIATE ADDRESSING MODE.................................................................................... 34
2.2.2 DIRECTLY ADDRESSING MODE ....................................................................................... 34
2.2.3 INDIRECTLY ADDRESSING MODE................................................................................... 34
2.3 STACK OPERATION...................................................................................................................... 35
2.3.1 OVERVIEW............................................................................................................................. 35
2.3.2 STACK REGISTERS............................................................................................................... 36
2.3.3 STACK OPERATION EXAMPLE.......................................................................................... 37
3
3
3RESET............................................................................................................................................. 38

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version0.1
3.1 OVERVIEW..................................................................................................................................... 38
3.2 POWER ON RESET......................................................................................................................... 39
3.3 WATCHDOG RESET...................................................................................................................... 39
3.4 BROWN OUT RESET ..................................................................................................................... 40
3.4.1 BROWN OUT DESCRIPTION............................................................................................... 40
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION................................................... 41
3.4.3 BROWN OUT RESET IMPROVEMENT .............................................................................. 41
3.5 EXTERNAL RESET........................................................................................................................ 44
3.6 EXTERNAL RESET CIRCUIT ....................................................................................................... 44
3.6.1 Simply RC Reset Circuit .......................................................................................................... 44
3.6.2 Diode & RC Reset Circuit........................................................................................................ 45
3.6.3 Zener Diode Reset Circuit........................................................................................................ 45
3.6.4 Voltage Bias Reset Circuit ....................................................................................................... 46
3.6.5 External Reset IC...................................................................................................................... 47
4
4
4SYSTEM CLOCK.......................................................................................................................... 48
4.1 OVERVIEW..................................................................................................................................... 48
4.2 CLOCK BLOCK DIAGRAM .......................................................................................................... 48
4.3 OSCM REGISTER........................................................................................................................... 49
4.4 SYSTEM HIGH CLOCK ................................................................................................................. 50
4.4.1 INTERNAL HIGH RC............................................................................................................. 50
4.4.2 EXTERNAL HIGH CLOCK.................................................................................................... 50
4.4.2.1 CRYSTAL/CERAMIC......................................................................................................... 51
4.4.2.2 RC......................................................................................................................................... 51
4.4.2.3 EXTERNAL CLOCK SIGNAL........................................................................................... 52
4.5 SYSTEM LOW CLOCK.................................................................................................................. 53
4.5.1 SYSTEM CLOCK MEASUREMENT .................................................................................... 54
5
5
5SYSTEM OPERATION MODE................................................................................................... 56
5.1 OVERVIEW..................................................................................................................................... 56
5.2 SYSTEM MODE SWITCHING EXAMPLE................................................................................... 57
5.3 WAKEUP......................................................................................................................................... 59
5.3.1 OVERVIEW............................................................................................................................. 59
5.3.2 WAKEUP TIME ...................................................................................................................... 59
6
6
6INTERRUPT................................................................................................................................... 60
6.1 OVERVIEW..................................................................................................................................... 60
6.2 INTEN INTERRUPT ENABLE REGISTER................................................................................... 61
6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 62
6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 63
6.5 PUSH, POP ROUTINE .................................................................................................................... 64

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8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version0.1
6.6 INT0 (P0.0) INTERRUPT OPERATION......................................................................................... 65
6.7 INT1 (P0.1) INTERRUPT OPERATION......................................................................................... 67
6.8 TC0 INTERRUPT OPERATION..................................................................................................... 68
6.9 TC1 INTERRUPT OPERATION..................................................................................................... 69
6.10 ADC INTERRUPT OPERATION ................................................................................................... 71
6.11 MULTI-INTERRUPT OPERATION............................................................................................... 72
7
7
7I/O PORT........................................................................................................................................ 73
7.1 I/O PORT MODE ............................................................................................................................. 73
7.2 I/O PULL UP REGISTER ................................................................................................................ 74
7.3 I/O PORT DATA REGISTER.......................................................................................................... 75
7.4 PORT 4ADC SHARE PIN............................................................................................................... 76
8
8
8TIMERS .......................................................................................................................................... 80
8.1 WATCHDOG TIMER...................................................................................................................... 80
8.2 TIMER/COUNTER 0(TC0) ............................................................................................................ 83
8.2.1 OVERVIEW............................................................................................................................. 83
8.2.2 TC0M MODE REGISTER....................................................................................................... 84
8.2.3 TC1X8, TC0X8, TC0GN FLAGS............................................................................................ 85
8.2.4 TC0C COUNTING REGISTER .............................................................................................. 85
8.2.5 TC0R AUTO-LOAD REGISTER............................................................................................ 87
8.2.6 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 88
8.2.7 TC0 TIMER OPERATION SEQUENCE................................................................................ 89
8.3 TIMER/COUNTER 1(TC1) ............................................................................................................ 91
8.3.1 OVERVIEW............................................................................................................................. 91
8.3.2 TC1M MODE REGISTER....................................................................................................... 92
8.3.3 TC1X8 FLAG........................................................................................................................... 92
8.3.4 TC1C COUNTING REGISTER .............................................................................................. 93
8.3.5 TC1R AUTO-LOAD REGISTER............................................................................................ 95
8.3.6 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 96
8.3.7 TC1 TIMER OPERATION SEQUENCE................................................................................ 97
8.4 PWM MODE.................................................................................................................................... 99
8.4.1 OVERVIEW............................................................................................................................. 99
8.4.2 TCnIRQ and PWM Duty........................................................................................................ 100
8.4.3 PWM Duty with TCnR Changing.......................................................................................... 101
8.4.4 PWM PROGRAM EXAMPLE.............................................................................................. 102
9
9
95+1 CHANNEL ANALOG TO DIGITAL CONVERTER....................................................... 103
9.1 OVERVIEW................................................................................................................................... 103
9.2 ADM REGISTER........................................................................................................................... 104
9.3 ADR REGISTERS.......................................................................................................................... 105

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8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version0.1
9.4 ADB REGISTERS.......................................................................................................................... 106
9.5 P4CON REGISTERS ..................................................................................................................... 107
9.6 VREFH REGISTERS..................................................................................................................... 108
9.7 ADC CONVERTING TIME .......................................................................................................... 109
9.8 ADC ROUTINE EXAMPLE.......................................................................................................... 110
9.9 ADC CIRCUIT............................................................................................................................... 112
1
1
10
0
0INSTRUCTION TABLE ..................................................................................................... 113
1
1
11
1
1ELECTRICAL CHARACTERISTIC................................................................................ 114
11.1 ABSOLUTE MAXIMUM RATING.............................................................................................. 114
11.2 ELECTRICAL CHARACTERISTIC............................................................................................. 114
1
1
12
2
2DEVELOPMENT TOOL VERSION................................................................................. 117
12.1 ICE (IN CIRCUIT EMULATION)......................................................................................................... 117
12.2 OTP WRITER ................................................................................................................................ 117
12.3 SN8IDE .......................................................................................................................................... 117
12.4 SN8P2711 EV KIT ......................................................................................................................... 118
12.4.1 PCB DESCRIPTION.............................................................................................................. 118
12.4.2 SN8P2711 EV KIT CONNECT TO SN8ICE 2K.................................................................. 120
12.5 TRANSITION BOARD FOR OTP PROGRAMMING................................................................. 121
12.5.1 SN8P2711 V3 TRANSITION BOARD................................................................................. 121
12.5.2 SN8P2711 MP028A TRANSITION BOARD FOR EZ/MPEZ WRITER ............................ 122
12.5.3 SN8P2711 MP028A CONNECT TO EZ_MP WRITER....................................................... 123
12.5.4 SN8P2711 MP028A CONNECT TO EZ WRITER............................................................... 123
12.5.5 SN8P2711 V3 CONNECT TO EZ WRITER ........................................................................ 124
12.5.6 SN8P2711 V3 CONNECT TO EZ_MP WRITER................................................................. 124
12.6 OTP PROGRAMMING PIN.......................................................................................................... 125
12.6.1 EASY WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT........................... 125
12.6.2 PROGRAMMING PIN MAPPING:...................................................................................... 126
1
1
13
3
3PACKAGE INFORMATION ............................................................................................. 127
13.1 P-DIP 14 PIN.................................................................................................................................. 127
13.2 SOP 14 PIN..................................................................................................................................... 128
13.3 SSOP 16 PIN................................................................................................................................... 129
1
1
14
4
4MARKING DEFINITION................................................................................................... 130
14.1 INTRODUCTION.......................................................................................................................... 130
14.2 MARKING INDETIFICATION SYSTEM.................................................................................... 130
14.3 MARKING EXAMPLE ................................................................................................................. 131
14.4 DATECODE SYSTEM.................................................................................................................. 131

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version0.1
1
1
1 PRODUCT OVERVIEW
SN8P2711A is modified from SN8P2711. Good internal high RC frequency 16MHz±2%. Good high
noisy protecting performance for household application.
zSN8P2711 is compatible to SN8P2711A.
zBetter IHRC performance from 16MHz±5% to 16MHz±2%.
zGood brown out reset production.
zSN8P2711 code can transfer to SN8P2711A directly. Program the original SN8 of SN8P2711
into SN8P2711A directly without declare SN8P2711A in source code and re-compile again.
1.1 FEATURES
)Features Selection Table
Timer PWM
CHIP ROM RAM Stack TC0 TC1 I/O ADC Green
Mode Buzzer
Wakeup
Pin No. Package
SN8P2711 1K*16 64 4 V V 12 5+1 ch V 2 5 P-DIP 14/SOP 14/SSOP 16
SN8P2711A 1K*16 64 4 V V 12 5+1 ch V 2 5 P-DIP 14/SOP 14/SSOP 16
♦Memory configuration ♦5+1 channel 12-bit ADC.
OTP ROM size: 1K * 16 bits. Five external ADC input
RAM size: 64 * 8 bits. One internal battery measurement
Internal AD reference voltage (VDD, 4V, 3V ,2V).
♦Four levels stack buffer.
♦Two 8-bit Timer/Counter
♦I/O pin configuration TC0: Auto-reload timer/Counter/PWM0/Buzzer output.
Bi-directional: P0, P4, P5. TC1: Auto-reload timer/Counter/PWM1/Buzzer output.
Input only: P0.4 shared with reset pin.
Wakeup: P0 level change trigger. ♦On chip watchdog timer and clock source is internal
Pull-up resisters: P0, P4, P5. low clock RC type (16KHz @3V, 32KHz @5V).
External Interrupt trigger edge:
P0.0 controlled by PEDGE register. ♦Dual system clocks
P0.1 is falling edge trigger only. External high clock: RC type up to 10 MHz.
External high clock: Crystal type up to 16 MHz.
♦3-Level LVD. Internal high clock: 16MHz RC type.
Reset system and power monitor. Internal low clock: RC type 16KHz(3V), 32KHz(5V).
♦Five interrupt sources ♦Operating modes
Three internal interrupts: TC0, TC1, ADC. Normal mode: Both high and low clock active.
Two external interrupts: INT0, INT1. Slow mode: Low clock only.
Sleep mode: Both high and low clock stop.
♦Powerful instructions Green mode: Periodical wakeup by TC0 timer
One clocks per instruction cycle (1T)
Most of instructions are one cycle only. ♦Package (Chip form support)
All ROM area JMP instruction. P-DIP 14 pins
All ROM area CALL address instruction. SOP 14 pins
All ROM area lookup table function (MOVC). SSOP 16 pins

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version0.1
)Migration SN8P2711 to SN8P2711A
Item SN8P2711 SN8P2711A
PCL PCL can’t be written at 0xnnFE and
0xnnFF ROM address. No limitation.
32KHz oscillator mode Not support. Support 32KHz mode.
Firmware comparison
SN8P2711 SN8 file can program into
SN8P2711A OTP directly by EZ/MP
writer.
SN8P2711A SN8 file (e.g. Re-compile
SN8P2711 source code with declaring
S8P2711A, SN8P2711A new code... )
can't program into SN8P2711 OTP
directly by EZ/MP writer.

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version0.1
1.2 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
INTERNAL
HIGH RC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
LVD
(Low Voltage Detector)
WATCHDOG TIMER
PWM 1
BUZZER 1
TIMER & COUNTER
P0 P5 P4
12-BIT ADC
PWM 0
BUZZER 0
ALU
PC
FLAGS
IR
OTP
ROM
PWM0
PWM1
BUZZER0
BUZZER1
AIN0~AIN4
Internal
Reference
Internal ADC
Channel for
Battery Detect

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version0.1
1.3 PIN ASSIGNMENT
SN8P2711AP (P-DIP 14 pins)
SN8P2711AS (SOP 14 pins)
VDD 1 U 14 VSS
P0.3/XIN 2 13 P4.4/AIN4
P0.2/XOUT 3 12 P4.3/AIN3
P0.4/RST/VPP 4 11 P4.2/AIN2
P5.3/BZ1/PWM1 5 10 P4.1/AIN1
P5.4/BZ0/PWM0 6 9 P4.0/AIN0/VREFH
P0.1/INT1 7 8 P0.0/INT0
SN8P2711AP
SN8P2711AS
SN8P2711AX (SSOP 16 pins)
VDD 1 U 16 VSS
P0.3/XIN 2 15 P4.4/AIN4
P0.2/XOUT 3 14 P4.3/AIN3
P0.4/RST/VPP 4 13 P4.2/AIN2
P5.3/BZ1/PWM1 5 12 P4.1/AIN1
P5.4/BZ0/PWM0 6 11 P4.0/AIN0/VREFH
P0.1/INT1 7 10 P0.0/INT0
NC 8 9 NC
SN8P2711AX

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version0.1
1.4 PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
P0.4/RST/VPP I, P
P0.4: Input only pin (Schmitt trigger) if disable external reset function.
P0.4 without build-in pull-up resister.
P0.4 is input only pin without pull-up resistor under P0.4 mode. Add the 100
ohm external resistor on P0.4, when it is set to be input pin.
Built-in wakeup function.
RST: System reset input pin. Schmitt trigger structure, low active, normal stay to
“high”.
VPP: OTP programming pin.
P0.3/XIN I/O
Port 0.3 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
Oscillator input pin while external oscillator enable (crystal and RC).
P0.2/XOUT I/O
Port 0.2 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
XOUT: Oscillator output pin while external crystal enable.
P0.0/INT0 I/O
Port 0.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
INT0 trigger pin (Schmitt trigger).
TC0 event counter clock input pin.
P0.1/INT1 I/O
Port 0.1 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
INT1 trigger pin (Schmitt trigger).
TC1 event counter clock input pin.
P4.0/AIN0/VREFH I/O
Port 4.0 bi-direction pin. No Schmitt trigger structure.
Built-in pull-up resisters.
AIN0: ADC channel-0 input.
VREFH: ADC external high reference voltage input.
P4.[4:1]/AIN[4:1] I/O
Port 4 [4:1] bi-direction pins. No Schmitt trigger structure.
Built-in pull-up resisters.
AIN[4:1]: ADC channel-1~4 input.
P5.3/BZ1/PWM1 I/O
Port 5.3 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin.
P5.4/BZ0/PWM0 I/O
Port 5.4 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin.

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version0.1
1.5 PIN CIRCUIT DIAGRAMS
Port 0.2, P0.3 structure:
Oscillator
Code Option
Int. Osc.
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 0.4 structure:
Pin
Ext. Reset
Code Option
Int. Bus
Int. Rst
Port 0, 5 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version0.1
Port 4.0 structure:
Int. VERFH
Pin
EVHENB
GCHS
Int. ADC
P4CON
Pull-Up
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 4 structure:
GCHS
Int. ADC
P4CON
Pull-Up
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Pin

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version0.1
2
2
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
)1K words ROM
ROM
0000H Reset vector User reset vector
Jump to user start address
0001H
.
.
0007H
General purpose area
0008H Interrupt vector User interrupt vector
0009H User program
.
.
000FH
0010H
0011H
.
.
.
.
.
03FCH
General purpose area
End of user program
03FDH
03FEH
03FFH
Reserved

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version0.1
2.1.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
)Power On Reset (NT0=1, NPD=0).
)Watchdog Reset (NT0=0, NPD=0).
)External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
¾Example: Defining Reset Vector
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 10H
START: ; 0010H, The head of user program.
… ; User program
…
ENDP ; End of program

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version0.1
2.1.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
¾Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine
…
START: ; The head of user program.
… ; User program
…
JMP START ; End of user program
…
ENDP ; End of program

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version0.1
¾Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.
ORG 10H
START: ; 0010H, The head of user program.
… ; User program.
…
…
JMP START ; End of user program.
…
MY_IRQ: ;The head of interrupt service routine.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine.
…
ENDP ; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version0.1
2.1.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
¾Example: To look up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS Z ; Z+1
JMP @F ; Z is not overflow.
INCMS Y ; Z overflow (FFH Æ00), ÆY=Y+1
NOP ;
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
¾Example: INC_YZ macro.
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version0.1
¾Example: Modify above example by “INC_YZ” macro.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
INC_YZ ; Increment the index address for next address.
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
¾Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV Y, #TABLE1$M ; To set lookup table’s middle address.
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…

SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version0.1
2.1.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾Example: Jump table.
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
zExample: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.