Sony E01X23A41 User manual

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Sony reserves the right to change products and specifications without prior notice.This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX423AL
20 pin DIP (Ceramic)
Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras
Description
The ICX423AL is an interline CCD solid-state image
sensor suitable for CCIR B/W video cameras with a
diagonal 11mm (Type 2/3) system.Compared with the
current product ICX083AL, basic characteristics such
as sensitivity and smear are improved drastically and
high saturation characteristics are realized.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX083AL and has the same drive conditions.
Features
•High sensitivity (+3.0dB compared with the ICX083AL)
•Low smear (–10.0dB compared with the ICX083AL)
•High saturation signal (+2.0dB compared with the ICX083AL)
•High resolution and Low dark current
•Excellent antiblooming characteristics
•Continuous variable-speed shutter
Device Structure
•Interline CCD image sensor
•Optical size: Diagonal 11mm (Type 2/3)
•Number of effective pixels: 752 (H) ×582 (V) approx. 440K pixels
•Total number of pixels: 795 (H) ×596 (V) approx. 470K pixels
•Chip size: 10.25mm (H) ×8.5mm (V)
•Unit cell size: 11.6µm (H) ×11.2µm (V)
•Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
•Substrate material: Silicon
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 11 40
3

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ICX423AL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products.You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor.You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
•The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
•You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products.You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
•Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
•Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
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•If the Products are controlled items under the export control laws or regulations of various countries, approval
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•The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
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will not assume responsibility for any problems in connection with your use of such information or for any
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•This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
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Other ApplicableTerms and Conditions
•The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.

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ICX423AL
Block Diagram and Pin Configuration
(Top view)
Horizontal Register
Output Unit
Note)
Note) : Photo sensor
GND
V
DD
SUB
RG Hφ 1
Vertical Register
HIS
V OUT
Vφ 4
Vφ 3
Vφ 2
Vφ 1
V L
GND
V
GG
V SS
GND
RD Hφ 2 V L
7
9
10
11
12
13
14
15 16 17 18 19 20
6
5
4
3
2
1
Pin Description
Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
Vφ4
Vφ3
Vφ2
SUB
GND
Vφ1
VL
NC
GND
VDD
Signal output
Output amplifier gate bias
Output amplifier source
GND
Reset drain
Reset gate clock
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
Horizontal register input source bias
Description Pin No. Symbol
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate (overflow drain)
GND
Vertical register transfer clock
Protective transistor bias
GND
Output amplifier drain power
11
12
13
14
15
16
17
18
19
20
VOUT
VGG
VSS
GND
RD
RG
VL
Hφ1
Hφ2
HIS

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ICX423AL
Absolute Maximum Ratings
Item
HIS, VDD, RD, VOUT, VSS – GND
HIS, VDD, RD, VOUT, VSS – SUB
Vertical clock input pins – GND
Vertical clock input pins – SUB
Substrate voltage SUB – GND
Supply voltage
Vertical clock input
voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2– Vφ4
Hφ1, Hφ2, RG, VGG – GND
Hφ1, Hφ2, RG, VGG – SUB
VL– SUB
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL
RG – VL
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2– VL
Storage temperature
Operating temperature
–0.3 to +55
–0.3 to +20
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
Ratings Unit Remarks
∗127V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Output amplifier drain voltage
Reset drain voltage
Output amplifier gate voltage
Output amplifier source
Substrate voltage adjustment range
Substrate voltage adjustment precision
Reset gate clock voltage adjustment range
Reset gate clock voltage adjustment precision
Protective transistor bias
Horizontal register input source bias
Item
VDD
VRD
VGG
VSS
VSUB
∆VSUB
VRGL
∆VRGL
VL
VHIS
Symbol
14.7
14.7
3.8
9
–3
0
–3
–11
14.7
Min.
V
V
V
V
%
V
%
V
V
Unit
VRD = VDD
±5%
∗2
∗2
∗3
VHIS = VDD
RemarksTyp. Max.
15.0
15.0
4.2
–10.5
15.0
15.3
15.3
4.6
19
+3
3.0
+3
–10
15.3
Bias Conditions
Ground with 750Ωresistor

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ICX423AL
DC Characteristics
Output amplifier drain current
Input current
Input current
Item IDD
IIN1
IIN2
Symbol 6 Min. Unit RemarksTyp. Max. mA
µA
µA
1
10
∗2Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to
the indicated voltage.The adjustment precision is ±3%.
VSUB code — one character indication
VRGL code — one character indication ↑↑
VRGL code VSUB code
"Code" and optimal setting correspond to each other as follows.
<Example> "5K" →VRGL = 2.0V
VSUB = 12.0V
VSUB code
Optimal setting
D
9.0
∗4
∗5
E
9.5
f
10.0
G
10.5
h
11.0
J
11.5
K
12.0
L
12.5
m
13.0
N
13.5
P
14.0
Q
14.5
R
15.0
S
15.5
T
16.0
U
16.5
V
17.0
W
17.5
X
18.0
Y
18.5
Z
19.0
VRGL code
Optimal setting
1
0
2
0.5
3
1.0
4
1.5
5
2.0
6
2.5
7
3.0
∗3This must no exceed the VVL voltage of the vertical clock waveform.
∗41) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are
not tested are grounded.
2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3and Vφ4pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.
4) Current to VLpin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1and Hφ2pins, while VLpin is grounded.
However, GND and SUB pins are left open.
∗5Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.