Sony D-VE45 User manual
1
SERVICE MANUAL
E Model
Chinese Model
D-VE45
PORTABLE VIDEO CD PLAYER
Ver 1.0 2001.07
9-873-215-01
2001G0400-1
© 2001.7
Sony Corporation
Personal Audio Company
Shinagawa Tec Service Manual Production Group
Model Name Using Similar Mechanism D-E220/E225/E226CK
CD Mechanism Type CDM-3123EBA
Optical Pick-up Name DAX-23E
System
Compact disc digital audio/video system
Laser diode properties
Material: GaAlAs
Wavelength: λ= 780 nm
Emission duration: Continuous
Laser output: Less than 44.6 µW (This output
is the value measured at a distance of 200 mm
from the objective lens surface on the optical
pick-up block with 7 mm aperture.)
Error correction
Sony Super Strategy Cross Interleave Reed
Solomon Code
D-A conversion
1-bit quartz time-axis control
Channel number
2 channels
Frequency response
20 - 20,000 Hz +1/–2 dB
(measured by JEITA CP-307)
Output (at 4.5 V input level)
Audio output
Output level 0.7 V rms at 47 kilohms
Recommended load impedance over 10
kilohms
Video output
Output level 1 Vp-p at 75 ohms
Recommended load impedance 75 ohms
Headphones (stereo minijack)
Approx. 5 mW + Approx. 5 mW at 16 ohms
SPECIFICATIONS
Power requirements
For the area code of the model you purchased, check
the upper left side of the bar code on the package.
• Two LR6 (size AA) batteries: 3 V DC
• AC power adaptor (DC IN 4.5 V jack):
E13 model: 220 - 230 V, 50/60 Hz
CH model: 220 V, 50 Hz
HK model: 220 V, 50/60 Hz
Battery life *(approx. hours)
(When you use the VIDEO CD player on a flat and
stable surface.)
Playing time varies depending on how the CD
player is used.
VIDEO CD Audio CD
ESP ESP
ON OFF
Two Sony alkaline 2 30 24
batteries LR6SG
* Measured value by the standard of JEITA (Japan
Electronics and Information Technology
Industries Association).
Operating temperature
5°C - 35°C (41°F - 95°F)
Dimensions (w/h/d)
(excluding projecting parts and controls)
Approx. 152.4 ×25.4 ×152.4 mm
Mass (excluding accessories)
Approx. 226 g
Design and specifications are subject to change
without notice.
Supplied accessories
AC power adaptor AC-E455F (1) (E13, EA)
AC power adaptor AC-E455 (1) (CH, HK)
AV cable (1)
Wireless remote commander RMT-DV11 (1)
Earphones MDR-E805LP (1)
Stand (1)
AC plug adaptor (1) (EA)
• Abbreviation
CH : Chinese model
EA : Saudi Arabia model
E13 : AC 220 - 230V area in E model
HK : Hong Kong model
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2
Flexible Circuit Board Repairing
•Keep the temperature of the soldering iron around 270°C during
repairing.
•Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
•Be careful not to apply force on the conductor when soldering
or unsoldering.
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be
damaged by heat.
TABLE OF CONTENTS
1. SERVICE NOTE ................................................................. 3
2. GENERAL
Getting Started ......................................................................... 4
3. DISASSEMBLY
3-1. Lid Sub Assy, Upper ........................................................... 6
3-2. Cabinet (Front) Assy ........................................................... 6
3-3. Main Board, MD Assy ........................................................ 7
3-4. Optical Pick-up, Motor ....................................................... 7
4. ELECTRICAL ADJUSTMENTS
4-1. Precautions for Check ......................................................... 8
4-2. Focus Bias Check ................................................................ 8
5. DIAGRAMS
5-1. IC Pin Descriptions ............................................................. 9
5-2. Block Diagram –CD Section–........................................... 15
5-3. Block Diagram –Video Section–....................................... 16
5-4. Block Diagram –Audio Section–...................................... 17
5-5. Block Diagram –Power Supply Section–.......................... 18
5-6. Printed Wiring Boards –Main Section–............................ 20
5-7. Schematic Diagram –Main Section (1/3)–........................ 22
5-8. Schematic Diagram –Main Section (2/3)–........................ 23
5-9. Schematic Diagram –Main Section (3/3)–........................ 24
5-10. IC Block Diagrams ............................................................ 25
6. EXPLODED VIEWS
6-1. Cabinet (Front) Section ..................................................... 28
6-2. Cabinet (Rear) Section ...................................................... 29
6-3. CD Mechanism Deck Section (CDM-3123EBA) ............. 30
6-4. Stand (Set) Section ............................................................ 31
7. ELECTRICAL PARTS LIST......................................... 32
D-VE45
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK 0OR DOTTED LINE
WITH MARK 0ON THE SCHEMATIC DIAGRAMS AND IN
THE PARTS LIST ARE CRITICAL TO SAFE OPERATION.
REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE
PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR
IN SUPPLEMENTS PUBLISHED BY SONY.
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3
D-VE45
S801
(OPEN)
S801
– MAIN BOARD – (SIDE B)
TAP802
–MAIN BOARD –(SIDE A)
SECTION 1
SERVICE NOTE
NOTES ON HANDLING THE OPTICAL PICK-UP BLOCK
OR BASE UNIT
The laser diode in the optical pick-up block may suffer electro-
static breakdown because of the potential difference generated by
the charged electrostatic load, etc. on clothing and the human body.
During repair, pay attention to electrostatic breakdown and also
use the procedure in the printed matter which is included in the
repair parts.
The flexible board is easily damaged and should be handled with
care.
Precautions for Checking Emission of Laser Diode
Laser light of the equipment is focused by the object lens in the
optical pick-up so that the light focuses on the reflection surface
of the disc. Therefore, be sure to keep your eyes more then 30 cm
apart from the object lens when you check the emission of laser
diode.
Before Replacing the Optical Pick-Up Block
Please be sure to check throughly the parameters as par the “Opti-
cal Pick-Up Block Checking Procedures” (Part No.: 9-960-027-
11) issued separately before replacing the optical pick-up block.
Note and specifications required to check are given below.
• FOK output : IC601 eg pin
When checking FOK, remove the lead wire to disc motor.
• RF signal P-to-P value : 0.6 ± 0.2 Vp-p
• The repairing grating holder is impossible.
Laser Diode Checking Methods
During normal operation of the equipment, emission of the laser
diode is prohibited unless the upper lid is closed while turning ON
the S801. (push switch type)
The following two checking methods for the laser diode are
operable.
• Method:
Emission of the laser diode is visually checked.
1. Open the upper lid.
2. With a disc not set, turn on the S801 with a screwdriver having a
thin tip as shown in Fig.1.
or TAP802 is shorted as shown in Fig.2.
Note: Do not push the detection lever strongly, or it may be bent
or damaged.
3. Press the N>button.
4. Observing the objective lens, check that the laser diode emits
light.
When the laser diode does not emit light, automatic power
control circuit or optical pick-up is faulty.
In this operation, the objective lens will move up and down 5
times along with inward motion for the focus search.
Fig. 2
Fig. 1
detection lever
detection lever
main board
S801
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6
D-VE45
Note : Follow the disassembly procedure in the numerical order given.
3-2. CABINET (FRONT) ASSY
SECTION 3
DISASSEMBLY
3-1. LID SUB ASSY, UPPER
1
claws
2
lid sub assy, upper
cabinet (rear) assy
1
screws, tapping
2
screws (B2), tapping, P3
3
screws (B2), tapping, P3
4
screws (B2), tapping, P3
5
cabinet (front) ass
y
claws
claw
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7
D-VE45
3-3. MAIN BOARD, MD ASSY
1
CN501
6
MAIN board
4
MD assy
5
2
CN502
S803
3
CN503
1
B 1.7x5
3
B 1.7x5
7
P 1.4x3.5
9
B 1.4x2.3
q;
rack
8
retainer, shaf
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screw (feed) assy
qd
shaft, standard
qs
pick-up block, optical
4
cover, gear
2
motor assy, turntable (M502)
5
motor assy, sled (M501)
chassis
6
gear (B)
3-4. OPTICAL PICK-UP, MOTOR
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8
D-VE45
J302
TP629 (RF)
– MAIN BOARD – (SIDE B)
Procedure:
1. Connect the oscilloscope between TP629 (RF)
and GND on MAIN board.
2. Insert the disc (YEDS-18). (Part No. : 3-702-101-01)
3. Press the N > button.
4. Confirm that the oscilloscope waveform is as shown in the
figure below. (eye pattern)
A good eye pattern means that the diamond shape ( ) in the
center of the waveform can be clearly distinguished.
5. Stop revolving of the disc motor by pressing the xbutton.
• RF signal reference waveform (eye pattern)
SECTION 4
ELECTRICAL ADJUSTMENT
CD section adjustments are done automatically in this set.
In case of operation check, confirm that focus bias.
4-1. PRECAUTIONS FOR CHECK
1. Perform check in the order given.
2. Use YEDS-18 disc (Part No.: 3-702-101-01) unless otherwise
indicated.
3. Power supply voltage requirement: DC 4.5 V in DC IN jack.
(J401)
VOLUME button : Minimum
HOLD switch : OFF
4-2. FOCUS BIAS CHECK
Condition:
• Hold the set in horizontal state.
Connection:
oscilloscope
(AC range)
2 kΩ
MAIN board
TP629 (RF)
When observing the eye pattern, set the oscilloscope for AC range
and raise vertical sensitivity.
RF level :
0.6
±
0.2 Vp-p
VOLT/DIV : 50 mV (10 : 1 probe in use)
TIME/DIV : 500 nS
Test Points:
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9
D-VE45
5-1. IC PIN DESCRIPTIONS
• IC801 TMP88CM22AF-MIRXV-2 (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Pin Description
1 VSS — Ground
2 RMC_I I Infrared remote control signal input
3 FOK_I I Focus OK signal input from CXD3028R (IC601).
4 AGCPWM_O O AGC control pulse output
5 VCDON_O O Control signal output for video block power.
6 XV_RECV_O O Ready signal output to TMP87CM41U (IC803).
7 AMUTE_O O Analog audio muting ON/OFF signal control signal output (H: Mute ON)
8 I_LIMIT_O O Limit current circuitry control signal output
9 XRST_O O Reset signal output to CXD3028R (IC601). (L: Reset)
10 SCK_O O Serial data transfer clock signal output to CXD3028R (IC601).
11 (SENS) MSDTI_I I Serial data input from CXD3028R (IC601).
12 MSDTO_O O Serial data output to CXD3028R (IC601).
13 WAKEUP_O O WAKE-UP control signal output (for system standby reset)
14 AD_SEL I Plug-in detection signal input of AUDIO/VIDEO OUT jack.
15 AD_CHGMNT I Not used. (Fixed at “L” in this set)
16 COLOR_BAR_DET I Color-bar detection signal input
17 AD_BATMNT I Battery voltage detection input
18 AD_KEY I Key input from switches (A/D input).
19 AD_RMKEY I Not used. (Fixed at “L” in this set)
20 AD_DCINMNT I DC input voltage detection input (A/D input) DC input jack use/no-use detect input
21 WP_OPEN (SLVCD) I CD door open/close detection input
22 VREFL I Reference voltage (0 V) input for A/D converter.
23 VREFH I Reference voltage (+2 V) input for A/D converter.
24 VDD — Power supply pin (+2 V)
25 SCOR_I I Sub code sync detection input from CXD3028R (IC601).
26 GRSCOR_I I GRSCOR signal input from CXD3028R (IC601).
27 MIR_I I Not used. (Fixed at “H” in this set)
28 BEEP_O O Beep sound output to AN17880A (IC351).
29 XV_SEND_O O Request signal output to TMP87CM41U (IC803).
30 RMSCK_O O Communication clock to TMP87CM41U (IC803).
31 RMDATI_I I Communication data bus input from TMP87CM41U (IC803).
32 RMDATO_O O Communication data bus output to TMP87CM41U (IC803).
33 XV_REQ_I I Request signal input from TMP87CM41U (IC803).
34 RESERVE I Not used. (Open)
35 RESERVE I Not used. (Open)
36 COMPON_I I ESP switch input (L: OFF, H: ON)
37 (NTSC/PAL) I SYSTEM SELECT (NTSC/PAL) select input (L: NTSC, H: PAL)
38 RESERVE I Not used. (Open)
39 HOLD_I I HOLD switch input (H: HOLD on, L: HOLD off)
40 COLOR_BAR_SW I Color-bar recovery circuit. (Fixed at “H” in this set)
41 RESERVE I Not used. (Open)
42 XDE_O O Optical pick-up VCC control signal output (L: on)
43 XLAT_O O Serial data latch pulse output to CXD3028R (IC601). (for ESP)
44 XSOE_O O Output enable signal output to CXD3028R (IC601). (for ESP)
45 RESERVE O Not used. (Open)
46 XPOWLT_O O Latch output to TB2125F (IC401).
47 RESERVE I Not used. (Open)
48 XAPC_OFF_O O Not used. (Open)
49 VRST_O O Reset signal output to TMP87CM41U (IC803).
50 – 57 SEG14 – 7 O LCD drive segment output (Not used in this set)
SECTION 5
DIAGRAMS
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10
D-VE45
Pin No. Pin Name I/O Pin Description
58 – 64 SEG6 – 0 O LCD drive segment output
65 – 68 COM3 – 0 O LCD drive common output
69 – 71 V3 – 1 O LCD drive bias output
72, 73 C1, 0 O Capacitor connected terminal of LCD driver for voltage-up.
74 TEST I Test terminal for IC. (Fixed at “L” in this set)
75 TEST I Test terminal for IC. (Fixed at “L” in this set)
76 PWRSW_O O HEADPHONE AMP ON/OFF control signal output (L: ON)
77 RESERVE I Not used. (Open)
78 RESET_I I System reset signal input from TB2125F (IC401). (L: Reset)
79 XIN_I I Oscillation input
80 XOUT O Oscillation output (Not used in this set)
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11
D-VE45
•IC803 TMP87CM41U-3E64 (VIDEO ENCODER, VIDEO CONTROLLER)
Pin No. Pin Name I/O Pin Description
1 TEST NTSC I NTSC/PAL video system test mode input (L: PAL, H: NTSC)
(Normally, fixed at “H”in this set)
2 –8 P01 –07 O Not used. (Open)
9 (INT0) P10 O Not used. (Open)
10 (INT1) P11 O Not used. (Open)
11 (INT2/TC1) P12 O Not used. (Open)
12 (DVO) P13 O Not used. (Open)
13 (PPG) P14 O Not used. (Open)
14 (TC2) P15 O Not used. (Open)
15 P16 O Not used. (Open)
16 TEST MODE I Video system test mode input (L: Normal mode, H: Test mode)
(Normally, fixed at “L”in this set)
17 XCV_INT_I I Interruption request signal input from CL680T-D1 (IC701).
18 TEST I Test pin (Fixed at “L”in this set)
19 P21 (XTI) O Not used. (Open)
20 P22 (XTOUT) O Not used. (Open)
21 RESET_I I System reset signal input from TMP88CM22F (IC801). (L: Reset)
22 XIN_I I High frequency oscillator input
23 XOUT O High frequency oscillator output (Not used in this set)
24 VSS —Ground
25 –30 P30 –35 O Not used. (Open)
31 NC O Not used. (Open)
32 C_RESET O Reset signal output to CL680T-D1 (IC701). (L: Reset)
33 XCV_RDY_I I Ready signal input from CL680T-D1 (IC701).
34 VC_SEL_O O Address select signal output to CL680T-D1 (IC701).
35 VC_CLK_O O Serial clock signal output to CL680T-D1 (IC701).
36 DATA_C2V_I I Serial data signal input from CL680T-D1 (IC701).
37 DATA_V2C_O O Serial data signal output to CL680T-D1 (IC701).
38 UV_CLK_I I Serial clock signal input from TMP88CM22F (IC801).
39 DATA_U2V_I I Serial data signal input from TMP88CM22F (IC801).
40 DATA_V2U_O O Serial data signal output to TMP88CM22F (IC801).
41 XU_TX_REQ_I I Request signal input from TMP88CM22F (IC801).
42 XU_RX_RDY_I I Ready signal input from TMP88CM22F (IC801).
43 XV_TX_REQ_O O Request signal output to TMP88CM22F (IC801).
44 P53 (HPWM0) I Not used. (Open)
45 P54 (HPWM1) I Not used. (Open)
46 AVSS —Not used. (Open)
47 AVREF —Not used. (Open)
48 P60 (AIN0) O Not used. (Open)
49 P61 (AIN1) O Not used. (Open)
50 P62 (AIN2) O Not used. (Open)
51 P63 (AIN3) O Not used. (Open)
52 P64 (AIN4) O Not used. (Open)
53 P65 (AIN5) O Not used. (Open)
54 P66 (AIN6) O Not used. (Open)
55 P67 (AIN7) O Not used. (Open)
56 VDD —Digital power supply pin (+3.2 V)
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12
D-VE45
Pin No. Pin Name I/O Pin Description
57 P70 (AIN10) O Not used. (Open)
58 P71 (AIN11) O Not used. (Open)
59 P72 (AIN12) O Not used. (Open)
60 P73 (AIN13) O Not used. (Open)
61 P74 (AIN14) O Not used. (Open)
62 P75 (AIN15) O Not used. (Open)
63 P76 (AIN16) O Not used. (Open)
64 P77 (AIN17) O Not used. (Open)
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TEL 13942296513 QQ 376315150 892498299
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13
D-VE45
•IC701 CL680T-P-D1 (AUDIO/VIDEO MPEG DECODER)
Pin No. Pin Name I/O Pin Description
1NC—Not used. (Open)
2 VSS —Ground
3 CD_BCK I CD decode bit clock signal (2.8224 MHz) input from the CXD3028R (IC601).
4 CD_DATA I CD decode data input from the CXD3028R (IC601).
5 CD_LRCK I CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3028R (IC601).
6 CD_C2PO I CD decode C2 error data input from the CXD3028R (IC601).
7 –9NC—Not used. (Open)
10 –15 MD0 –5 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
16 VSS —Ground
17 MD6 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
18 VDD3 —Power supply pin (+3.3 V)
19 MD7 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
20 VSS —Ground
21 MD8 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
22 VDD3 —Power supply pin (+3.3 V)
23 –28 MD9 –14 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
29 MD15 I/O Two-way data bus with the program ROM (IC704).
30 –36 NC —Not used. (Open)
37 MCE O Chip enable signal output to the program ROM (IC704).
38 MWE O Write enable signal output to the DRAM (IC703).
39 VSS —Ground
40 CAS O Column address strobe signal output to the DRAM (IC703).
41 VDD3 —Power supply pin (+3.3 V)
42 RAS0 O Row address strobe signal output to the DRAM (IC703).
43 RAS1 O Row address strobe signal output (Not used in this set)
44, 45 MA10, 9 O Address signal output to the program ROM (IC704).
46 MA8 O Address signal output to the program ROM (IC704) and DRAM (IC703).
47 VSS —Ground
48 MA7 O Address signal output to the program ROM (IC704) and DRAM (IC703).
49 VDD3 —Power supply pin (+3.3 V)
50 –52 MA6 –4 O Address signal output to the program ROM (IC704) and DRAM (IC703).
53 VSS —Ground
54 MA3 O Address signal output to the program ROM (IC704) and DRAM (IC703).
55 VDD3 —Power supply pin (+3.3 V)
56 –58 MA2 –0 O Address signal output to the program ROM (IC704) and DRAM (IC703).
59 PGIO7 I/O Not used. (Open)
60 RESET I Reset signal input from TMP87CM41U (IC803). (L: Reset)
61 VDDMAX_IN I Fix the maximum input voltage each input pin and input/output pin.
62 –64 NC —Not used. (Open)
65 AGND_DAC —Ground (for D/A converter)
66 AVDD_DAC —Power supply pin (+3.3 V) (for D/A converter)
67 COMPOS_OUT O Composite video signal output
68 AGND_DAC —Ground (for D/A converter)
69 Y-OUT O Luminance video signal output (Not used in this set)
70 AVDD_DAC —Power supply pin (+3.3 V) (for D/A converter)
71 AGND_DAC —Ground (for D/A converter)
72 RREF I Fix the video signal output level control.
73 VREF O Reference voltage (+1.235 V) output
74 AVDD_DAC —Power supply pin (+3.3 V) (for D/A converter)
75 C-OUT O Chrominance video signal output (Not used in this set)
76 AGND_DAC —Ground (for D/A converter)
77 CLK_SEL (0) I Clock select 0 input (Fixed at “H”in this set)
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4
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8
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14
D-VE45
Pin No. Pin Name I/O Pin Description
78 CLK_SEL (1) I Clock select 1 input (Fixed at “H”in this set)
79 CLK_SEL (2) I Clock select 2 input (Fixed at “H”in this set)
80 VSS —Ground
81 CLK_SEL (3) I Clock select 3 input (Fixed at “L”in this set)
82 VDD3 —Power supply pin (+3.3 V)
83, 84 CLK_SEL (4), (5) O Clock select 4, 5 output (Fixed at “L”in this set)
85 AGND_PLL —Ground (for PLL system)
86 DA_XCK (16.934MHz) I Main reference clock signal (16.9344 MHz=384 fs) from CXD3028R (IC601).
87 AVDD_PLL —Power supply pin (+3.3 V) (for PLL system)
88 PGIO4 I/O Not used. (Open)
89 PGIO5 I/O Not used. (Open)
90 PGIO6 I/O Not used. (Open)
91 PGIO0 I/O Not used. (Open)
92 PGIO8 I/O Not used. (Open)
93 PGIO2/VSYNC/CSYNC O Vertical synchronized signal output (Not used in this set)
94 AVDD_PLL —Power supply pin (+3.3 V) (for PLL system)
95 VID_DAC_CK —Not used. (Fixed at “L”in this set)
96 PROC_CK —Not used. (Open)
97 NC —Not used. (Open)
98 AGND_PLL —Ground (for PLL system)
99 VSS —Ground
100 NC —Not used. (Open)
101 PGIO3/HSYNC I/O Not used in this set. (Open)
102 VDD3 —Power supply pin (+3.3 V)
103 PGIO1/VCK-OUT I/O Not used. (Open)
104 VSS —Ground
105 GCK I Normally, fixed at “L”in this set.
106 VCK_IN (27MHz) I Main clock for video signal processor input from Buffer (27 MHz) (IC705).
107 DA-EMP O Not used. (Open)
108 DA-LRCK O Digital audio L/R sampling clock signal (44.1 kHz) output to CXD3028R (IC601).
109 VDDMAX_OUT O Fix the maximum output voltage (+5 V) certain output
110 DA-DATA O Digital audio data output to CXD3028R (IC601).
111 DA-BCK O Digital audio bit clock signal (2.8224 MHz) output to CXD3028R (IC601).
112 HD-OUT_O O Serial data output to TMP87CM41U (IC803).
113 HRDY_O O Ready signal output to TMP87CM41U (IC803)
114 HINT_O O Interrupt request signal output to TMP87CM41U (IC803).
115 CDG-SCK I/O CD graphics serial clock input/output (Fixed at “L”in this set)
116 VSS —Ground
117 HCK_I I Serial data transfer clock signal input from TMP87CM41U (IC803).
118 VDD3 —Power supply pin (+3.3 V)
119 HD-IN_I I Serial data input from TMP87CM41U (IC803).
120 VDD3 —Power supply pin (+3.3 V)
121 HSEL_I I Command selection signal input from TMP87CM41U (IC803).
122 CDG-SDATA I CD graphics serial data input (Fixed at “L”in this set)
123 CDG-VFSY I CD graphics VFSY input (Fixed at “L”in this set)
124 CDG-SOS1 I CD graphics SOS1 input (Fixed at “L”in this set)
125 –128 NC —Not used. (Open)
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TEL 13942296513 QQ 376315150 892498299
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D-VE45
15 15
5-2. BLOCK DIAGRAM — CD SECTION —
RF AMP,
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR,
D-RAM CONTROLLER
IC601
13
99
98
97
38
39
83
78
2826 30 35
242523
3
2611 44
43101225
21
LPF
SIGNAL
PROCESSOR
BLOCK
MEMORY
CONTROLLER,
BUS BOOST
BLOCK
SERVO
BLOCK
MDS
44
42
43
MDS
MDP
C176
MDP
SENS
SCOR
17
SCOR_O
SDTO
RFAC
XSOE
R4M
XLAT
CLOK
AMUTE
FOK
FOK
R4M
WDCK
WFCK
NC
SDTO_I
SENS_O
CLOK_I
XLAT_I
XSOE_I
XSOE_O
GRSCOR_I
FOK_I
9
XRST
MSDTO_O
SCOR_I
(SENS)
MSDTI_I
SCK_O
XLAT_O
46
47
SFDR
XRST
RFDC
B
A
2
WDCK
WFCK
XTAO
XTAI
E
F
SRDR
TRDR
FRDR
FFDR
TFDR
FFDR
FRDR
59 F
62
61
A
B
58
71
RFDC
RFAC
E
50
51
SFDR
XTAO
XTAI
SRDR
48
49
35
36
13
14
61
TFDR
TRDR
OPTICAL PICK-UP
BLOCK (DAX-23E)
A
A
B
RF
E
F
B
RF
E
F
PD
VR
PD
LD
LD
DETECTOR
VCC
FOCUS
COIL
TRACKING
COIL
FI2
RI2
33
34
FI1
RI1
FI3
VINDET
RI3
16
PDL/RI4
TRDR
TFDR
FRDR
FFDR
SRDR
SFDR
15
PWM/FI4
APCREF
VCC1 +2V
FO2
RO2
FO3
RO3
RF2
INM2
RF21
PAPC
F+
F-
T+
T-
4AGCPWM_O
42 XDE_O
60
94
93
SYSTEM CONTROLLER
IC801 (1/4)
D-RAM
IC603
11
12
14
13
15
16
17
8
7
28
26
23
21
63
64
59
DRIVER
FO1
RO1
32
30
DRIVER
FO4
RO4
19
17
DRIVER
CONTROLLER
DRIVER
PD AMP
LD AMP
OPTICAL
PICK-UP
POWER
CONTROL
Q403,405
LEVEL
SHIFTER
60
FOCUS/TRACKING COIL DRIVER,
SPINDLE/SLED MOTOR DRIVER
IC401 (1/2)
NC
62
A
B
C
E
F
D
115 – 118
113
114
119
120
4
3
23
22
XRAS
XWE
XCAS
XOE
AOUT1
AIN1
LOUT1
D0-D3
D0-D3
A0-A9
A0-A9
RAS
WE
CAS
OE
4
10
2
4
10
6
5
4
89
91
87
PCMDI
SELECTOR
BCKI
LRCKI
3
2
1
88
90
86
PCMD CD_DATA
DA_DATA
CD_BCK
DA_BCK
CD_LRCK
DA_LRCK
BCK
LRCK
1-3, 5-7, 106-109
1, 2, 24, 25
5, 9-12, 14-18
79
XIN_I
MAIN BOARD (1/4)
102
103
104
LPF
AOUT2
AIN2
LOUT2
HPL
HPR
HPL
AU_R
AU_L
HPR
9
10
X601
16.9MHz
COMP OUT
11
12
10
SAW TOOTH
COMPARATOR
MDP
+
OPTICAL PICK-UP
POWER ON SWITCH
Q500
13
12
11
7
8
6
4
1
2
3
9
1
2
10
CN501
CN503
2
1
CN502
M501
SLED MOTOR
M
S+
S-
C+
C-
M502
SPINDLE MOTOR
M
• Signal Path
: CD PLAY
: VIDEO (VIDEO CD)
(Page 16)
(Page 16)
(Page 17)
(Page 16)
(Page 18)
(Page 16)
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4
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TEL 13942296513 QQ 376315150 892498299
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D-VE45
1616
5-3. BLOCK DIAGRAM —VIDEO SECTION —
D0 –D15
LEVEL SHIFT
IC708
1
2
3
CD_DATA
CD_BCK
CD_LRCK
CD_DATA
CD_BCK
CD_LRCK
DA-DATA
DA-BCK
DA-LRCK
DA-DATA
DA-BCK
DA-LRCK
DA_XCK(16.934MHz)
COMPOS_OUT
VCK_IN(27MHz)
CD-ROM
INTERFACE
CIRCUIT
MPEG
SYSTEM
DECODER MPEG
VIDEO
DECODER
MPEG
VIDEO
DECODER
VIDEO
PROCESS
CIRCUIT
AUDIO
INTERFACE
CIRCUIT
D-RAM/ROM INTERFACE CPU INTERFACE
HD-IN_I
HCK_I
HD-OUT_O
HSEL_I
HINT_O
HRDY_O
CAS
RESET
RAS0
MWE
MCE
MD0–MD15MA0–MA10
A0 –A10
A0 –A10
D0 –D15
A0 –A8
D8 –D14
A11–A17D0–D7
D0–D7
A0–A10
1, 4-6, 10-1221-23, 25-29
A0–A8
A0
2,3, 13-16, 17-20, 31
D0–D15
30
CE
UCAS
LCAS
RAS
WE
ROM(512K)
IC704
16-19, 22-26 2-5, 7-10, 31-34, 36-39
28 29 14 13
DRAM(4M)
IC703
DATA BUS
ADDRESS BUS
33
17
34
36
37
35
32
21
VC_CLK_O
DATA_V2C_O
DATA_C2V_I
VC_SEL_O
XCV_INT_I
XCV_RDY_I
C_RESET
RESET_I
38
UV_CLK_I
VREF
39
DATA_U2V_I
41
XU_TX_REQ_I
VREF
4.19MHz
16.9MHz
COMPARATOR
IC706,707
43
1
43
1
SWITCH
Q810
42
XU_RX_RDY_I SWITCH
Q811
40
XV_TX_REQ_O
22
XIN_I
43
DATA_V2U_O
17
19
14
18
6
5
4
VRST_O
RMSCK_O
RMDATO_O
XV_SEND_O
XV_RECV_O
RMDATI_I
29
32
30
49
COLOR_BAR_DET
16
6
31
XV_REQ_I
33
SYSTEM CONTROLLER
IC801(2/4)
VIDEO ENCODER
VIDEO CONTROLLER
IC803
4
3
5
6
1
3
2
7
5
110
111
108
86
67
106
10-15, 17, 19, 21, 23-2958-56, 54 52-50, 48, 46-44 6040
119 117112121114113
423837
AUDIO/VIDEO MPEG DECODER
IC701
42
IC709
4
2
IC705
OSC
X701
27MHz
B
F
G
D
H
A
IC706
IC707
Q814
MAIN BOARD (2/4)
•Signal Path
: CD PLAY
: VIDEO (VIDEO CD)
(Page 15)
(Page 15)
(Page 15)
(Page 17)
(Page 15)
(Page 18)
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TEL 13942296513 QQ 376315150 892498299
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D-VE45
17 17
5-4. BLOCK DIAGRAM —AUDIO SECTION —
7
2
76 28 39 14
AMUTE_O
RMC_I
PWRSW_O
BEEP_O
HOLD_I
SEG6
I
SEG0
COM3
I
COM0
AD_SEL
SYSTEM CONTROLLER
IC801 (3/4)
D601
Q815
HPR
HPL
AU_R
AU_L
V_OUT
OFF
ON
HOLD
VCPU +2V
TAP801
(TEST)
36
COMPON_I
ON
OFF
S804
ESP
LIN
RIN
BIAS
HEADPHONE AMP
IC351
8
9
LOUT
ROUT
VREF
6
5
4
PWRSW
MUTE
13
BEEP
11
PW SW
BEEP
MT SW
14
58 - 64 65 - 68
LIQUID CRYSTAL DISPLAY
PANEL
LCD801
LINE MUTE
Q301
LINE MUTE
CONTROL SWITICH
Q302
S803
37
(NTSC/PAL)
NTSC
PAL
S802
21
WP_OPEN
18
AD_KEY
S801
(OPEN)
TAP802
(OPEN)
11
10
9
C
19
7
8
J302
J701
i
MAIN BOARD (3/4)
S806-812
SYSTEM
SELECT
REMOTE
CONTROL
RECEIVER
IC905
SUB BOARD
G
AUDIO / VIDEO
OUT
•Signal Path
: CD PLAY
: VIDEO (VIDEO CD)
(Page 16)
(Page 15)
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2
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9
4
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8
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3
9
4
2
2
9
6
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9
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D-VE45
1818
5-5. BLOCK DIAGRAM —POWER SUPPLY SECTION —
SWITCHING
POWER
CIRCUIT 2
SWITCHING
POWER
CIRCUIT 6
SWITCHING
POWER
CIRCUIT 5
CHARGE
CONTROL
+2.5V
POWER
SWITCH
Q407
CHARGE
SWITCH
INTERFACE
CLK
OR OSC
AMP
BIAS
SAWTOOTH
GENERATOR
STANDBY
REFERENCE
DC IN
REGULATOR
Q401,405,408
SWITCH
Q402
52
50
49
57
42
5
6
8
7
9
53
55
56
38
40
41
2
37
CHG ON/OFF
BANDGAP
REFERENCE
(VREF)
4
SYSTEM CONTROLLER
IC801 (4/4)
17 20
58
AD_BATMNT
78
RESET_I
5
VCDON_O
8
I_LIMIT_O
13
WAKEUP_O
46
XPOWLT_O
AD_DCINMNT
VCC3 +3.3V
VCPU +2V
VCC1 +2V
VCC2 +2.6V
VREF
POWER CONTROLLER
IC401 (2/2)
B+
B-
WAKE-UP RESET
SWITCH
Q406
RESET SWITCH
IC403
OUT VIN
J401
DC IN 4.5V
!
L1H
L1L
NC
VCPU2 (2.0V)
VCPU1 (2.65V)
VCC1 (2.65V) VCC1
VCPU
48 INP1
54 STNG
VIN
NC
NC
NC
BATM1
BATM2
CHGSW
RS
DCIN
RF4
DC IN
VG
43
VLGO1
CHGMHT
SYNC
WAKEUP
CLOCK
DATA
16
LATCH
RSTB
VREF
44
DRY BATTERY
SIZE "AA"
(IEC DESIGNATION LR6)
2PCS,3V
D406
L408
L4
D401
L412
D823
E
B+ +3V
FOCUS/TRACKING COIL DRIVER
SPINDLE/SLED MOTOR DRIVER
(IC401) +3V,
HEADPHONE AMP
(IC351) +3V
MAIN BOARD (4/4)
1
1 3
L401
L402
Q812
Q411
Q413
PWM-PFM CONTROLLER
IC421
EXT VDD
5 2
FB CE
1 3
DC/DC
CONVERTER
Q409,410
SWITCH
Q490
SWITCH
Q412
15
12
13
18
H
++
(Page 15)
(Page 16)
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0
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2
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2
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8
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1
3
9
4
2
2
9
6
5
1
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9
2
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TEL 13942296513 QQ 376315150 892498299
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D-VE45
19 19
1V/div 2µsec/div
100mV/div 0.5µsec/div
1V/div 2msec/div
1V/div 0.05µsec/div
1V/div 5µsec/div
1V/div 0.05µsec/div
1V/div 0.5µsec/div
•Waveforms
3
2Vp-p
IC601 qj (SCOR_O)
6
0
2Vp-p
TP707 (LRCK)
6.9msec 23µsec
IC421 5(EXT) (VIDEO CD PB)
8
1.8Vp-p
9
2Vp-p
TP705 (BCK)
1V/div 0.1µsec/div
0.44µsec
27MHz
TP713 (27MHz)
(VIDEO CD PB)
16.9MHz
IC601 of (XTAO)
qa 1V/div 0.05µsec/div
qf
IC701 yj (COMPOS_OUT)
(VIDEO CD PB)
qd 500mV/div 0.5µsec/div
qs 1V/div 0.1µsec/div
3.4Vp-p
2Vp-p
3.5Vp-p
2.6Vp-p
0.44µsec
H
IC701 3(CD_BCK)
(VIDEO CD PB)
2
2Vp-p
TP405 (SCK)
1
2.6Vp-p
5.5µsec
1.9µsec
4
200mVp-p
TP633 (A), TP632 (B)
5
7
IC601 rd (MDP)
2Vp-p
3.8µsec
16.9MHz
IC701 ih (DA_XCK
(16.934MHz)) (VIDEO CD PB)
For schematic diagrams
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
• % : indicates tolerance.
•f: internal component.
•C: panel designation.
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS
AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
•A: B+ Line.
• Power voltage is dc 4.5V and fed with regulated dc power
supply from external power voltage jack.
• Voltages and waveforms are dc with respect to ground in
playback mode.
no mark : VIDEO CD PLAY
( ) : AUDIO CD PLAY
∗: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
J: CD
L: VIDEO
For printed wiring boards
•X: parts extracted from the component side.
•Y: parts extracted from the conductor side.
•a: Through hole.
•f: internal component.
•: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
Note: The components identified by mark 0or dotted line
with mark 0are critical for safety.
Replace only with part number specified.
VIDEO TEST DISC: HLV-401 (TGIS-3)
Part No.: J-6095-031-A
Playback track No.: 34 (Full field color bar 75%)
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B) pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A) parts face are indicated.
1V/div 2µsec/div
200mV/div 0.5µsec/div
0.6±0.2Vp-p
TP629 (RF)
1V/div 0.5µsec/div
2Vp-p
IC601 wg (CLOK_I)
1.9µsec
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
D-VE45
2020
5-6. PRINTED WIRING BOARDS —MAIN SECTION —•Refer to page 19 for Note.
1
A
B
C
D
E
F
G
H
I
J
23456789101112
1-681-215-
1-681-216-
1-681-216-
MAIN BOARD
(SIDE A)
SUB BOARD
(SIDE B)
SUB BOARD
(SIDE A)
VCC
VOUT
GND
VCC
VOUT
GND
LCD801 LCD MODULE
OPTICAL
PICK-UP
BLOCK
DAX-23E
M502
SPINDLE
MOTOR
OFF ON
HOLD
RED
BLK
M501
SLED
MOTOR
WHT
BLK
BLK
RED
BLK
WHT
21 21
Ref. No. Location
D403 C-7
D404 I-6
D409 J-5
D501 B-7
D502 B-7
D806 C-8
IC351 D-10
IC421 C-8
IC603 C-8
IC905 G-1
Q401 I-5
Q403 E-8
Q404 E-8
Q405 I-5
Q408 J-5
Q409 C-7
Q410 C-7
Q413 C-8
Q500 E-9
Q812 D-9
Q815 E-3
•Semiconductor
Location (Side A)
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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